General Description
The DS1861 is a laser-driver control IC designed to
reduce the production cost of fiber optics circuits by
eliminating multiple temperature tests. It works with
nearly all laser-driver ICs to provide automatic power
control (APC) and automatic extinction ratio control
(AERC), which improves the performance of the system
over temperature and aging. It also has built-in monitor-
ing capability to provide early fault detection, which can
be configured to latch the IC into a shutdown condition.
Settings programmed into the DS1861 are stored in
password-protected EEPROM memory, which write-
protects calibration data. Programming is accom-
plished through an I2C-compatible interface, which can
also be used to read diagnostic information.
Applications
Optical Transceivers
Optical Transponders
Features
♦Automatic Power Control (APC)
♦Automatic Extinction Ratio Control (AERC)
Across Temperature and Laser Aging
♦Works in AC-Coupled Laser Systems
♦Configurable Latched Automatic Shutdown with
Tx-Fault and Tx-Disable
♦Programmable Fast Alarm Conditions
♦I2C-Compatible Serial Interface Allows Up to Eight
Devices on the Same Serial Bus
♦Operates Over Wide Supply-Voltage Range
♦Nonvolatile Memory for Device Settings
♦Small, 14-Pin TSSOP Package
♦-40°C to +95°C Operating Temperature Range
DS1861
Full Laser Control with Fault Management
______________________________________________ Maxim Integrated Products 1
TX-D
GND
VCC
N.C.
A2
A1
TX-F
SDA
SCL
4.7kΩ
4.7kΩ
VCC
4.7kΩ
N.C.
DS1861
A0
30kΩ
VCC VCC
BIASSET BIAS
IBIASSET
IMODSET
MOD
OUT
BIAS
LASER DRIVER
MODSET
BMD
IBMD 1nF
MAX3736
Typical Operating Circuit
Rev 0; 5/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configuration appears at end of data sheet.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS1861E
-40°C to +95°C
14 TSSOP (173 mils)
DS1861E+
-40°C to +95°C
14 TSSOP (173 mils)
+Denotes lead free.
DS1861
Full Laser Control with Fault Management
2_____________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(VCC = +2.85V to 5.5V, TA= -40°C to +95°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCC, SDA, and SCL
Pins Relative to Ground.....................................-0.5V to +6.0V
Voltage Range on A0, A1, A2, Tx-Fault, Tx-Disable,
BIASSET, MODSET, and BMD Relative to
Ground.................-0.5V to (VCC + 0.5V), not to exceed +6.0V
Operating Temperature Range ...........................-40°C to +95°C
EEPROM Programming Temperature Range .........0°C to +70°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature .......................................See IPC/JEDEC
J-STD-020 Specification
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Supply Voltage VCC (Note 1)
2.85 5.50
V
Input Logic 1
(SDA, SCL, A2, A1, A0)VIH1 0.7 x
VCC
VCC +
0.3 V
Input Logic 0
(SDA, SCL, A2, A1, A0)VIL1
-0.3
+0.3 x
VCC
V
Input Logic 1 (TX-D) VIH2 1.5 V
Input Logic 0 (TX-D) VIL2 0.9 V
Voltage at BIASSET and
MODSET 0.6 3.0 V
ITH/IAPC Ratio (Note 2) 7:1
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to 5.5V, TA= -40°C to +95°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Supply Current ICC (Note 3) 5 7 mA
Input Leakage ILI -1 +1 µA
Output Leakage (TX-F, SDA) ILO High impedance -1 +1 µA
VOL1 3mA sink current 0 0.4
Low-Level Output Voltage (TX-F,
SDA) VOL2 6mA sink current 0 0.6 V
I/O Capacitance CI/O 10 pF
Input Current Each I/O Pin 0.4 < VI/O < 0.9 x VDD -10
+10
µA
DS1861
Full Laser Control with Fault Management
_____________________________________________________________________ 3
ANALOG OUTPUT CHARACTERISTICS
(VCC = +2.85V to 5.5V; TA= -40°C to +95°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
BIASSET Current Range
IBIASSET 0.01 1.50
mA
BIASSET Shutdown Current 10 100 nA
MODSET Current Range
IMODSET 0.01 1.20
mA
MODSET Shutdown Current 10 100 nA
APC Calibration Accuracy
(Error in Setting IBMD)(Note 4) 3 %
APC Temp Drift
(% Drift in IBMD)(Note 5) ±2 ±4 %
40µA < IM OD S E T < 100µA at + 25oC ( N ote 6) ±1 ±4
100µA < IM OD S E T < 400µA at + 25oC ( N ote 6) ±1 ±3N Temp Drift
IM OD S E T > 400µA at + 25oC ( N ote 6) ±1
±2.75
%
Extinction Ratio Calibration
Accuracy At 10dB extinction ratio
0.22
dB
Loop Transient Settling Error IBIASSET and IMODSET after 300ms 3 %
Extinction Ratio Update
Frequency fERU 525Hz
Peak BMD Disturbance Current IDIST Percent increase above IBMD
3.33 3.60
%
ANALOG INPUT CHARACTERISTICS
(VCC = +2.85V to 5.5V, TA= -40°C to +95°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BMD Current—Source or Sink (±)
ISET (Note 7)
0.05 1.50
mA
BMD Voltage VBMD IBMD = 0.5x to 2x ISET 1.0
1.24
1.5 V
Gain = 16 175 265 350
Gain = 8 350 530 700
Gain = 4 700 1060 1400
Gain = 2 1400 2120 2800
BMD Input Resistance RBMD IBMD = ISET ±10% (ISET)
Gain = 1 2800 4240 5600
Ω
Reference Voltage VREF
1.24
V
DS1861
Full Laser Control with Fault Management
4_____________________________________________________________________
FAST ALARMS AND VCC MONITOR CHARACTERISTICS
(VCC = +2.85V to 5.5V, TA= -40°C to +95°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
High Bias Alarm LSB 255 settings (includes off) 8.2 µA
High Bias Alarm Threshold
Accuracy High bias settings > 100µA 10 %
LTXP_Thres (bin)
XXXXX000 LTXP Alarm OFF
XXXXX001 Do not use
XXXXX010
0.81
XXXXX011
0.76
XXXXX100
0.54
XXXXX101
0.41
XXXXX110
0.28
LTXP Alarm Threshold Multiplier
(ISET Multiplier Shown, Note 8)
XXXXX111
0.14
mA/mA
HTXP_Thres (bin)
XXXXX000 HTXP Alarm OFF
XXXXX001 Do not use
XXXXX010
1.30
XXXXX011
1.43
XXXXX100
1.56
XXXXX101
1.69
XXXXX110
1.82
HTXP Alarm Threshold Multiplier
(ISET Multiplier Shown, Note 8)
XXXXX111
1.95
mA/mA
VCC Power Good VPOA
2.15 2.70
V
Vcc Fault Deassert Delay tPOAR
360 700
µs
Digital Power-On Reset Voltage VPOD 1.0 2.2 V
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to 5.5V, TA= -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 14)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
SCL Clock Frequency fSCL (Note 9) 0
400
kHz
Bus Free Time Between Stop and
Start Conditions tBUF 1.3 µs
Hold Time (Repeated) Start
Condition
tHD:STA
0.6 µs
Low Period of SCL tLOW 1.3 µs
High Period of SCL tHIGH 0.6 µs
Data Hold Time
tHD:DAT
0 0.9 µs
DS1861
Full Laser Control with Fault Management
_____________________________________________________________________ 5
I2C AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.85V to 5.5V, TA= -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 14)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Data Setup Time
tSU:DAT 100
ns
Start Setup Time tSU:STA 0.6 µs
SDA and SCL Rise Time tR(Note 10) 20 +
0.1CB300
ns
SDA and SCL Fall Time tF(Note 10) 20 +
0.1CB300
ns
Stop Setup Time
tSU:STO
0.6 µs
SDA and SCL Capacitive
Loading CB(Note 10)
400
pF
EEPROM Write Time tW(Note 11) 10 20 ms
POWER-SUPPLY AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to 5.5V, TA= -40°C to +95°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Supply Slew Rate
dV/dt ↑ Vcc
VCC = 0 to 5.5 (Note 12) 30
V/ms
SHUTDOWN AND FAULT AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to 5.5V, TA= -40°C to +95°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
BIASSET and MODSET Disable
(10% of Active Level) tOFF From rising edge of TX-D 5 µs
APC Recovery From Normal
Disable (to IBMD 90% Level) tON:B From falling edge of TX-D (Note 13) 0.8 ms
Modulation Recovery From
Normal Disable (to IMODDRIVER
90% Level)
tON:M From falling edge of TX-D (Note 14) 0.2 ms
APC Recovery After Power-Up or
Shutdown (to IBMD 90% Level) tINIT:B (Note 13) 0.8 ms
Modulation Recovery After
Power-Up or Shutdown (to
IMODDRIVER 90% Level)
tINIT:M
100
ms
Fault Reset Time (to TX-Fault = 0)
tINIT:F 100
150
ms
Shutdown Time (to 10% IBIASSET,
10% IMODSET, TX-F High) tFAULT
IBMD > HTXP Threshold, or
IBIAS ≥ HBIAS Threshold, or
IBMD < LTXP Threshold
50 µs
Minimum Reset Pulse Width tRESET 1µs
DS1861
Full Laser Control with Fault Management
6_____________________________________________________________________
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to 5.5V, TA= 0°C to +70°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Writes +70°C (Note 15)
50,000
Note 1: All voltages are referenced to ground. Currents into the IC are positive, out of the IC negative.
Note 2: The threshold current (ITH) to light producing current (IAPC) ratio should remain below 7:1. This limits overshoot to under
10% and ensures the data sheet accuracies are met.
Note 3: Max ICC is dependent on SCL clock rates.
Note 4: Calibration accuracy refers to the accuracy achieved at the end of calibration.
Note 5: This specification refers to the error contribution due to this chip, and does not include the error due to the drift of the mon-
itor-diode responsivity with temperature.
Note 6: The N Temperature Drift specification includes error caused by changes in modulation current due to system temperature
variation. After the part is calibrated at +25°C, this spec allows for modulation current changes of up to +65% with increas-
ing temperature and -25% with decreasing temperature. Larger modulation current variations would have increased drift,
but this range accommodates a reasonable change (up to 2x across temperature) in laser diode slope efficiency.
Calibration is assumed to take place at +25°C for the purposes of this spec. This does not imply that the system must be
calibrated at +25°C.
Note 7: Within the APC calibration accuracy.
Note 8: Values in the table are multiplied times the IBMD set point (set by APC register) to determine the threshold limits.
Note 9: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard-mode timing.
Note 10: CB—total capacitance of one bus line in pF.
Note 11: EEPROM write begins after a stop condition occurs.
Note 12: If the supply ramps up at slew rates within the specification, the device will be functional after VCC exceeds VPOA and the
power-up time (tPOAR) elapses.
Note 13: On power-up and when TX-D is deasserted, IBIASSET ramps up from zero current to its final value with ≤10% APC over-
shoot during the transient.
Note 14: Modulation is applied at the level it was at before disable. If the time from disable is so long that the laser has cooled
down, then meeting ER accuracy is contingent upon completion of the first ER update. The MODLOAD enable bit and
MODLOAD register can be used to load a predetermined IMODSET value if desired. See the Detailed Register Descriptions
section for more information.
Note 15: This parameter is guaranteed by design.
DS1861
Full Laser Control with Fault Management
_____________________________________________________________________ 7
VCC > VPOA
tPOAR
tINIT:F
tINIT:B
tINIT:M
TX-D
TX-F
IBIASSET
IMODSET
Timing Diagrams
Figure 1. Power-Up Timing with TX-D Not Asserted (Including Hotplug)
VCC > VPOA
TX-D
TX-F
IBIASSET
IMODSET
tINIT:B
tINIT:M
tINIT:F
Figure 2. Power-Up Timing with TX-D Asserted
DS1861
Full Laser Control with Fault Management
8_____________________________________________________________________
TX-D
*TX-F WILL ASSERT IF THE HTXP ALARM IS TRIGGERED WHILE THE BIAS CURRENTS
ARE DISABLED. THE LTXP ALARM IS MASKED WHILE TX-D IS ASSERTED.
FIRST CONTROL LOOP ADJUSTMENT OF
IMODSET AFTER TX-D IS DEASSERTED
TX-F*
IBIASSET
IMODSET
tOFF
tOFF
tON:M
tINIT:M
tON:B
Timing Diagrams (continued)
Figure 3. TX-D Timing During Normal Operation
OCCURENCE
OF FAULT
TX-D
TX-F
IBIASSET
IMODSET
tFAULT
tFAULT
tFAULT
Figure 4. Detection of Transmitter Safety Fault Condition
DS1861
Full Laser Control with Fault Management
_____________________________________________________________________ 9
tRESET
tINIT:B
tINIT:F
tINIT:M
OCCURENCE
OF FAULT
TX-D
TX-F
IBIASSET
IMODSET
Timing Diagrams (continued)
Figure 5. Successful Recovery from Transmitter Safety Fault Condition
tRESET
tINIT:M
OCCURENCE
OF FAULT
TX-D
TX-F
IBIASSET
TX-F REMAINS HIGH DURING
AN UNSUCCESSFUL RECOVERY
DUE TO THE INTERNAL TIMER. IBIASSET AND IMODSET MAY HAVE
TO BIAS THE PART TO RECREATE THE
SHUTDOWN CONDITION.
IMODSET
Figure 6. Unsuccessful Recovery from Transmitter Safety Fault Condition
DS1861
Full Laser Control with Fault Management
10 ____________________________________________________________________
Typical Operating Characteristics
(VCC = +5.0V, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DS1861 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.354.854.353.853.35
5.4
5.9
6.4
6.9
4.9
2.85
DPOL = 0, TA = +85°C
DPOL = 0, TA = +25°C
DPOL = 0, TA = -40°C
DPOL = 1, TA = +25°C
DPOL = 1, TA = +85°C
DPOL = 1, TA = -40°C
GAIN = 4, APC = 16, EXT. LOOP GAIN = 1
SUPPLY CURRENT
vs. TEMPERATURE
DS1861 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7.0
6.0
-40 85
DPOL = 0
DPOL = 1
VCC = 5.0V, APC = 4, GAIN = 16
IBMD DRIFT
vs. SUPPLY VOLTAGE
DS1861 toc03
SUPPLY VOLTAGE (V)
IBMD DRIFT (%)
5.354.854.353.853.35
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
2.85
TA = 25°C, APC = 16, GAIN = 4
DPOL = 1
DPOL = 0
IBMD DRIFT
vs. TEMPERATURE
DS1861 toc04
TEMPERATURE (°C)
IBMD DRIFT (%)
603510-15
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
-1.8
-40 85
DPOL = 1
DPOL = 0
VCC = 5.0V, APC = 16, GAIN = 4
TX-F OUTPUT CURRENT
vs. OUTPUT VOLTAGE
DS1861 toc05
OUTPUT VOLTAGE
OUTPUT CURRENT (mA)
0.90.80.70.60.50.40.30.20.1
5
10
15
20
25
30
0
01.0
VCC = 2.85V
N DRIFT
vs. TEMPERATURE
DS1861 toc06
TEMPERATURE (°C)
N DRIFT (%)
85603510-15
-2
-1
0
1
2
3
-3
-40
IMODSET = 100µA
IMODSET = 400µA
IMODSET = 40µA
VCC = 2.85V, DPOL = 0, N = 30
DS1861
Full Laser Control with Fault Management
____________________________________________________________________ 11
Pin Description
11 ___________________________________________________________________________________________________
PIN NAME FUNCTION
1SDA Serial Data Input/Output. I2C bidirectional data pin, which requires a pullup resistor to realize high
logic levels.
2SCL Serial Clock Input. I2C clock input.
3TX-F Transmit Fault Output. Open-collector output that indicates an alarm condition has occurred. A pullup
resistor is required on this pin to realize high logic levels.
4TX-D Transmit Disable Input
5, 8 N.C. No Connection
6BMD Photodiode Current Input
7GND Ground
9
BIASSET
Bias Current Output
10 A0
11 A1
12 A2
I2C Address Inputs. These inputs determine the slave address of the device. The slave address in
binary is 1010A2A1A0.
13
MODSET
Modulation Current Ouput
14 VCC Power Supply
DS1861
Full Laser Control with Fault Management
12 ____________________________________________________________________
Functional Diagram
WITH SETTINGS
PASSWORD
PROTECTION
DISTURBANCE
CURRENT
USER EEPROM
(8 BYTES)
Σ
I2C-COMPATIBLE
INTERFACE AUTOMATIC
POWER CONTROL
QUICK TRIP
FAULT MONITOR
AUTOMATIC
EXTINCTION
RATIO CONTROL
NONVOLATILE
NONVOLATILE
NONVOLATILE
CURRENT
SINK/SOURCE
ISET
VREF
IBMD
RBMD
IBMD
IBMD
IB
IB
IDIST
BIASSET
MODSET
BMD
CURRENT
SENSE
DS1861
VCC
VCC
SDA
SCL
A2
A1
A0
TX-D
TX-F
GND
VCC
Detailed Description
Automatic Power Control
The DS1861 APC is accomplished by adjusting the
bias current (IBIAS) until the feedback current (IBMD)
from a photodiode matches the value determined by
the APC register. The relationship between the APC
register and IBMD is given by:
ISET = 1.525µA Gain (APC<4:0> + 32)
where APC<4:0> is the numerical value determined by
the five least significant bits of the APC register, and
the gain value is determined by the upper three bits of
the APC register, as shown in the truth table below. See
Figure 7 for a graph of the BMD current-set point vs.
the APC register value.
The BMD pin appears to the photodiode as a voltage
source (VREF) with an output resistance equal to RBMD
in parallel with a current source (ISET) equal to the IBMD
setpoint. When the control loop is at its steady state
value, the voltage at the BMD pin (VBMD) is equal to
VREF, and the BMD current will all be sourced by ISET.
When an imbalance causes the feedback current to differ
from the set current, the difference in the currents causes
the DS1861 to adjust the BIASSET and the MODSET cur-
rents to new settings so the input current matches the
set current. During transient periods, the difference in
the ISET and IBMD currents causes a small current to
pass through RBMD. This causes a slight increase or
decrease in the VBMD voltage. The current source can
sink and source current, which must be configured using
the DPOL bit in the control byte for proper operation.
This allows the photodiode to be referenced to either
VCC or GND. See the Memory Map and Detailed
Register Descriptions sections for more detail.
APC<7:5> GAIN
000 1
001 2
010 4
011 8
1xx 16
Reading the BIASSET and MODSET
Registers
The IBIASSET and IMODSET currents are generated by
embedded 18-bit and 12-bit DACs, respectively, and
their output currents can be read when the DS1861 has
been halted using the halt bit, and the password has
been entered. See the Detailed Register Descriptions
section for information on calculating the output current
from the register’s value.
Automatic Extinction Ratio Control
The DS1861 injects a small disturbance current to mea-
sure the gain (light/mA) of the laser driver and laser
diode pairing. This control methodology makes the
extinction ratio insensitive to changes in the photodi-
ode’s responsivity due to temperature and aging
effects, as long as the ratio of the laser driver’s bias
current gain (AD) and modulation current gain (AM)
remains constant (Figure 8).
The disturbance current is automatically scaled as the
BMD current-set point is adjusted, so the peak distur-
bance current always increases IBMD by approximately
3.3%. See Figure 9 for details.
To understand how the MODSET and BIASSET currents
control the extinction ratio, the extinction ratio equation
(extinction ratio = P1/P0) must first be expressed in
terms of the modulation power (PMOD) and average
power (PAVG). Figure 10 shows the current and power
levels that correspond to the optical logic 1 (P1) and
logic 0 (P0) levels.
Extinction Ratio P
P
PP
PP
AVG MOD
AVG MOD
== +
−
1
0
1
2
1
2
DS1861
Full Laser Control with Fault Management
____________________________________________________________________ 13
0
0.375
0.750
1.500
1.125
0 12864 192 255
DS1861 fig07
APC REGISTER SETTING (DECIMAL)
ISET (mA)
Figure 7. BMD Current Setpoint vs. APC Register Setting
DS1861
BIASSET IBIASSET BIASREF
MODREF
BIAS
MOD
IMODSET
PHOTO-
DIODE
LASER DRIVER
LASER
DIODE
LIGHT
*ID = IBIAS IMOD
±1
2
AD
AC-COUPLING
CIRCUITRY
IBIAS
ID*
IMOD
AM
IBMD
MODSET
BMD
Figure 8. AERC Block Diagram
DS1861
Once the extinction ratio is expressed as a function of
the average power and the modulation power, the
equation can then be written in terms of the modulation
and average power currents. The modulation current
(IMOD) is defined as the difference between the I1and
I0currents (IMOD = I1- I0). The average power current
(IAPC) is the arithmetic mean of the I1and I0currents
referenced to the threshold current (IAPC = 1/2I1 +
1/2I0 - ITH). After defining these currents, the equation
can now be rewritten as the following equations.
The APC loop is already controlling IAPC to keep the
average power at a constant value, so the DS1861 out-
puts IMODSET so that IMOD/IAPC remains constant to
control the extinction ratio. The DS1861 determines the
IMOD/IAPC ratio according to the following formula,
where N is a variable gain that can be used to adjust
the extinction ratio.
Substituting into the previous extinction ratio equation
yields the extinction ratio as a function of N.
Extinction Ratio
NA
A
NA
A
NA
A
NA
A
M
D
M
D
M
D
M
D
=
+× ×
××
=
+
−−
11
230
11
230
60
60
I
I
NxA
A
MOD
APC
M
D
=30
Extinction Ratio
II
II
I
I
I
I
APC MOD
APC MOD
MOD
APC
MOD
APC
=+=
+×
×
−−
1
2
1
2
11
2
11
2
Full Laser Control with Fault Management
14 ____________________________________________________________________
Figure 9. BMD Disturbance Current
Figure 10. Laser Diode Bias Current Definitions
DS1861 fig09
TIME
BMD CURRENT
IDIST
1
fERU
DS1861 fig10
CURRENT (mA)
P0
IMOD
2
IMOD
2
I1
I0
P1
AVERAGE
POWER PMOD
IMOD
IAPC
ITH
Figure 11 shows the extinction ratios (expressed in
decibels) as a function of N for several AM/ADratios.
Note the actual extinction ratio value is determined by
the ratio AM/ADin addition to N. If the AM/ADratio
varies due to voltage, temperature, or aging effects, it
becomes an additional error source when determining
the overall extinction ratio variance. The DS1861 is
meant to be used with a monolithic laser driver, where
AMand ADare generated on the same chip, so
changes in the ratio of AMto ADare minimal.
The N value itself is determined by the extinction ratio
register. There are two components of the ER register
used to calculate N. The range select bit (RSEL), which
selects the high (RSEL = 1) or low (RSEL = 0) range of
N, is the MSB of the register. The lower seven bits of
the register (ER<6:0>) determine the value of N within
the selected range. The value of N is given by:
The ER<6:0> value should be programmed to values
between 28 and 104 (decimal), regardless if the high or
low range is selected, to ensure that the N value
remains accurate and constant as intended. These lim-
its allow the N values of the high and low range to over-
lap to ensure that all N values can be attained, but
prevents potential errors that can be caused by using
the extremes of each RSEL range. Figure 12 shows the
N values as a function of the ER register setting.
The Convergence Algorithm and
Overshoot Control
The DS1861 uses a tiered slew-rate control system that
adjusts the DAC update rate and the number of LSBs it
increases/decreases per update cycle when the control
loop is seeking to converge to its steady state value. For
the APC loop, it makes its decision on the required con-
vergence rate based on the percent error between the
present BMD current and the BMD current-set point.
The modulation current slew rate is adjusted based
solely on the difference between its present code and
the code-set point that is determined by the AERC cir-
cuitry. Both update rates are designed to prevent any
overshoot during large set-point changes in excess of
10%, which assumes (see the following) the ratio of the
laser diode’s threshold current (ITH) to the average
power current (IAPC) is below 7:1. Most systems do not
exhibit any overshoot when using the DS1861.
:
:
N
ER when RSEL
ER when RSEL
=
<>+ =
<>+ =
60 32
20
60 32 1
DS1861
Full Laser Control with Fault Management
____________________________________________________________________ 15
EXTINCTION RATIO (AM/AD = 1.2)
vs. ER SETTING
DS1861 fig11a
ER SETTING (DECIMAL)
EXTINCTION RATIO (dB)
9680644832
5
10
15
20
25
0
16 112
RSEL = 0
EXTINCTION RATIO (AM/AD = 0.8)
vs. ER SETTING
DS1861 fig11b
ER SETTING (DECIMAL)
EXTINCTION RATIO (dB)
9680644832
5
10
15
20
25
0
16 112
EXTINCTION RATIO (AM/AD = 0.4)
vs. ER SETTING
DS1861 fig11c
ER SETTING (DECIMAL)
EXTINCTION RATIO (dB)
9680644832
5
10
15
20
25
0
16 112
RSEL = 0
RSEL = 0
RSEL = 1
RSEL = 1
Figure 11. Typical Extinction Ratios vs. N Codes
DS1861
The average power current is defined as the difference
between the current required to reach the average
power output and the threshold current of the laser
diode. The average power output is defined as the
mean of the power used to transmit a high logic level
(P1) and the power used to transmit a low power level
(P0). Figure 10 graphically shows the threshold and
average power currents as they relate to the light out-
put of a laser diode.
Fault Monitors and Shutdown
The DS1861 has a VCC monitor plus three programma-
ble quick-trip (QT) fault monitors (Figure 13) that can
trigger the TX-F output. The QTs monitor for high trans-
mit power (HTXP), low transmit power (LTXP), and for
high bias current (HBIAS). All the QTs feature program-
mable trip levels, an alarm disable, and a shutdown
enable to determine if the enabled QT alarm shuts off
the IBIASSET and IMODSET outputs.
VCC is monitored against two internal voltage levels to
ensure that VCC is at an adequate level for the part to
Full Laser Control with Fault Management
16 ____________________________________________________________________
Figure 12. Setting N Using the ER Register
DS1861 fig12
ER REGISTER SETTING (DECIMAL)
N
104 10527 28
16
32
48
64
80
96
112
128
144
0
127
INVALID INVALID
INVALID ER
SETTINGS SHADED
HIGH RANGE (RSEL = 1)
LOW RANGE (RSEL = 0)
Figure 13. Quick Trip Logic Diagram
BIASSET
RST
OUT
IN
IN
S
R
DQ
Q
FAULT RESET TIMER
(130ms)
OUT
QUICKSTART
MODLOAD
ENABLE
TX-F
SHUTDOWN
FLAG
CONTROL
LOGIC MODSET
S
R
DQ
Q
S
HBIAS
SHUTDOWN
LTXP ALARM
LTXP ENABLE
HTXP ALARM
HTXP ENABLE
HBIAS ALARM
HBIAS ENABLE
TX-D
NOTE: POA IS HIGH WHEN VCC < VPOA.
SOFT TX-D
POA
HTXP
SHUTDOWN
LTXP
SHUTDOWN
R
DQ
Q
communicate over the I2C bus and for the analog cir-
cuitry to function properly. The first monitoring level, the
power-on digital voltage (VPOD), inhibits the part’s I2C
functionality when VCC is below VPOD. The second
monitoring level is the power-on analog voltage (VPOA).
The DS1861 disables IBIASSET and IMODSET and
asserts the TX-F output whenever VCC is below VPOA.
Both VCC monitors are nonmaskable, so there is no way
to force the chip to function when VCC is not at an ade-
quate level to assure the DS1861 operates properly.
The high and low transmit power quick-trip thresholds
are each programmed by 3 bits that select one of
seven different levels as a function of the expected
IBMD current. Each QT monitor can be disabled by pro-
gramming all three bits to zero. Disabling a QT by pro-
gramming its control bits to zero prevents the QT alarm
flags from ever being set, which consequently prevents
that monitor from asserting the TX-F output, latching the
device into a shutdown condition, or setting the alarm
bits in the Status register. The HTXP and LTXP enable
bits can be used to prevent the transmit power level
QTs from causing shutdown while allowing the TX-F
output to be set to flag the system of a transmit power
fault condition. Figure 13 shows the shutdown logic.
Tables 1 and 2 show the QT thresholds as a function of
IBMD current-set point.
The high-bias, quick-trip alarm features an 8-bit thresh-
old setting with an LSB of 8.2µA. Programming the
HBIAS threshold to zero inhibits the HBIAS alarm flag,
preventing TX-F from being asserted, the HBIAS alarm
from causing a shutdown, and the HBIAS alarm bit in
Status from being set. The HBIAS enable bit can be
used to prevent shutdown from occurring while allow-
ing the HBIAS alarm flag to trigger TX-F.
Password Protection
The DS1861 has two 16-bit password entry registers
(used as a 32-bit value) and two 16-bit password regis-
ters (used as 32-bit value) that can be used to write-pro-
tect all the configuration settings. The password entry
registers, PWE High and PWE Low, are the locations
where the user enters the password to disable the write
protection and change the device settings. The pass-
word bytes, PW High and PW Low, set the password to a
new value. When the device is write-protected, the only
bytes that can be written are the password entry bytes.
To secure the password, the PW bytes always read as
0s when the PWE bytes do not match the PW bytes.
Once the correct password has been entered into the
PWE bytes, the password can also be read from the
PW registers. Because the PWE bytes can be read all
the time, it is recommended that the PWE bytes are
written to all 1s once the desired settings are modified
to prevent anyone from simply reading PWE to attain
the password. The PWE bytes are SRAM, so they reset
themselves to 1s if VCC drops below VPOA.
In addition to write protection, the password must also
be entered and the DS1861 must be HALTed to read
the IBIASSET and IMODSET DAC codes. See the
Reading the BIASSET and MODSET Registers section
for more information about reading the DAC codes.
DS1861
Full Laser Control with Fault Management
____________________________________________________________________ 17
HTXP_Thresh<2:0>
HIGH-TRANSMIT POWER
THRESHOLD (ISET)
000 Disabled*
001 Do not use
010 1.30
011 1.43
100 1.56
101 1.69
110 1.82
111 1.95
Table 1. HTXP Threshold Settings
*Disabled inhibits the HTXP QT from causing a shutdown or
asserting TX-F.
LTXP_Thresh<2:0>
LOW-TRANSMIT POWER
THRESHOLD (ISET)
000 Disabled*
001 Do not use
010 0.81
011 0.76
100 0.54
101 0.41
110 0.28
111 0.14
Table 2. LTXP Threshold Settings
*Disabled inhibits the LTXP QT from causing a shutdown or
asserting TX-F.
DS1861
Full Laser Control with Fault Management
18 ____________________________________________________________________
DS1861 Memory Map
WORD 0 WORD 1 WORD 2 WORD 3
BASE
ADDR
ROW
NAME
BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E
BYTE 7/F
78h Password
Entry Status SRAM SRAM PWE High PWE Low
Reserved
B0h
APC Config User EE User EE
APC
User EE
ER (N) MODLOAD Control
B8h
Fast Comp
HTXP
Threshold
LTXP
Threshold
HBIAS
Threshold User EE User EE
User EE User EE
User EE
C0h
Password Reserved Reserved Reserved
PW High PW Low
Reserved
D0h
DAC Codes Reserved
IBIASSET
Code
Reserved Reserved Reserved Reserved
IMODSET Code
EXPANDED BYTES
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BYTE
ADDR BYTE NAME bit15 bit14 bit13 bit12 bit11 bit10 bit9bit8bit7bit6bit5bit4bit3bit2bit1bit0
78h Status Shutdown
Flag
HTXP
Shutdown
LTXP
Shutdown
HBIAS
Shutdown POA HTXP
Alarm
LTXP
Alarm
HBIAS
Alarm
7Bh PWE High 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216
7Dh PWE Low 215 214 213 212 211 210 29282726252423222120
B2h APC GAIN2 GAIN1 GAIN0 2423222120
B4h ER (N) RSEL 26252423222120
B5h MODLOAD 211 210 29282726252423222120EE EE EE EE
B7h Control MODLOAD
Enable
HTXP
Enable
LTXP
Enable
HBIAS
Enable DPOL Soft
TX-D
Excite
Disable HALT
B8h High TX-P
Alarm Threshold EE EE EE EE EE 222120
B9h Low TX-P
Alarm Threshold EE EE EE EE EE 222120
BAh High BIAS Alarm
Threshold 2726252423222120
C3h PW High 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216
C5h PW Low 215 214 213 212 211 210 29282726252423222120
D1h IBIASSET Code 2726252423222120
D6h IMODSET Code 211 210 292827262524232221200 0 0 0
KEY: SRAM EEPROM
Note: 0 indicates an unused bit that reads as 0.
DS1861
Full Laser Control with Fault Management
____________________________________________________________________ 19
Detailed Register Description Conventions
Name of Row
•Name of Byte...<Write Access><Volatility><Power-
Up/Factory Default Value>
0. Name of bit 0.....Bit 0 Description
1. Name of bit 1.....Bit 1 Description
2 to 7. Bit names.....Bit 2 to 7 Descriptions
Write Access: W is write-only access, R is read-only
access, and R/W is read/write access. A password may
be required for write access on R/W registers. See the
memory map for complete access code descriptions.
Volatility: V is volatile (SRAM), NV is nonvolatile (EEPROM).
Power-Up/Factory Default Value: For SRAM registers,
this value is always the power-up value. For EEPROM
registers, this is the factory default value. These can be
permanently modified by entering the password and
writing the register. N/A is used for hardware-depen-
dent values, such as alarm flags.
Password Entry
•Status <R><V><N/A, depends on power-up condi-
tion>
0. HBIAS Alarm.....High Bias-Current Alarm. This
flag is high when IBIASSET ≥HBIAS Alarm
Threshold. This flag is updated every 4µs or
16µs depending on the state of the convergence
algorithm. Programming HBIAS threshold byte to
zero disables the HBIAS Alarm.
1. LTXP Alarm.....Low Transmitted Power Alarm.
This flag is high when the IBMD current drops
below the value set by the LTXP threshold. This
flag is updated every 16µs. Programming LTXP
threshold to zero disables this flag. This flag willl
be high when TX-D = 1 unless the alarm has
been disabled.
2. HTXP Alarm....High Transmitted Power Alarm.
This flag is high when the IBMD current rises
above the value set by the HTXP threshold. This
flag is updated every 16µs. Programming HTXP
Threshold to zero disables this flag.
3. POA....Analog Power-On Reset Alarm (VCC
Power Good). This flag is set when VCC < VPOA.
4. HBIAS Shutdown....This flag goes high when a
HBIAS safety fault is generated and HBIAS
Enable is high. HBIAS Shutdown goes low with
POA or a falling edge of the TX-D pin, providing
the safety fault is no longer present.
5. LTXP Shutdown....This flag goes high when a
LTXP safety fault is generated and LTXP Enable
is high. LTXP Shutdown goes low with POA or a
falling edge of TX-D, providing the safety fault is
no longer present.
6. HTXP Shutdown....This flag goes high when a
HTXP safety fault is generated and HTXP Enable
is high. HTXP Shutdown goes low with POA or a
falling edge of TX-D, providing the safety fault is
no longer present.
7. Shutdown Flag....This flag is high when any of
the three latched safety faults are high (HBIAS
Shutdown, LTXP Shutdown, or HTXP Shutdown),
and it remains high after the individual flag’s are
reset until fault reset time has elapsed.
•PWE High & Low....<R/W><V><FFFFh> Until the cor-
rect 32-bit password is written to PWE, the PWE bytes
are the only locations that can be written. PWE should
be written to a value other than the password once the
device’s configuration has been updated to prevent the
password from being read from PWE. After a power
cycle these locations will each be reset to FFFFh.
APC Config
•APC....<R/W><NV><00h> Sets the desired value of
the feedback current into the IBMD pin. The 3 MSB’s
determine the input GAIN value according to this table:
The remaining 5 LSBs determine the IBMD current set-
point (ISET) assuming a GAIN of 1. The formula for the
IBMD current setpoint with the gain is then given by:
ISET = 1.525µA GAIN (APC<4:0> + 32)
If values greater than 10011111b (9Fh) are pro-
grammed into the APC register, the DS1861 will clamp
ISET to its maximum value, equivalent to if the register
was set to 10011111b.
•ER (N)....<R/W><NV><1Ch> Sets the gain (N)on the
measured excitation current used to generate IMODSET.
This sets the extinction ratio of the system. Higher N
values increase the excitation ratio. The MSB of this
register (RSEL) is a flag that selects a high (RSEL = 1)
or low (RSEL = 0) range for N. The 7 LSBs of the regis-
ter determine the actual N code. The value of N can be
calculated by the following equation:
APC<7:5> GAIN
000 1
001 2
010 4
011 8
1xx 16
DS1861
Full Laser Control with Fault Management
20 ____________________________________________________________________
The default setting of ER = 1Ch corresponds to N = 30,
which is the minimum useable value. The maximum
useable value is N = 136 (ER = E8h). For more informa-
tion refer to the Automatic Extinction Ration Control
section.
•MODLOAD.....<R/W><NV><0000h> This register
determines the startup value of IMODSET following a
falling edge of TX-D when MODLOAD_Enable = 1 and
no fault condition has occurred. This 12-bit register
value is left justified in a 16-bit register. The 4 LSBs
default to 0s.
•Control.....<R/W><NV><70h> This byte is used to
enable/disnable the shutdown alarms and configure
several other settings. Writing to this byte causes an
EEPROM write cycle, even if only the HALT bit (SRAM)
is changed. It should not be modified more than the
specified number of write cycles.
0. HALT.....Setting this bit high stops the control
loop and freezes the outputs at their present
state. Once the control loop is stopped the IBIASSET
and IMODSET output registers can be read.
This bit is SRAM and resets to zero when VCC
drops below VPOAF.
1. Excite_Disable.....Setting this bit high prevents
the DS1861 from entering the excitation state (it
does not add the disturbance current), which
disables automatic extinction ratio control. IMODSET
will remain at its last value until reset by a
fault or set to MODLOAD.
2. Soft_TX-Disable.....This bit is ORed with the TX-D
pin to create the internal TX-Disable signal. So
asserting either Soft_TX-Disable or the TX-D pin
will disable the outputs. Both Soft_TX-Disable
and TX-D must be deasserted for the outputs to
operate.
3. DPOL.....Diode Polarity. Set to 0 to have the
BMD pin source current. Set to 1 to have BMD
sink current.
4. HBIAS_Enable.....Set high to allow a safety fault
caused by high bias alarm shut the part down.
5. LTXP_Enable.....Set high to allow a safety fault
caused by low transmitted power alarm shut the
part down.
6. HTXP_Enable.....Set high to allow a safety faultl
caused by high transmitted power alarm shut
the part down.
7. MODLOAD_Enable.....If high, IMODSET loads the
value in MODLOAD on the falling edge of TX-D
when no fault condition is present. Otherwise,
IMODSET will return to operation with its value
prior to when TX-D was asserted.
Quick-Trip Monitors
•HTXP Threshold.....<R/W><NV><00h> Sets the
threshold current for the HTXP alarm. The alarm trips
when IBMD > IBMD SETPOINT · [1 + (HTXP
Threshold<2:0>) 0.125]. Set to 00h to disable the alarm.
•LTXP Threshold.....<R/W><NV><00h> Sets the
threshold current for the LTXP alarm. The alarm trips
when IBMD < IBMD SETPOINT · [1 - (LTXP
Threshold<2:0>) 0.125]. Set to 00h to disable the alarm.
•HBIAS Threshold.....<R/W><NV><00h> Sets the
threshold current for the high bias current alarm. The
alarm trips when BIAS current is ≥7.625µA x (HBIAS
Threshold). This register value is compared directly
against the IBIASSET code value in register D1h to
determine if an alarm condition has occurred. Set
HBIAS threshold to 00h to disable this alarm.
Password
•PW High and Low.....<R/W><NV><0000h> The PWE
value is compared against the value written to these
locations to determine if the user has write access to
password-protected memory locations. These locations
read as zeros unless the password has been entered
into PWE to ensure the password remains secure.
DAC Codes
•IBIASSET Code.....<R/W><V><00h> This is the most
signicant byte of the 18-bit IBIASSET DAC code. IBIASSET
= 7.625µA x (IBIASSET code). The part must be halted
and the password must be entered to read this value.
•IMODSET Code.....<R/W><V><0000h> The IMODSET
DAC code. The LSB weight of the IMODSET DAC code
is 477nA. Thus, IMODSET = 477nA x (IMODSET code).
The part must be halted and the password entered to
read this value. The four least significant bytes of this
register read as 0s.
:
:
N
ER RSEL
ER RSEL
=
<>+ =
<>+ =
60 32
20
60 32 1
DS1861
Full Laser Control with Fault Management
____________________________________________________________________ 21
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, and start and stop conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high gener-
ates a stop condition. See the timing diagram for
applicable timing.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer to
indicate that it will immediately initiate a new data trans-
fer following the current one. Repeated starts are com-
monly used during read operations to identify a specific
memory address to begin a data transfer. A repeated
start condition is issued identically to a normal start con-
dition. See the timing diagram for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (Figure 14). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (Figure 14) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge (NACK)
is always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read or
the slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 14) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
SDA
SCL
tHD:STA
tLOW
tHIGH
tRtF
tBUF
tHD:DAT
tSU:DAT REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP
NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).
START
Figure 14. I2C Timing Diagram
DS1861
Full Laser Control with Fault Management
22 ____________________________________________________________________
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minated communication so the slave returns control of
SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave addressing byte sent immediately
following a start condition. The slave address byte
(Figure 15) contains the slave address in the most sig-
nificant 7 bits and the R/Wbit in the least significant bit.
The DS1861’s slave address is 1010A2A1A0 (binary),
where A2, A1, and A0are the values of the address
pins. The address pins allow the device to respond to
one of eight possible slave addresses. By writing the
correct slave address with R/W= 0, the master indi-
cates it will write data to the slave. If R/W= 1, the mas-
ter will read data from the slave. If an incorrect slave
address is written, the DS1861 assumes the master is
communicating with another I2C device and ignore the
communications until the next start condition is sent.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
I2C Communication
Writing a Single Byte to a Slave: The master must
generate a start condition, write the slave address byte
(R/W= 0), write the memory address, write the byte of
data and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave the master generates a start condition,
writes the slave address byte (R/W= 0), writes the
memory address, writes up to 8 data bytes and gener-
ates a stop condition.
The DS1861 can write 1 to 8 bytes (referred to as 1
row) with a single write transaction. This is internally
controlled by an address counter that allows data to be
written to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one row of the mem-
ory map. Attempts to write to additional memory rows
without sending a stop condition between rows will
result in the address counter wrapping around to the
beginning address of the present row.
Example: A 3-byte write starts at address BEh and writes
three data bytes (11h, 22h, and 33h) to three “consecu-
tive” addresses. The result would be addresses BEh and
BFh would contain 11h and 22h, respectively, and the
third data byte, 33h, would be written to address B8h.
To prevent address wrapping from occurring, the mas-
ter must send a stop condition at the end of the row,
and then wait for the bus free or EEPROM write time to
elapse. Then the master can generate a new start con-
dition, write the slave address byte (R/W= 0), and the
first memory address of the next memory row before
continuing to write data.
Acknowledge Polling: Any time EEPROM is written,
the DS1861 requires the EEPROM write time (tW) after
the stop condition to write the contents of the row to
EEPROM. During the EEPROM write time, the DS1861
does not acknowledge its slave address because it is
busy. It is possible to take advantage of this phenome-
non by repeatedly addressing the DS1861, which
allows the next row to be written as soon as the DS1861
is ready to receive the data. The alternative to acknowl-
edge polling is to wait for maximum period of tWto
elapse before attempting to write again to the DS1861.
EEPROM Write Cycles: When EEPROM writes occur,
the DS1861 will write the whole EEPROM memory row
even if only a single byte on the row was modified.
Writes that do not modify all 8 bytes on the row are
allowed and do not corrupt the remaining bytes of
memory on the same row. Because the whole row is
written, bytes on the row that were not modified during
the transaction are still subject to a write cycle. This
7-BIT SLAVE ADDRESS
MOST
SIGNIFICANT BIT
A2, A1 AND A0
PIN VALUES
DETERMINES
READ OR WRITE
R/W
1010A
2
A
1
A
0
Figure 15. Slave Address Byte
can result in a whole row being worn out over time by
writing a single byte repeatedly. Writing a row one byte
at a time will wear out the EEPROM eight times faster
than writing the entire row at once. The DS1861’s EEPROM
write cycles are specified in the Nonvolatile Memory
Characteristics table.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation
occurs at the present value of the memory address
counter. To read a single byte from the slave at the
location currently in the address counter; the master
generates a start condition, writes the slave address
byte with R/W= 1, reads the data byte with a NACK to
indicate the end of the transfer, and generates a stop
condition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a start condition, writes the slave address byte
(R/W= 0), writes the memory address where it desires
to read, generates a repeated start condition, writes the
slave address byte (R/W= 1), reads data with ACK or
NACK as applicable, and generates a stop condition.
Figure 16 shows a read example using the repeated
start condition to specify the starting memory location.
Reading Multiple Bytes from a Slave: The read oper-
ation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the mas-
ter reads the last byte, it NACKs to indicate the end of
the transfer and generates a stop condition. This can
be done with or without modifying the address
counter’s location before the read cycle.
DS1861
Full Laser Control with Fault Management
____________________________________________________________________ 23
XXXXXXXX
101 0 A
00A1
A2
101 0 A
00A1
A2
101 0 A
00A1
A2101 0 A
00A1
A2
101 0 A
00A1
A2
101 0 A
00A1
A2
COMMUNICATIONS KEY
WRITE A SINGLE BYTE
WRITE UP TO AN 8-BYTE PAGE WITH A SINGLE TRANSACTION
READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER
READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER
8-BITS ADDRESS OR DATA
WHITE BOXES INDICATED THE MASTER IS
CONTROLLING SDA
NOTES
2) THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
SHADED BOXES INDICATED THE SLAVE IS
CONTROLLING SDA
START ACK
NOT
ACK
S
S
S
S
S
A
A
A
A
A
A
AP
A
ASR
SR
A
A
AP
NP
NP
AA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
MEMORY ADDRESS
MEMORY ADDRESS
MEMORY ADDRESS
MEMORY ADDRESS
DATA
AA
A
PN
SR
STOP
REPEATED
START
1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
Figure 16. I2C Communications Examples
DS1861
Applications Information
Calibrating APC and Extinction Ratio
Before calibrating, the APC register should be set to a
low value to ensure the laser’s maximum power level is
not exceeded before the power level is calibrated.
Additionally, the ER register should be set to its mini-
mum value (28 decimal) to ensure that a data test pat-
tern does not cause the laser to shut off. Once the APC
and ER registers are at minimal values, enable a data
pattern and calibrate the average power level first.
Calibrating the Average Power Level
While sending data through the laser diode, increase
the value in the APC register until the light output
matches the desired average power level. The average
power level is the arithmetic average of the 1 and 0
power levels.
Calibrating the Extinction Ratio
While sending data through the laser diode, begin
increasing the ER register from its minimum value of 28
decimal (1Ch), until the proper extinction ratio is
reached or the maximum setting (104 decimal or 68h)
of the low range is reached. If the maximum low range
value is reached, write the ER register to 156 decimal
(9Ch), which switches the extinction ratio value to the
minimum value of the high range. Continue increasing
the ER setting until the proper extinction ratio is
reached. If the maximum value of the high range set-
ting is reached (232 decimal or E8h) without reaching
the proper extinction ratio, then either the desired
extinction ratio cannot be reached or a problem is pre-
venting the system from operating properly.
Addressing Multiple DS1861s
on a Common I2C Bus
Up to eight DS1861s can be addressed on a single I2C
bus by using the device’s address inputs (A2, A1, A0) to
change its slave address. For information about device
addressing, see the I2C Communications section.
Power-Supply Decoupling
To achieve best results, it is recommended that the power
supply is decoupled with a 0.01µF or a 0.1µF capacitor.
Use high-quality, ceramic, surface-mount capacitors, and
mount the capacitors as close as possible to the VCC and
GND pins to minimize lead inductance.
BMD Shunt Capacitor
The BMD shunt capacitor works with the internal resis-
tance of the BMD input to provide a lowpass filter that
reduces the effects of noise on the APC loop. Its
capacitance value must be chosen carefully to ensure
that it is both large enough to provide good filtering of
high-frequency noise and small enough that it does not
cause the control loop to become unstable. A 1nF, 10%
tolerant, X7R ceramic capacitor is recommended.
SDA and SCL Pullup Resistors
SDA is an open-collector bidirectional data pin on the
DS1861 that requires a pullup resistor to realize high
logic levels. Either an open-collector output with a
pullup resistor or a push-pull output driver can be used
for the SCL input. Pullup resistor values should be cho-
sen to ensure that the rise and fall times listed in the AC
Electrical Characteristics table are within specification.
Full Laser Control with Fault Management
24 ____________________________________________________________________
DS1861
Full Laser Control with Fault Management
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Chip Information
TRANSISTOR COUNT: 55,677
SUBSTRATE CONNECTED TO GROUND
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
MODSET
A2
A1
TX-D
TX-F
SCL
SDA
TOP VIEW
A0
BIASSET
N.C.GND
BMD
N.C.
DS1861
Pin Configuration