Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 LMZ23608 8-A SIMPLE SWITCHER(R) Power Module With 36-V Maximum Input Voltage and Current Sharing 1 Features 2 Applications * * * * 1 * * * * * * * * * Integrated Shielded Inductor Simple PCB Layout Frequency Synchronization Input (350 kHz to 600 kHz) Current Sharing Capability Flexible Start-up Sequencing Using External SoftStart, Tracking and Precision Enable Protection Against Inrush Currents and Faults Such as Input UVLO and Output Short Circuit Junction Temperature Range -40C to 125C Single Exposed Pad and Standard Pinout for Easy Mounting and Manufacturing Fully Enabled for WEBENCH(R) Power Designer Pin Compatible With LMZ22010/08, LMZ12010/08, LMZ23610/06H, and LMZ13610/08/06H Electrical Specifications - 40-W Maximum Total Output Power - Up to 8-A Output Current - Input Voltage Range 6 V to 36 V - Output Voltage Range 0.8 V to 6 V - Efficiency up to 92% Performance Benefits - High Efficiency Reduces System Heat Generation - Low Radiated Emissions (EMI) Tested to EN55022 Class B Standard - Only 7 External Components - Low Output Voltage Ripple - No External Heat Sink Required - Simple Current Sharing for Higher Current Applications * * * Point-of-load Conversions from 12-V and 24-V Input Rail Time-Critical Projects Space Constrained and High Thermal Requirement Applications Negative Output Voltage Applications (See AN-2027 SNVA425) 3 Description The LMZ23608 SIMPLE SWITCHER(R) power module is an easy-to-use step-down DC-DC solution capable of driving up to 8-A load. The LMZ23608 is available in an innovative package that enhances thermal performance and allows for hand or machine soldering. The LMZ23608 can accept an input voltage rail between 6 V and 36 V and can deliver an adjustable and highly accurate output voltage as low as 0.8 V. The LMZ23608 only requires two external resistors and three external capacitors to complete the power solution. The LMZ23608 is a reliable and robust design with the following protection features: thermal shutdown, input undervoltage lockout, output overvoltage protection, short circuit protection, output current limit, and allows start-up into a prebiased output. The sync input allows synchronization over the 350 to 600-kHz switching frequency range. Device Information(1)(2) PART NUMBER LMZ23608 PACKAGE NDY (11) BODY SIZE (NOM) 15.00 mm x 15.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Peak reflow temperature equals 245C. See SNAA214 for more details. NOTE: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B, tested on Evaluation Board with EMI configuration Simplified Application Schematic Efficiency 3.3-V Output at 25C 100 LMZ23608 EFFICIENCY (%) SH VOUT SS FB AGND PGND EN SYNC VIN 90 VIN VOUT Share Clock CFF 4.7 nF (OPT) Enable RFBT 3 x 10 PF CSS 0.47 PF (OPT) RFBB See Table 70 60 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 50 40 See Table CIN 80 COUT 2 x 330 PF 30 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 8 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics ............................................. Detailed Description ............................................ 14 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 14 14 14 17 8 Application and Implementation ........................ 18 8.1 Application Information............................................ 18 8.2 Typical Application ................................................. 18 9 Power Supply Recommendations...................... 24 10 Layout................................................................... 24 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Examples................................................... Power Dissipation and Thermal Considerations ... Power Module SMT Guidelines ............................ 24 25 26 27 11 Device and Documentation Support ................. 29 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 29 29 29 29 29 29 12 Mechanical, Packaging, and Orderable Information ........................................................... 30 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (October 2013) to Revision G Page * Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 * Deleted Easy-to-Use PFM 7-Pin Package image .................................................................................................................. 1 Changes from Revision E (March 2013) to Revision F Page * Deleted 12 mils....................................................................................................................................................................... 4 * Changed 12 mils................................................................................................................................................................... 24 * Changed 12 mils................................................................................................................................................................... 26 * Added Power Module SMT Guidelines................................................................................................................................. 27 2 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 5 Pin Configuration and Functions NDY Package 11-Pin Top View 11 10 9 8 7 6 5 4 3 2 1 PGND/EP Connect to AGND VOUT VOUT SH SS FB AGND AGND EN SYNC VIN VIN Pin Functions PIN I/O NAME NO. AGND 5 DESCRIPTION Ground Analog Ground -- Reference point for all stated voltages. Must be externally connected to EP/PGND. 6 EN 4 Analog Enable -- Input to the precision enable comparator. Rising threshold is 1.274 V typical. Once the module is enabled, a 20-A source current is internally activated to accommodate programmable hysteresis. FB 7 Analog Feedback -- Internally connected to the regulation, overvoltage, and short circuit comparators. The regulation reference point is 0.8 V at this input pin. Connect the feedback resistor divider between the output and AGND to set the output voltage. PGND -- Ground Exposed Pad / Power Ground Electrical path for the power circuits within the module. -- NOT Internally connected to AGND / pin 5. Used to dissipate heat from the package during operation. Must be electrically connected to pin 5 external to the package. SH 9 Analog Share pin. Connect this to the share pin of other LMZ23608 modules to share the load between the devices. One device must be configured as the master by connecting the FB normally. All other devices must be configured as slaves by leaving their respective FB pins floating. Leave this pin floating if not used, do not ground. See Design Steps section. SS 8 Analog Soft-Start/Track input -- To extend the 1.6-ms internal soft-start connect an external soft-start capacitor. For tracking connect to an external resistive divider connected to a higher priority supply rail. See Design Steps section. SYNC 3 Analog Sync Input -- Apply a CMOS logic level square wave whose frequency is between 350 kHz and 600 kHz to synchronize the PWM operating frequency to an external frequency source. When not using synchronization this pin must be tied to ground. The module free running PWM frequency is 350 kHz. VOUT 10 Power Output Voltage -- Output from the internal inductor. Connect the output capacitor between this pin and PGND. Power Supply input -- Nominal operating range is 6 V to 36 V. A small amount of internal capacitance is contained within the package assembly. Additional external input capacitance is required between this pin and PGND. 11 VIN 1 2 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 3 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT VIN to PGND -0.3 40 V EN, SYNC to AGND -0.3 5.5 V SS, FB, SH to AGND -0.3 2.5 V AGND to PGND -0.3 0.3 V 150 C 150 C Junction temperature Storage temperature, Tstg (1) (2) (3) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. For soldering specifications: see product folder at www.ti.com and SNOA549 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT 2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN MAX VIN 6 36 V EN, SYNC 0 5 V -40 125 C Operation junction temperature UNIT 6.4 Thermal Information LMZ23608 THERMAL METRIC (1) NDY UNIT 11 PINS Junction-to-ambient thermal resistance (2) RJA RJC(top) (1) (2) 4 Natural Convection 9.9 225 LFPM 6.8 500 LFPM 5.2 Junction-to-case (top) thermal resistance 1.0 C/W C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Theta JA measured on a 3.0-in x 3.5-in 4-layer board, with 2-oz. copper on outer layers and 1-oz. copper on inner layers, two hundred and ten thermal vias, and 2-W power dissipation. Refer to evaluation board application note layout diagrams. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 6.5 Electrical Characteristics Limits are for TJ = 25C unless otherwise specified. Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12V, VOUT = 3.3V PARAMETER MIN (1) TEST CONDITIONS TYP (2) MAX (1) UNIT SYSTEM PARAMETERS ENABLE CONTROL 1.274 VEN EN threshold VEN rising IEN-HYS EN hysteresis source current VEN > 1.274 V ISS SS source current VSS = 0 V tSS Internal soft-start interval over the junction temperature (TJ) range of -40C to +125C 1.096 1.452 13 V A SOFT-START 50 over the junction temperature (TJ) range of -40C to +125C 40 60 1.6 A ms CURRENT LIMIT ICL Current limit threshold DC average 10.5 A INTERNAL SWITCHING OSCILLATOR fosc Free-running oscillator frequency Sync input connected to ground 314 fsync Synchronization range Vsync = 3.3 Vp-p 314 VIL-sync Synchronization logic zero amplitude Relative to AGND over the junction temperature (TJ) range of -40C to +125C VIH-sync Synchronization logic one amplitude Relative to AGND over the junction temperature (TJ) range of -40C to +125C SyncDC Synchronization duty cycle range 359 404 kHz 600 kHz 0.4 V 1.8 15% V 50% 85% REGULATION AND OVERVOLTAGE COMPARATOR VSS >+ 0.8 V IO = 8 A VFB In-regulation feedback voltage VFB-OV Feedback over-voltage protection threshold IFB Feedback input bias current IQ Non-switching quiescent current SYNC = 3 V ISD Shutdown quiescent current VEN = 0 V Dmax Maximum duty factor 0.795 over the junction temperature (TJ) range of -40C to +125C 0.775 0.815 V 0.86 V 5 nA 3 mA 32 A 85% THERMAL CHARACTERISTICS TSD Thermal shutdown Rising 165 C TSD-HYST Thermal shutdown hysteresis Falling 15 C 24 mVPP PERFORMANCE PARAMETERS (3) VO Output voltage ripple BW at 20 MHz VO/VIN Line regulation VIN = 12V to 20 V, IOUT= 8 A VO/IOUT Load regulation VIN = 12 V, IOUT= 0.001 A to 8 A Peak efficiency VIN = 12 V, VOUT = 3.3 V, IOUT = 5 A 89.5% Full load efficiency VIN = 12 V, VOUT = 3.3 V, IOUT = 8 A 88.5% (1) (2) (3) 0.2% 1 mV/A Minimum and Maximum limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Typical numbers are at 25C and represent the most likely parametric norm. Refer to BOM in Table 1. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 5 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com 6.6 Typical Characteristics Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 3 x 10 F + 47-nF X7R Ceramic; COUT = 2 x 330F Specialty Polymer + 47-F Ceramic + 47-nF Ceramic; CFF = 4.7 nF; TA = 25C for waveforms. All indicated temperatures are ambient. 100 10 8 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 9 90 DISSIPATION (W) EFFICIENCY (%) 8 80 70 60 8 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 50 40 30 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 7 6 5 4 3 2 1 0 8 0 Figure 1. Efficiency 50-V Output at 25C 10 DISSIPATION (W) EFFICIENCY (%) 8 60 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 50 40 30 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 7 6 5 4 3 1 0 8 0 10 DISSIPATION (W) EFFICIENCY (%) 8 70 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 40 30 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 7 8 7 6 5 4 3 2 1 0 8 Figure 5. Efficiency 2.5-V Output at 25C 6 2 3 4 5 6 OUTPUT CURRENT (A) 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 9 90 80 1 Figure 4. Dissipation 3.3-V Output at 25C 100 50 8 2 Figure 3. Efficiency 3.3-V Output at 25C 60 7 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 9 90 70 2 3 4 5 6 OUTPUT CURRENT (A) Figure 2. Dissipation 5-V Output at 25C 100 80 1 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 8 Figure 6. Dissipation 2.5-V Output at 25C Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 3 x 10 F + 47-nF X7R Ceramic; COUT = 2 x 330F Specialty Polymer + 47-F Ceramic + 47-nF Ceramic; CFF = 4.7 nF; TA = 25C for waveforms. All indicated temperatures are ambient. 90 10 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 9 80 DISSIPATION (W) EFFICIENCY (%) 8 70 60 50 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 40 30 20 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 5 4 3 1 0 7 8 0 90 10 80 9 60 50 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 40 30 20 10 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 6 4 3 1 0 7 8 0 9 70 8 DISSIPATION (W) 10 60 50 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 10 0 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 8 Figure 10. Dissipation 1.5-V Output at 25C 80 20 8 5 90 30 7 2 Figure 9. Efficiency 1.5-V Output at 25C 40 2 3 4 5 6 OUTPUT CURRENT (A) 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 8 70 1 Figure 8. Dissipation 1.8-V Output at 25C DISSIPATION (W) EFFICIENCY (%) 6 2 Figure 7. Efficiency 1.8-V Output at 25C EFFICIENCY (%) 7 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 7 6 5 4 3 2 1 0 7 8 Figure 11. Efficiency 1.2-V Output at 25C 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 8 Figure 12. Dissipation 1.2-V Output at 25C Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 7 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) 90 10 80 9 70 8 DISSIPATION (W) EFFICIENCY (%) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 3 x 10 F + 47-nF X7R Ceramic; COUT = 2 x 330F Specialty Polymer + 47-F Ceramic + 47-nF Ceramic; CFF = 4.7 nF; TA = 25C for waveforms. All indicated temperatures are ambient. 60 50 40 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 30 20 10 0 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 7 6 5 4 3 2 1 0 7 8 Figure 13. Efficiency 1-V Output at 25C 0 10 8 DISSIPATION (W) EFFICIENCY (%) 90 8 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 60 50 40 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 5 4 3 1 0 8 0 90 9 70 60 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 20 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 2 3 4 5 6 OUTPUT CURRENT (A) 7 8 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 8 80 1 Figure 16. Dissipation 5-V Output at 85C DISSIPATION (W) EFFICIENCY (%) 6 10 30 7 6 5 4 3 2 1 0 8 Figure 17. Efficiency 3.3-V Output at 85C 8 7 100 40 8 2 Figure 15. Efficiency 5-V Output at 85C 50 7 8 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 9 70 2 3 4 5 6 OUTPUT CURRENT (A) Figure 14. Dissipation 1-V Output at 25C 100 80 1 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 8 Figure 18. Dissipation 3.3-V Output at 85C Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 Typical Characteristics (continued) 100 10 90 9 80 8 DISSIPATION (W) EFFICIENCY (%) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 3 x 10 F + 47-nF X7R Ceramic; COUT = 2 x 330F Specialty Polymer + 47-F Ceramic + 47-nF Ceramic; CFF = 4.7 nF; TA = 25C for waveforms. All indicated temperatures are ambient. 70 60 50 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 40 30 20 10 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 6 5 4 3 1 0 7 8 0 90 10 80 9 60 50 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 40 30 20 10 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 6 4 3 1 0 7 8 0 80 9 DISSIPATION (W) 60 50 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 10 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 2 3 4 5 6 OUTPUT CURRENT (A) 7 8 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 8 70 1 Figure 22. Dissipation 1.8-V Output at 85C 10 20 8 5 90 30 7 2 Figure 21. Efficiency 1.8-V Output at 85C 40 2 3 4 5 6 OUTPUT CURRENT (A) 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 8 70 1 Figure 20. Dissipation 2.5-V Output at 85C DISSIPATION (W) EFFICIENCY (%) 7 2 Figure 19. Efficiency 2.5-V Output at 85C EFFICIENCY (%) 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 7 6 5 4 3 2 1 0 7 8 Figure 23. Efficiency 1.5-V Output at 85C 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 8 Figure 24. Dissipation 1.5-V Output at 85C Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 9 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) 90 10 80 9 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 8 70 DISSIPATION (W) EFFICIENCY (%) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 3 x 10 F + 47-nF X7R Ceramic; COUT = 2 x 330F Specialty Polymer + 47-F Ceramic + 47-nF Ceramic; CFF = 4.7 nF; TA = 25C for waveforms. All indicated temperatures are ambient. 60 50 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 40 30 20 10 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 6 5 4 3 2 1 0 7 8 Figure 25. Efficiency 1.2-V Output at 85C 0 12 10 DISSIPATION (W) EFFICIENCY (%) 70 40 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36Vin 30 20 10 0 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 8 6 4 0 7 8 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 7 8 Figure 28. Dissipation 1-V Output at 85C 1.002 10 MAXIMUM OUTPUT CURRENT (A) NORMALIZED VOUT (V/V) 8 2 Figure 27. Efficiency 1-V Output at 85C 1.001 1.000 6 Vin 8 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 36 Vin 0.999 0.998 0 1 2 3 4 5 6 7 OUTPUT CURRENT (A) 8 6 4 2 JA = 9.9 C/W JA = 6.8 C/W JA = 5.2 C/W 0 8 20 30 40 50 60 70 80 90 100 110 120 TEMPERATURE (C) VOUT = 3.3 V VIN = 24 V, VOUT = 5 V Figure 29. Normalized Line and Load Regulation 10 7 6 Vin 10 Vin 12 Vin 16 Vin 20 Vin 24 Vin 30 Vin 36 Vin 80 50 2 3 4 5 6 OUTPUT CURRENT (A) Figure 26. Dissipation 1.2-V Output at 85C 90 60 1 Submit Documentation Feedback Figure 30. Thermal Derating Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 3 x 10 F + 47-nF X7R Ceramic; COUT = 2 x 330F Specialty Polymer + 47-F Ceramic + 47-nF Ceramic; CFF = 4.7 nF; TA = 25C for waveforms. All indicated temperatures are ambient. 30 2 Layer 0 LFPM 2 Layer 225 LFPM 4 Layer 0 LFPM 4 Layer 225 LFPM 27 8 24 THETA JA (C/W) MAXIMUM OUTPUT CURRENT (A) 10 6 4 21 18 15 12 9 2 JA = 9.9 C/W JA = 6.8 C/W JA = 5.2 C/W 0 6 3 20 30 40 50 60 70 80 90 100 110 120 TEMPERATURE (C) 0 2 4 6 8 2 COPPER AREA (in ) 10 12 VIN = 24 V, VOUT = 3.3 V Figure 31. Thermal Derating 12 VIN, 5 VOUT at Full Load, BW = 20 MHz Figure 32. JA vs Copper Heat Sinking Area 12 VIN, 5 VOUT at Full Load, BW = 250 MHz Figure 33. Output Ripple 12 VIN, 3.3 VOUT at Full Load, BW = 20 MHz Figure 34. Output Ripple 12 VIN, 3.3 VOUT at Full Load, BW = 250 MHz Figure 36. Output Ripple Figure 35. Output Ripple Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 11 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 3 x 10 F + 47-nF X7R Ceramic; COUT = 2 x 330F Specialty Polymer + 47-F Ceramic + 47-nF Ceramic; CFF = 4.7 nF; TA = 25C for waveforms. All indicated temperatures are ambient. 12 VIN, 1.2 VOUT at Full Load, BW = 250 MHz 12 VIN, 1.2 VOUT at Full Load, BW = 20 MHz Figure 38. Output Ripple Figure 37. Output Ripple 12 VIN, 5 VOUT 1- to 8-A Step 12 VIN, 3.3 VOUT 1- to 8-A Step Figure 39. Transient Response Figure 40. Transient Response 16 14 CURRENT (A) 12 10 8 6 4 Output Current Input Current 2 0 5 10 15 INPUT VOLTAGE (V) 20 12 VIN, 1.2 VOUT 1- to 8-A Step Figure 41. Transient Response 12 Figure 42. Short Circuit Current vs Input Voltage Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 3 x 10 F + 47-nF X7R Ceramic; COUT = 2 x 330F Specialty Polymer + 47-F Ceramic + 47-nF Ceramic; CFF = 4.7 nF; TA = 25C for waveforms. All indicated temperatures are ambient. No CSS CSS = 0.47 F Figure 43. 3.3 VOUT Soft-Start Figure 44. 3.3 VOUT Soft-Start Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 13 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com 7 Detailed Description 7.1 Overview The architecture used is an internally compensated emulated peak current mode control, based on a monolithic synchronous SIMPLE SWITCHER core capable of supporting high load currents. The output voltage is maintained through feedback compared with an internal 0.8-V reference. For emulated peak current-mode, the valley current is sampled on the down-slope of the inductor current. This is used as the DC value of current to start the next cycle. The primary application for emulated peak current-mode is high input voltage to low output voltage operating at a narrow duty cycle. By sampling the inductor current at the end of the switching cycle and adding an external ramp, the minimum ON-time can be significantly reduced, without the need for blanking or filtering which is normally required for peak current-mode control. 7.2 Functional Block Diagram Linear Regulator 2M VIN 1 3 3 CIN EN 2 350 kHz PWM SS 2.2 uH VOUT VREF 3 RFBT CINint 1 SYNC CSS CBST COUT FB RFBB 2 Comp SH Filter AGND Regulator IC EP/ PGND Internal Passives 7.3 Feature Description 7.3.1 Synchronization Input The PWM switching frequency can be synchronized to an external frequency source. The PWM switching will be in phase with the external frequency source. If this feature is not used, connect this input either directly to ground, or connect to ground through a resistor of 1.5 k or less. The allowed synchronization frequency range is 314 kHz to 600 kHz. The typical input threshold is 1.4 V. Ideally, the input clock must overdrive the threshold by a factor of 2, so direct drive from 3.3-V logic through a 1.5-k or less Thevenin source resistance is recommended. Applying a sustained logic 1 corresponds to 0-Hz PWM frequency and will cause the module to stop switching. 7.3.2 Current Sharing When a load current higher than 8 A is required by the application, the LMZ23608 can be configured to share the load between multiple devices. To share the load current between the devices, connect the SH pin of all current sharing LMZ23608 modules. One device must be configured as the master by connecting FB normally. All other devices must be configured as slaves by leaving their respective FB pins floating. The modules must be synchronized by a clock signal to avoid beat frequencies in the output voltage caused by small differences in the internal 359-kHz clock. If the modules are not synchronized, the magnitude of the ripple voltage will depend on the phase relationship of the internal clocks. The external synchronizing clocks can be in phase for all modules, 14 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 Feature Description (continued) or out of phase to reduce the current stress on the input and output capacitors. As an example, two modules can be run 180 degrees out of phase, and three modules can be run 120 degrees out of phase. The VIN, VOUT, PGND, and AGND pins must also be connected with low impedance paths. It is particularly important to pay close attention to the layout of AGND and SH, as offsets in grounding or noise picked up from other devices will be seen as a mismatch in current sharing and could cause noise issues. Current sharing modules can be configured to share the same set of bulk input and output capacitors, while each having their own local input and output bypass capacitors. A CIN_BYP >= 30 F is still recommended for each module that is connected in a current sharing configuration. A COUT_BYP consisting of 47-nF X7R ceramic capacitor in parallel with a 22-F ceramic capacitor is recommended to locally bypass the output voltage for each module. These capacitors will provide local bypassing of high-frequency switched currents. In a current sharing system using two or more modules, the slaves have their error amp circuitry disconnected. The master overrides the error amplifier outputs of the slaves. This signal is then compared to each module's individual current sense circuitry. Due to this, the current sense gain of the entire system increases according to the number of modules slaved to the master. To compensate for this and ensure good stability, the total output capacitance has to be increased. For example, two modules configured to provide 1.2 VOUT and 16 amps have a required total bulk output capacitance of COUT_BULK = 2 x 450 F (ESR 25 m). This is a thirty six percent increase in the required output capacitance of a stand alone module. Up to 6 modules can be connected in parallel for loads up to 48 A. For more information on current sharing refer to AN-2093 (SNVA460). SH VOUT SS X X Clk CIN_BYP FB PGND EN AGND VIN SYNC SLAVE Share COUT_BYP Enable VIN VOUT Clk CIN_BYP LOAD COUT_BULK VOUT SH SS FB PGND AGND SYNC VIN EN MASTER CIN_BULK Share CSS Enable COUT_BYP RFBB RFBT Figure 45. Current Sharing Example Schematic Figure 46. Output Voltage Ripple of Two Modules With Synchronization Clocks in Phase Figure 47. Output Voltage Ripple of Two Modules With Synchronization Clocks 180 Degrees Out of Phase Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 15 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com Feature Description (continued) 7.3.3 Output Overvoltage Protection If the voltage at FB is greater than a 0.86-V internal reference, the output of the error amplifier is pulled toward ground, causing VOUT to fall. 7.3.4 Current Limit The LMZ23608 is protected by both low-side (LS) and high-side (HS) current limit circuitry. The LS current limit detection is carried out during the OFF-time by monitoring the current through the LS synchronous MOSFET. Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 13 A (typical), the current limit comparator disables the start of the next switching period. Switching cycles are prohibited until current drops below the limit. NOTE DC current limit is dependent on duty cycle as illustrated in the graph in the Typical Characteristics section. The HS current limit monitors the current of top side MOSFET. Once HS current limit is detected (16 A typical) , the HS MOSFET is shutoff immediately, until the next cycle. Exceeding HS current limit causes VOUT to fall. Typical behavior of exceeding LS current limit is that fSW drops to 1/2 of the operating frequency. 7.3.5 Thermal Protection The junction temperature of the LMZ23608 must not be allowed to exceed its maximum ratings. Thermal protection is implemented by an internal Thermal Shutdown circuit which activates at 165C (typical) causing the device to enter a low power standby state. In this state the main MOSFET remains off causing VOUT to fall, and additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for accidental device overheating. When the junction temperature falls back below 150C (typical hysteresis = 15C) the SS pin is released, VOUT rises smoothly, and normal operation resumes. Applications requiring maximum output current especially those at high input voltage may require additional derating at elevated temperatures. 7.3.6 Prebiased Start-Up The LMZ23608 will properly start up into a prebiased output. This start-up situation is common in multiple rail logic applications where current paths may exist between different power rails during the start-up sequence. The following scope capture shows proper behavior in this mode. Trace one is Enable going high. Trace two is 1.8-V prebias rising to 3.3 V. Trace three is the SS voltage with a CSS= 0.47 F. Rise-time determined by CSS. Figure 48. Prebiased Start-Up 16 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 7.4 Device Functional Modes 7.4.1 Discontinuous Conduction and Continuous Conduction Modes At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the critical conduction point, it will operate in continuous conduction mode (CCM). When operating in DCM, inductor current is maintained to an average value equaling IOUT. In DCM the low-side switch will turn off when the inductor current falls to zero, this causes the inductor current to resonate. Although it is in DCM, the current is allowed to go slightly negative to charge the bootstrap capacitor. In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the OFF-time. Following is a comparison pair of waveforms showing both the CCM (upper) and DCM operating modes. VIN = 12 V, VO = 3.3 V, IO = 3 A / 0.3 A Figure 49. CCM and DCM Operating Modes Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 17 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMZ23608 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 8 A. The following design procedure can be used to select components for the LMZ23608. Alternately, the WEBENCH software may be used to generate complete designs. When generating a design, the WEBENCH software uses iterative design procedure and accesses comprehensive databases of components. Please go to www.ti.com for more details. 8.2 Typical Application + CIN5 (OPT) CIN2,3,4 SH Clk CIN1 VOUT Share CSS RSYNC CO3,4 CO1 (OPT) CO2 (OPT) CO5 (OPT) LOAD RFBB RENT D1 5.1V (OPT) VOUT SS PGND FB AGND EN VIN VIN CIN6 (OPT) SYNC LMZ23608 RENB RFBT Figure 50. Typical Application Schematic Diagram 8.2.1 Design Requirements For this example the following application parameters exist. * VIN Range = Up to 36 V * VOUT = 0.8 V to 6 V * IOUT = 8 A 8.2.2 Detailed Design Procedure 8.2.2.1 Design Steps The LMZ23608 is fully supported by WEBENCH which offers: component selection, electrical and thermal simulations. Additionally, there are both evaluation and demonstration boards that may be used as a starting point for design. The following list of steps can be used to manually design the LMZ23608 application. All references to values refer to the typical applications schematic Table 1. 1. 2. 3. 4. 5. 6. 18 Select minimum operating VIN with enable divider resistors Program VOUT with FB resistor divider selection Select COUT Select CIN Determine module power dissipation Layout PCB for required thermal performance Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 Typical Application (continued) 8.2.2.2 Enable Divider, RENT, RENB and RENH Selection Internal to the module is a 2-M pullup resistor connected from VIN to Enable. For applications not requiring precision undervoltage lockout (UVLO), the Enable input may be left open circuit and the internal resistor will always enable the module. In such case, the internal UVLO occurs typically at 4.3 V (VIN rising). In applications with separate supervisory circuits Enable can be directly interfaced to a logic source. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ23608 output rail. Enable provides a precise 1.274-V threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as VIN. Additionally there is 13 A (typical) of switched offset current allowing programmable hysteresis. See Figure 51. The function of the enable divider is to allow the designer to choose an input voltage below which the circuit will be disabled. This implements the feature of a programmable UVLO. The two resistors must be chosen based on the following ratio: RENT / RENB = (VIN UVLO / 1.274 V) - 1 (1) The LMZ23608 typical application shows 12.7 k for RENB and 42.2 k for RENT resulting in a rising UVLO of 5.51 V. NOTE This divider presents 4.62 V to the EN input when VIN is raised to 20 V. This upper voltage must always be checked, making sure that it never exceeds the Abs Max 5.5-V limit for Enable. A 5.1-V Zener clamp can be applied in cases where the upper voltage would exceed the EN input's range of operation. The Zener clamp is not required if the target application prohibits the maximum Enable input voltage from being exceeded. Additional enable voltage hysteresis can be added with the inclusion of RENH. It is possible to select values for RENT and RENB such that RENH is a value of zero allowing it to be omitted from the design. Rising threshold can be calculated as follows: VEN(rising) = 1.274 ( 1 + (RENT|| 2 meg)/ RENB) (2) Whereas the falling threshold level can be calculated using: VEN(falling) = VEN(rising) - 13 A ( RENT|| 2 meg || RENTB + RENH ) VIN (3) INT-VCC (5V) 13 PA 2.0M RENT 42.2k RENH ENABLE RUN 100: 5.1V RENB 12.7k 1.274V Figure 51. Enable Input Detail 8.2.2.3 Output Voltage Selection Output voltage is determined by a divider of two resistors connected between VOUT and AGND. The midpoint of the divider is connected to the FB input. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 19 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com Typical Application (continued) The regulated output voltage determined by the external divider resistors RFBT and RFBB is: VOUT = 0.795 V x (1 + RFBT / RFBB) (4) Rearranging terms; the ratio of the feedback resistors for a desired output voltage is: RFBT / RFBB = (VOUT / 0.795 V) - 1 (5) These resistors must generally be chosen from values in the range of 1.0 k to 10.0 k. For VOUT = 0.8 V the FB pin can be connected to the output directly and RFBB can be set to 8.06 k to provide minimum output load. Table 1 lists the values for RFBT , and RFBB. Table 1. Typical Application Bill of Materials REF DES DESCRIPTION CASE SIZE MANUFACTURER U1 SIMPLE SWITCHER PFM-11 Texas Instruments MANUFACTURER P/N LMZ23608TZ CIN1,6 (OPT) 0.047 F, 50 V, X7R 1206 Yageo America CC1206KRX7R9BB473 CIN2,3,4 10 F, 50 V, X7R 1210 Taiyo Yuden UMK325BJ106MM-T CIN5 (OPT) CAP, AL, 150 F, 50 V Radial G Panasonic EEE-FK1H151P CO1,5 (OPT) 0.047 F, 50 V, X7R 1206 Yageo America CC1206KRX7R9BB473 CO2 (OPT) 47 F, 10 V, X7R 1210 Murata GRM32ER61A476KE20L CO3,4 330 F, 6.3 V, 0.015 CAPSMT_6_UE Kemet T520D337M006ATE015 RFBT 3.32 k 0805 Panasonic ERJ-6ENF3321V RFBB 1.07 k 0805 Panasonic ERJ-6ENF1071V RSYNC 1.50 k 0805 Vishay Dale CRCW08051K50FKEA RENT 42.2 k 0805 Panasonic ERJ-6ENF4222V RENB 12.7 k 0805 Panasonic ERJ-6ENF1272V CSS 0.47 F, 10%, X7R, 16 V 0805 AVX 0805YC474KAT2A D1 (OPT) 5.1 V, 0.5 W SOD-123 Diodes Inc. MMSZ5231BS-7-F 8.2.2.4 Soft-Start Capacitor Selection Programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time. Upon turnon, after all UVLO conditions have been passed, an internal 1.6-ms circuit slowly ramps the SS input to implement internal soft start. If 1.6 ms is an adequate turnon time then the Css capacitor can be left unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input. Soft-start duration is given by the formula: tSS = VREF x CSS / Iss = 0.795 V x CSS / 50 A (6) This equation can be rearranged as follows: CSS = tSS x 50 A / 0.795 V (7) Using a 0.22-F capacitor results in 3.5-ms typical soft-start duration; and 0.47 F results in 7.5 ms typical. 0.47 F is a recommended initial value. As the soft-start input exceeds 0.795 V the output of the power stage will be in regulation and the 50-A current is deactivated. The following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal current sink. * * * 20 The Enable input being pulled low A thermal shutdown condition VIN falling below 4.3 V (typical) and triggering the VCC UVLO Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 8.2.2.5 Tracking Supply Divider Option The tracking function allows the module to be connected as a slave supply to a primary voltage rail (often the 3.3-V system rail) where the slave module output voltage is lower than that of the master. Proper configuration allows the slave rail to power up coincident with the master rail such that the voltage difference between the rails during ramp-up is small (that is, < 0.15 V typical). The values for the tracking resistive divider must be selected such that the effect of the internal 50-A current source is minimized. In most cases the ratio of the tracking divider resistors is the same as the ratio of the output voltage setting divider. Proper operation in tracking mode dictates the soft-start time of the slave rail be shorter than the master rail; a condition that is easy to satisfy because the CSS cap is replaced by RTKB. The tracking function is only supported for the power up interval of the master supply; once the SS/TRK rises past 0.795 V the input is no longer enabled and the 50-A internal current source is switched off. 3.3V Master 2.5Vout Int VCC 50 PA Rtkt 226 Rfbt 2.26k SS FB Rtkb 107 Rfbb 1.07k Figure 52. Tracking Option Input Detail 8.2.2.6 COUT Selection None of the required COUT output capacitance is contained within the module. A minimum value ranging from 330 F for 6-VOUT to 660 F for 1.2-VOUT applications is required based on the values of internal compensation in the error amplifier. These minimum values can be decreased if the effective capacitor ESR is higher than 15 m. A Low ESR (15-m) tantalum, organic semiconductor or specialty polymer capacitor types in parallel with a 47nF X7R ceramic capacitor for high frequency noise reduction is recommended for obtaining lowest ripple. The output capacitor COUT may consist of several capacitors in parallel placed in close proximity to the module. The output voltage ripple of the module depends on the equivalent series resistance (ESR) of the capacitor bank, and can be calculated by multiplying the ripple current of the module by the effective impedance of your chosen output capacitors (for ripple current calculation, see Equation 14). Electrolytic capacitors will have large ESR and lead to larger output ripple than ceramic or polymer types. For this reason a combination of ceramic and polymer capacitors is recommended for low output ripple performance. The output capacitor assembly must also meet the worst case ripple current rating of iL, as calculated in Equation 14 below. Loop response verification is also valuable to confirm closed loop behavior. For applications with dynamic load steps; the following equation provides a good first pass approximation of COUT for load transient requirements. Istep COUTt ('VOUT - ISTEP x ESR) x ( fSW ) VOUT (8) For 12 VIN, 3.3 VOUT, a transient voltage of 5% of VOUT = 0.165 V (VOUT), a 7-A load step (ISTEP), an output capacitor effective ESR of 3 m, and a switching frequency of 350 kHz (fSW): 7A COUTt (0.165V - 7A x 0.003) x ( 350e3 ) 3.3V t458 PF (9) Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 21 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com NOTE The stability requirement for minimum output capacitance must always be met. One recommended output capacitor combination is two 330-F, 15-m ESR tantalum polymer capacitors connected in parallel with a 47-F 6.3-V X5R ceramic. This combination provides excellent performance that may exceed the requirements of certain applications. Additionally some small 47-nF ceramic capacitors can be used for high-frequency EMI suppression. 8.2.2.7 CIN Selection The LMZ23608 module contains two internal ceramic input capacitors. Additional input capacitance is required external to the module to handle the input ripple current of the application. The input capacitor can be several capacitors in parallel. This input capacitance must be located in very close proximity to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Input ripple current rating is dictated by the equation: ICIN-RMS = IOUT x D(1-D) where D VOUT / VIN * (10) As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when VIN = 2 x VOUT. Recommended minimum input capacitance is 30-F X7R (or X5R) ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. TI also recommends to pay attention to the voltage and temperature derating of the capacitor selected. NOTE Ripple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this parameter. If the system design requires a certain minimum value of peak-to-peak input ripple voltage (VIN) to be maintained then the following equation may be used. CIN 8 IOUT x D x (1 - D) fSW x 'VIN (11) If VIN is 200 mV or 1.66% of VIN for a 12-V input to 3.3-V output application and fSW = 350 kHz then: 8A x CIN 8 3.3V * 3.3V* x 1(c) 12V (c) 12V 350 kHz x 200mV 8 22.4F (12) Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines. The LMZ23608 typical applications schematic and evaluation board include a 150-F 50-V aluminum capacitor for this function. There are many situations where this capacitor is not necessary. 8.2.2.8 Discontinuous Conduction and Continuous Conduction Modes Selection The approximate formula for determining the DCM/CCM boundary is as follows: (VIN - VOUT) x D IDCB = 2 x L x fSW (13) The inductor internal to the module is 2.2 H. This value was chosen as a good balance between low and high input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple current (iL). iL can be calculated with: (VIN - VOUT) x D 'iL = L x fSW 22 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 where * * VIN is the maximum input voltage and fSW is typically 359 kHz. (14) If the output current IOUT is determined by assuming that IOUT = IL, the higher and lower peak of iL can be determined. 8.2.3 Application Curves 100 MAXIMUM OUTPUT CURRENT (A) 10 EFFICIENCY (%) 90 80 70 60 50 40 30 24 Vin 20 0 1 2 3 4 5 6 OUTPUT CURRENT (A) 8 6 4 2 JA = 9.9 C/W JA = 6.8 C/W JA = 5.2 C/W 0 7 8 20 VIN = 24 V, VOUT = 3.3 V 40 60 80 100 TEMPERATURE (C) 120 VIN = 24 V, VOUT = 3.3 V Figure 54. Thermal Derating Curve Figure 53. Efficiency AMPLITUDE (dBV/m) 50 40 30 20 10 0 Horizontal Peak Vertical Peak Class B Limit Class A Limit 0 100 200 300 400 500 600 700 800 9001000 FREQUENCY (MHz) VIN = 24 V, VOUT = 5 V, IOUT = 8 A Figure 55. Radiated EMI (EN 55022) Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 23 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com 9 Power Supply Recommendations The LMZ23608 device is designed to operate from an input voltage supply range between 6 V and 36 V. This input supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the LMZ23608 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is more than a few inches from the LMZ23608, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-F or 100-F electrolytic capacitor is a typical choice. 10 Layout 10.1 Layout Guidelines PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. A good layout example is shown in Figure 59. 1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout as shown in the figure above. The high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor (CIN) is placed at a distance away from the LMZ23608. Therefore place CIN as close as possible to the LMZ23608 VIN and PGND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor must consist of a localized top side plane that connects to the PGND exposed pad (EP). 2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components must be routed to the AGND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Additionally provide a single point ground connection from pin 4 (AGND) to EP/PGND. 3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB must be located close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The traces from RFBT, RFBB must be routed away from the body of the LMZ23608 to minimize possible noise pickup. 4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy. 5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heatspreading ground planes. For best results use a 10 x 10 via array or larger with a minimum via diameter of 8 mil thermal vias spaced 46.8 mil (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125C. 24 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 10.2 Layout Examples VOUT VIN VOUT VIN High di/dt CIN COUT PGND Loop 2 Loop 1 Figure 56. Critical Current Loops to Minimize Top View Thermal Vias GND GND 3 4 5 6 7 8 9 10 11 AGND EN SH SS FB AGND COUT VOUT VOUT 2 VIN VIN EPAD 1 SYNC VIN CIN VOUT CSS Clock > RFBT Enable > CFF RFBB GND Plane Figure 57. PCB Layout Guide Figure 58. Top View of Evaluation PCB Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 25 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com Layout Examples (continued) Figure 59. Bottom View of Evaluation PCB 10.3 Power Dissipation and Thermal Considerations When calculating module dissipation use the maximum input voltage and the average output current for the application. Many common operating conditions are provided in the characteristic curves such that less common applications can be derived through interpolation. In all designs, the junction temperature must be kept below the rated maximum of 125C. For the design case of VIN = 12 V, VOUT = 3.3 V, IOUT = 8 A, and TA-MAX = 50C, the module must see a thermal resistance from case to ambient (CA) of less than: TJ-MAX TA-MAX - TJC TCA < PIC_LOSS (15) Given the typical thermal resistance from junction to case (JC) to be 1.0C/W. Use the 85C power dissipation curves in the Typical Characteristics section to estimate the PIC-LOSS for the application being designed. In this application it is 3.9 W. TCA < 125C - 50C - 1.0 C < 18.23 C 3.9 W W W (16) To reach CA = 18.23, the PCB is required to dissipate heat effectively. With no airflow and no external heat-sink, a good estimate of the required board area covered by 2-oz. copper on both the top and bottom metal layers is: Board Area_cm2 8 500 . C x cm 2 TCA W (17) As a result, approximately 27.42 square cm of 2-oz. copper on top and bottom layers is the minimum required area for the example PCB design. This is 5.23 x 5.23 cm (2.06 x 2.06 in) square. The PCB copper heat sink must be connected to the exposed pad. For best performance, use approximately 100, 8 mil thermal vias spaced 59 mil (1.5 mm) apart connect the top copper to the bottom copper. 26 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 Power Dissipation and Thermal Considerations (continued) Another way to estimate the temperature rise of a design is using JA. An estimate of JA for varying heat sinking copper areas and airflows can be found in the typical applications curves. If our design required the same operating conditions as before but had 225 LFPM of airflow. We locate the required JA of TJA < TJ-MAX - TA-MAX PIC_LOSS TJA < (125 - 50) C C < 19.23 3.9 W W (18) On the JA vs copper heatsinking curve, the copper area required for this application is now only 1 square inches. The airflow reduced the required heat sinking area by a factor of four. To reduce the heat sinking copper area further, this package is compatable with D3-PAK surface mount heat sinks. For an example of a high thermal performance PCB layout for SIMPLE SWITCHER power modules, refer to AN2093 SNVA460, AN-2084 SNVA456, AN-2125 SNVA473, AN-2020 SNVA419 and AN-2026 SNVA424. 10.4 Power Module SMT Guidelines The recommendations below are for a standard module surface mount assembly * Land Pattern -- Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads * Stencil Aperture - For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern - For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation * Solder Paste -- Use a standard SAC Alloy such as SAC 305, type 3 or higher * Stencil Thickness -- 0.125 to 0.15 mm * Reflow -- Refer to solder paste supplier recommendation and optimized per board size and density * Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information * Maximum number of reflows allowed is one Figure 60. Sample Reflow Profile Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 27 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com Power Module SMT Guidelines (continued) Table 2. Sample Reflow Profile Table 28 PROBE MAX TEMP (C) REACHED MAX TEMP TIME ABOVE 235C REACHED 235C TIME ABOVE 245C REACHED 245C TIME ABOVE 260C REACHED 260C 1 242.5 6.58 0.49 6.39 0.00 - 0.00 - 2 242.5 7.10 0.55 6.31 0.00 7.10 0.00 - 3 241.0 7.09 0.42 6.44 0.00 - 0.00 - Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 LMZ23608 www.ti.com SNVS708G - MARCH 2011 - REVISED AUGUST 2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support For developmental support, see the following: WEBENCH Tool, http://www.ti.com/webench 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: * AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, (SNVA425) * Absolute Maximum Ratings for Soldering, (SNOA549) * AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422) * AN-2085 LMZ23605/03, LMZ22005/03 Evaluation Board (SNVA457) * AN-2054 Evaluation Board for LM10000 - PowerWise AVS System Controller (SNVA437) * AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419) * AN-2093 LMZ23610/8/6 and LMZ22010/8/6 Current Sharing Evaluation Board (SNVA460) * AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules (SNVA424) * Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. SIMPLE SWITCHER is a registered trademark of Texas Insturments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 29 LMZ23608 SNVS708G - MARCH 2011 - REVISED AUGUST 2015 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 30 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LMZ23608 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMZ23608TZ/NOPB ACTIVE PFM NDY 11 32 RoHS & Green SN Level-3-245C-168 HR -40 to 85 LMZ23608 LMZ23608TZE/NOPB ACTIVE PFM NDY 11 250 RoHS & Green SN Level-3-245C-168 HR -40 to 85 LMZ23608 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 27-May-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMZ23608TZE/NOPB Package Package Pins Type Drawing PFM NDY 11 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 32.4 Pack Materials-Page 1 15.45 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.34 6.2 20.0 32.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 27-May-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMZ23608TZE/NOPB PFM NDY 11 250 367.0 367.0 55.0 Pack Materials-Page 2 MECHANICAL DATA NDY0011A BOTTOM SIDE OF PACKAGE TOP SIDE OF PACKAGE TZA11A (Rev F) www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI's products are provided subject to TI's Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI's provision of these resources does not expand or otherwise alter TI's applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2020, Texas Instruments Incorporated