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19-0479; Rev 1; 7/97
________________General Description
The MAX3664 low-power transimpedance preamplifier
for 622Mbps SDH/SONET applications consumes only
85mW. Operating from a single +3.3V supply, it converts
a small photodiode current to a measurable differential
voltage. A DC cancellation circuit provides a true differ-
ential output swing over a wide range of input current
levels, thus reducing pulse-width distortion. The differen-
tial outputs are back-terminated with 60Ωper side.
The transimpedance gain is nominally 6kΩ. For input
signal levels beyond approximately 100µAp-p, the
amplifier will limit the output swing to 900mV. The
MAX3664’s low 55nA input noise provides a typical
sensitivity of -33.2dBm in 1300nm, 622Mbps receivers.
The MAX3664 is designed to be used in conjunction
with the MAX3675 clock recovery and data retiming IC
with limiting amplifier. Together, they form a complete
3.3V, 622Mbps SDH/SONET receiver.
In die form, the MAX3664 is designed to fit on a header
with a PIN diode. It includes a filter connection, which
provides positive bias for the photodiode through a 1kΩ
resistor to VCC. The device is also available in 8-pin SO
and µMAX packages.
________________________Applications
SDH/SONET Receivers
PIN/Preamplifier Receivers
Regenerators for SDH/SONET
____________________________Features
♦Single +3.3V Supply Operation
♦55nARMS Input-Referred Noise
♦6kΩGain
♦85mW Power
♦300µA Peak Input Current
♦200ps Max Pulse-Width Distortion
♦Differential Output Drives 100ΩLoad
♦590MHz Bandwidth
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
________________________________________________________________
Maxim Integrated Products
1
MAX3664
MAX3675
LIMITING
AMP
100pF INREF2
1k
VCC
100Ω
0.01µF
47nF
VCC (+3.3V)
DATA
CLK
( ) ARE FOR MAX3664E/D (DICE) ONLY.
47nF
400pF
OUT+
OUT-
COMP
GND
VCC (+3.3V)
(FILT)
INREF1
IN
DATA
AND
CLOCK
RECOVERY
__________________________________________________Typical Application Circuit
PART
MAX3664E/D
MAX3664ESA
MAX3664EUA* -40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP. RANGE PIN-PACKAGE
Dice
8 SO
8 µMAX
EVALUATION KIT
AVAILABLE
_______________Ordering Information
Pin Configuration appears at end of data sheet.
* Contact factory for package availability.
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.3V ±0.3V, COMP = GND, 100Ωload between OUT+ and OUT-, TA= -40°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.) (Notes 1, 2)
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.3V ±0.3V, CCOMP = 400pF, CIN = 1.1pF, outputs terminated into 50Ω, 8-pin SO package in MAX3664 EV board,
TA= +25°C, unless otherwise noted.) (Notes 3, 4)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 3: AC Characteristics are guaranteed by design.
Note 4: CIN is the total capacitance at IN.
Note 5: PWD = |2 x Pulse width - Period |
2
Note 6: DC to 470MHz, measured with 3-pole Bessel filter at output.
Note 1: Dice are tested at Tj= +27°C.
Note 2: µMAX package tested at TA= +25°C to +85°C.
VCC........................................................................-0.5V to +5.5V
Continuous Current
IN, INREF1, INREF2, COMP, FILT....................................5mA
OUT+, OUT-...................................................................25mA
Continuous Power Dissipation (TA= +85°C)
SO (derate 5.88mW/°C above +85°C)........................383mW
µMAX (derate 4.1mW/°C above +85°C) .....................268mW
Operating Junction Temperature (die)..............-40°C to +150°C
Processing Temperature (die).........................................+400°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
IIN = 0
IIN = 0 to 20µA
IIN = 0 to 300µA
IIN = 300µA
Differential output
f < 1MHz, referred to output
IIN = 200µA, CCOMP = 400pF
CONDITIONS
mA12 25 35ICC
Supply Current %±5 V0.8 0.95VIN
Input Bias Voltage
Gain Nonlinearity
mV950VOUT(max)Maximum Output Voltage Ω40 60 75ZOUT
Output Impedance (per side)
kΩ4.5 6 7.5z21
Small-Signal Transimpedance VVCC - 1.3Output Common-Mode Level dB20PSRRPower-Supply Rejection Ratio mV±7∆VOUT
Differential Output Offset
UNITSMIN TYP MAXSYMBOLPARAMETER
Relative to gain at 10MHz
CIN = 1.1pF (Note 6), IIN = 0
2µA to 100µA peak input current,
50% duty cycle, 1–0 pattern
100µA to 300µA peak input current,
50% duty cycle, 1–0 pattern
CIN = 0.3pF (Note 6), IIN = 0
CONDITIONS
kHz150 MHz590BW-3dB
Small-Signal Bandwidth
Low-Frequency Cutoff
nA
73 86
in
RMS Noise Referred to Input
6 100 ps
80 200
PWD
Pulse-Width Distortion
(Note 5)
55
UNITSMIN TYP MAXSYMBOLPARAMETER
Ω800 1000 1200RFILT
Filter Resistor (die only)
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
_______________________________________________________________________________________
3
100
0-40 30 100
INPUT-REFERRED NOISE
vs. TEMPERATURE
30
20
40
10
70
90
80
60
MAX3664-01
JUNCTION TEMPERATURE (°C)
NOISE (nA)
-5 65
50
470MHz BANDWIDTH
CIN = 1.5pF
CIN = 0.5pF
CIN = 1.0pF
CIN IS SOURCE CAPACITANCE
PRESENTED TO DIE. INCLUDES PACKAGE
PARASITIC, PIN DIODE, AND PARASITIC
INTERCONNECT CAPACITANCE
80
78
76
10k 100k 10M 10G
SMALL-SIGNAL GAIN
vs. FREQUENCY
62
60
72
70
74
68
MAX3664-02
FREQUENCY (Hz)
GAIN (dB)
1M 100M
64
66
1G
MAX3664 IN EV BOARD
COMP CONNECTED
TO GROUND
COMP CONNECTED
THROUGH 400pF
TO GROUND
200
-50 -40 25 45 85
PULSE-WIDTH DISTORTION
vs. TEMPERATURE
0
100
150
MAX3664-03
AMBIENT TEMPERATURE (°C)
PWD (ps)
-25 0 65
50
IIN = 100µA
IIN = 300µA
MAX3664 IN EV BOARD
1000
0.1 1 10 100 1000
INPUT-REFERRED RMS NOISE CURRENT
vs. DC INPUT CURRENT
MAX3664-04
DC INPUT CURRENT (µA)
RMS NOISE CURRENT (nA)
10
100
CSTC = 0.5pF
470MHz BANDWIDTH
300
00 80 100 120 160
LOW-FREQUENCY CUTOFF
vs. AVERAGE INPUT CURRENT
50
150
250
200
MAX3664-07
AVERAGE INPUT CURRENT (µA)
LOW-FREQUENCY CUTOFF (kHz)
20 40 60 140
100
CCOMP = 50pF
CCOMP = 100pF
CCOMP = 200pF
CCOMP = 400pF
CCOMP = 1000pF
6400
5800 -40 30 100
SMALL-SIGNAL TRANSIMPEDANCE
vs. TEMPERATURE
5900
6000
6200
6300
MAX3664-05
JUNCTION TEMPERATURE (°C)
TRANSIMPEDANCE (Ω)
-5 65
6100 VCC = 3V
MEASUREMENT FREQUENCY = 20MHz
VCC = 3.6V
650
400 -40 30 100
BANDWIDTH vs. TEMPERATURE
450
500
550
600
MAX3664-06
JUNCTION TEMPERATURE (°C)
BANDWIDTH (MHz)
-5 65
CIN = 0.5pF
CIN = 1.0pF
CIN = 1.5pF
CIN IS SOURCE CAPACITANCE
PRESENTED TO DIE. INCLUDES PACKAGE
PARASITIC, PIN DIODE, AND PARASITIC
INTERCONNECT CAPACITANCE
120
00 150 200 300
DATA-DEPENDENT JITTER
vs. INPUT SIGNAL AMPLITUDE
20
60
100
80
MAX3664-08
PEAK-TO-PEAK AMPLITUDE (µA)
PEAK-TO-PEAK JITTER (ps)
50 100 250
40
CCOMP = 100pF
CCOMP = 200pF
CCOMP = 400pF
CCOMP = 800pF
EXTINCTION RATIO > 10
INPUT: 213 - 1 PRBS
CONTAINS 72 ZEROS
__________________________________________Typical Operating Characteristics
(VCC = +3.3V, CCOMP = 400pF, TA= +25°C, unless otherwise noted.)
-1.15
-1.40 -40 40 60 100
OUTPUT COMMON-MODE VOLTAGE
(REFERENCED TO VCC) vs. TEMPERATURE
-1.35
-1.30
-1.20
-1.25
MAX3664-09
AMBIENT TEMPERATURE (°C)
COMMON-MODE VOLTAGE (V)
-20 0 20 80
VCC = 3.0V
VCC = 3.3V
VCC = 3.6V
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
4 _______________________________________________________________________________________
_____________________________Typical Operating Characteristics (continued)
(VCC = +3.3V, CCOMP = 400pF, TA= +25°C, unless otherwise noted.)
800
200 -40 40 60 100
OUTPUT AMPLITUDE
vs. TEMPERATURE
300
500
700
600
MAX3664-10
AMBIENT TEMPERATURE (°C)
AMPLITUDE (mV)
-20 0 20 80
400
INPUT = 300µAp-p VCC = 3.6V
VCC = 3.3V
VCC = 3.0V
EYE DIAGRAM
(INPUT = 300µAp-p)
100mV/
div
MAX3664-12
300ps/div
INPUT: 213 - 1 PRBS
CONTAINS 72 ZEROS
DC
CANCELLATION
AMP
PARAPHASE
AMP
VCC
VCC
VCC
VCC
D1
Q2
Q3
R3
R4
R2
R1 OUT+
(FILT)
OUT-
1k
6k
Q1
INREF2
INREF1
IN
Q4
TRANSIMPEDANCE
AMP
COMP
MAX3664
( ) ARE FOR MAX3664E/D (DIE) ONLY.
RF
_____________________Pin Description
NAME FUNCTION
1VCC +3.3V Supply Voltage
2 IN Signal Input
PIN
3, 4 INREF1,
INREF2 Input References 1 and 2. Connect to
photodetector AC ground.
5 GND Ground
— FILT*
Filter Connection. Provides positive
bias for photodiode through a 1kΩ
resistor to VCC. See
Step 3:
Designing Filters
. (This pad is acces-
sible on the die only.)
8 COMP
External Compensation Capacitor for
DC cancellation loop. Connect 400pF
or more from COMP to GND for nor-
mal operation. Connect COMP directly
to GND to disable the DC cancellation
loop.
7 OUT- Inverting Voltage Output. Current flow-
ing into IN causes VOUT- to decrease.
6 OUT+ Noninverting Voltage Output. Current
flowing into IN causes VOUT+ to
increase.
* MAX3664E/D (die) only. Figure 1. Functional Diagram
________________Detailed Description
The MAX3664 is a transimpedance amplifier designed
for 622Mbps SDH/SONET applications. It comprises a
transimpedance amplifier, a paraphase amplifier with
emitter-follower outputs, and a DC cancellation loop.
Figure 1 is a functional diagram of the MAX3664.
Transimpedance Amplifier
The signal current at IN flows into the summing node of
a high-gain amplifier. Shunt feedback through RFcon-
verts this current to a voltage with a gain of 6kΩ. Diode
D1 clamps the output voltage for large input currents.
INREF1 is a direct connection to the emitter of the input
transistor, and must be connected directly to the pho-
todetector AC ground return for best performance.
Paraphase Amplifier
The paraphase amplifier converts single-ended inputs to
differential outputs, and introduces a voltage gain of 2.
This signal drives a pair of internally biased emitter follow-
ers, Q2 and Q3, which form the output stage. Resistors
R1 and R2 provide back-termination at the output,
absorbing reflections between the MAX3664 and its load.
The output emitter followers are designed to drive a
100Ωdifferential load between OUT+ and OUT-. They
can also drive higher output impedances, resulting in
increased gain and output voltage swing.
DC Cancellation Loop
The DC cancellation loop removes the DC component
of the input signal by using low-frequency feedback.
This feature centers the signal within the MAX3664’s
dynamic range, reducing pulse-width distortion on
large input signals.
The output of the paraphase amplifier is sensed through
resistors R3 and R4 and then filtered, amplified, and fed
back to the base of transistor Q4. The transistor draws
the DC component of the input signal away from the
transimpedance amplifier’s summing node.
The COMP pin sets the DC cancellation loop’s
response. Connect 400pF or more between COMP and
GND for normal operation. Connect the pin directly to
GND to disable the loop. The DC cancellation loop can
sink up to 300µA of current at the input. When operated
with CCOMP = 400pF, the loop takes approximately
20µs to stabilize.
The MAX3664 minimizes pulse-width distortion for data
sequences that exhibit a 50% duty cycle. A duty cycle
other than 50% causes the device to generate pulse-
width distortion.
DC cancellation current is drawn from the input and
adds noise. For low-level signals with little or no DC
component, this is not a problem. Preamplifier noise will
increase for signals with significant DC component.
___________Applications Information
The MAX3664 is a low-noise, wide-bandwidth transim-
pedance amplifier that is ideal for 622Mbps SDH/
SONET receivers. Its features allow easy design into a
fiber optic module, in four simple steps.
Step 1: Selecting a Preamplifier for a 622Mbps
Receiver
Fiber optic systems place requirements on the band-
width, gain, and noise of the transimpedance preampli-
fier. The MAX3664 optimizes these characteristics for
SDH/SONET receiver applications that operate at
622Mbps.
In general, the bandwidth of a fiber optic preamplifier
should be 0.6 to 1 times the data rate. Therefore, in a
622Mbps system, the bandwidth should be between
375MHz and 622MHz. Lower bandwidth causes pat-
tern-dependent jitter and a lower signal-to-noise ratio,
while higher bandwidth increases thermal noise. The
MAX3664 typical bandwidth is 590MHz, making it ideal
for 622Mbps applications.
The preamplifier’s transimpedance must be high
enough to ensure that expected input signals generate
output levels exceeding the sensitivity of the limiting
amplifier (quantizer) in the following stage. The
MAX3675 clock recovery and limiting amplifier IC has
an input sensitivity of 3.6mVp-p, which means that
3.6mVp-p is the minimum signal amplitude required to
produce a fully limited output. Therefore, when used
with the MAX3664, which has a 6kΩtransimpedance,
the minimum detectable photodetector current is 600nA.
It is common to relate peak-to-peak input signals to
average optical power. The relationship between opti-
cal input power and output current for a photodetector
is called the responsivity (ρ), with units Amperes/Watt
(A/W). The photodetector peak-to-peak current is relat-
ed to the peak-to-peak optical power as follows:
Ip-p = (Pp-p)(ρ)
Based on the assumption that SDH/SONET signals
maintain a 50% duty cycle, the following equations
relate peak-to-peak optical power to average optical
power and extinction ratio (Figure 2):
Average Optical Power = PAVE = (P0 + P1) / 2
Extinction Ratio = re= P1 / P0
Peak-to-Peak Signal Amplitude = Pp-p = P1 - P0
Therefore,PAVE = Pp-p (1 / 2)[(re+ 1) / (re- 1)]
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
_______________________________________________________________________________________ 5
MAX3664
In a system where the photodiode responsivity is
0.9A/W and the extinction ratio is 10, the MAX3664/
MAX3675 receiver with 670nA gain sensitivity will deliv-
er a fully limited output for signals of average optical
power larger than:
(600nA / 0.9A/W)(1 / 2)(11 / 9) = 407nW ⇒-33.9dBm
Sensitivity is a key specification of the receiver module.
The ITU/Bellcore specifications for SDH/SONET
receivers require a link sensitivity of -27dBm with a bit
error rate (BER) of 1E - 10. There is an additional 1dB
power penalty to accommodate various system losses;
therefore, the sensitivity of a 622Mbps receiver must be
better than -28dBm.
Although several parameters affect sensitivity (such as
the quantizer sensitivity and preamplifier gain, as previ-
ously discussed), most fiber optic receivers are designed
so that noise is the dominant factor. Noise from the high-
gain transimpedance amplifier, in particular, determines
the sensitivity. The noise generated by the MAX3664 can
be modeled with a Gaussian distribution. In this case, a
BER of 1E - 10 corresponds to a peak-to-peak signal
amplitude to RMS noise ratio (SNR) of 12.7. The
MAX3664’s typical input-referred noise, in, (bandwidth-
limited to 470MHz) is 55nARMS. Therefore, the minimum
input for a BER of 1E - 10 is (12.7 x 55nA) = 700nAp-p.
Rearranging the previous equations in these terms
results in the following relation:
Optical Sensitivity (dBm) =
-10log[(in/ ρ)(SNR)(1/2)(re+ 1) / (re- 1)(1000)]
At room temperature, with re= 10, SNR = 12.7, in=
55nA, and ρ= 0.9A/W, the MAX3664 sensitivity is
-33.2dBm. At +85°C, noise increases to 62nA and sen-
sitivity decreases to -32.7dBm. The MAX3664 provides
4.7dB margin over the SDH/SONET specifications, even
at +85°C.
The largest allowable input to an optical receiver is called
the input overload. The MAX3664’s largest input current
(Imax) is 300µAp-p, with 200ps of pulse-width distortion.
The pulse-width distortion and input current are closely
related (see
Typical Operating Characteristics
). If the
clock recovery circuit can accept more pulse-width dis-
tortion, a higher input current might be acceptable. For
worst-case responsivity and extinction ratio, ρ= 1A/W
and re= ∞, the input overload is:
Overload (dBm) = -10log (Imax)(1 / 2)(1000)
For Imax = 300µA, the MAX3664 overload is -8.2dBm.
Step 2: Selecting Time Constants
A receiver built with the MAX3664 will have a bandpass
frequency response. The low-frequency cutoff causes
unwanted data-dependent jitter and sensitivity loss.
Because SDH/SONET data streams contain scrambled
data, certain data sequences may generate continuous
successions of 1s or 0s. The low-frequency cutoff
forces the output of such sequences to zero, ultimately
causing a sensitivity reduction. The SDH specifications
state that a receiver must be able to handle up to 72
consecutive bits of the same value within the data.
Therefore, choose the low-frequency cutoff to ensure
an acceptable amount of data-dependent jitter and
sensitivity loss.
Determine the reduction in signal-to-noise ratio due to a
transitionless sequence of duration t as follows:
SNRloss = 1 - e-t / τ= 1-e-(2πfct)
where τis the time constant of the offset correction, fc
is the low-frequency cutoff, and t is the time for 72 bits
(116ns for a 622Mbps data rate).
Suppose that the receiver should not have more than
0.25dB (6%) of sensitivity loss due to a 72-bit transition-
less sequence. This means that:
(1 - e-(2πfc)(116ns))< 0.06
fc= (ln 0.94) / [(-2π)(116ns)] = 85kHz (max)
The loss of sensitivity is a concern only when the SNR is
small (close to 12.7), which occurs with input currents
less than 3µAp-p.
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
6 _______________________________________________________________________________________
POWER
TIME
P0
P1
PAVE
Figure 2. Optical Power Definitions
The cutoff frequency also affects the data-dependent
jitter (DDJ). DDJ due to low-frequency cutoff can be
approximated as droop / slope, where the slope in
V/sec is measured at the 50% crossing of an eye dia-
gram, and droop is the loss-of-signal to noise calculat-
ed above as 1 - e-(2πfct). The slope at the 50% crossing
is typically two times the 10% to 90% slope, which is
approximately 0.35 / bandwidth. For a 622Mbps receiv-
er with a 470MHz bandwidth, the 10% to 90% rise time
is approximately 750ps. The slope through the 50%
crossing will be approximately:
Amplitude (2)(0.8) / 750ps =
1.6 Amplitude / 750ps = 2E9 Amplitude V/sec
DDJ = 2 [Amplitude (1 - e-(2πfct))] /
[ 2.0E9 Amplitude ] = (1 - e-(2πfct)) / (1E9)
OR
fc= -ln[1 - (1.0E9)(DDJ)] / [2πt]
If the maximum allowable DDJ is 100ps, and t = 112ns
for a 72-bit sequence, then the maximum low-frequency
cutoff is 150kHz.
Several circuits in the receiver can determine the low-
frequency cutoff. In a receiver using the MAX3664 and
MAX3675, there are three locations for concern:
1) The MAX3664’s DC cancellation circuit.
2) The coupling capacitors between the MAX3664
outputs and MAX3675 inputs.
3) The MAX3675’s offset correction circuit.
The highest cutoff frequency in the system determines
the amount of data-dependent jitter created.
The time constants of the MAX3675’s offset correction
and of the coupling capacitors should be separated by
a factor of ten (one decade) to prevent low-frequency
oscillations.
For example, select the offset correction of the MAX3664
to set the receiver cutoff frequency. Note that the
MAX3664’s low-frequency cutoff increases with average
input current. Since DDJ increases with fc, it follows that
DDJ increases as average input increases. When the
input signal is large enough to limit the outputs, however,
DDJ does not increase. Therefore, the maximum DDJ
results from the lowest input that causes the MAX3664
to have limited outputs (see
Typical Operating
Characteristics
), which is about 150µAp-p. When select-
ing a capacitor for the COMP pin that achieves your
desired DDJ, use the data from
Typical Operating
Characteristics
at IINPUT = 150µA.
In summary, use the following method to select the low-
frequency cutoff that will provide the sensitivity and
DDJ required for SDH/SONET receivers:
1) Determine the longest time without transitions.
2) Determine the acceptable loss of SNR ratio, and
the acceptable DDJ due to the transitionless time.
3) Estimate the low-frequency cutoff required for
either the worst-case SNR loss or for DDJ.
4) Select the location in the receiver to determine the
highest cutoff frequency. Normally, the MAX3664
would determine the dominant low-frequency cutoff.
Then select all other low-frequency cutoffs one
decade lower.
5) Select a capacitor for the COMP pin from the
Typical Operating Characteristics
graphs. 400pF is
adequate for most 622Mbps SDH/SONET applica-
tions.
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
_______________________________________________________________________________________ 7
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
8 _______________________________________________________________________________________
Step 3: Designing Filters
The MAX3664’s noise performance is a strong function
of the circuit’s bandwidth, which changes over temper-
ature and varies from lot to lot. The receiver sensitivity
can be improved by adding filters to limit this band-
width. Filter designs can range from a one-pole filter
using a single capacitor, to more complex filters using
inductors. Figure 3 illustrates two examples: the simple
filter provides moderate roll-off with minimal compo-
nents, while the complex filter provides a sharper roll-
off and better transient response.
Supply voltage noise at the cathode of the photodiode
produces a current I = CPHOTO (∆V/∆t), which reduces
the receiver sensitivity. CPHOTO is the photodiode
capacitance.
The FILT resistor of the MAX3664, combined with an
external capacitor (see
Typical Operating Circuit
) can
be used to reduce this noise. The external capacitor
(CFILT) is placed in parallel with the photodiode.
Current generated by supply noise is divided between
CFILT and CPHOTO. The input noise current due to sup-
ply noise is (assuming the filter capacitor is much larger
than the photodiode capacitance):
If the amount of tolerable noise is known, then the filter
capacitor can be easily selected:
For example, with maximum noise voltage = 100mVp-p,
CPHOTO = 0.5pF, RFILT = 1kΩ, and INOISE selected to
be 5nA (1/10 of MAX3664 input-referred noise):
Step 4: Designing a Low-Capacitance Input
Noise performance and bandwidth are adversely
affected by stray capacitance on the input node.
Select a low-capacitance photodiode and use good
high-frequency design and layout techniques to mini-
mize capacitance on this pin. The MAX3664 is
optimized for 0.5pF of capacitance on the input—
approximately the capacitance of a photodetector
diode sharing a common header with the MAX3664 in
die form.
Photodiode capacitance changes significantly with bias
voltage. With a 3.3V supply voltage, the reverse voltage
on the PIN diode is only 2.5V. If a higher voltage supply
is available, apply it to the diode to significantly reduce
capacitance.
Take great care to reduce input capacitance. With the
SO and µMAX versions of the MAX3664, the package
capacitance is about 0.3pF, and the PC board between
the MAX3664 input and the photodiode can add para-
sitic capacitance. Keep the input line short, and remove
power and ground planes beneath it. Packaging the
MAX3664 into a header with the photodiode provides
the best possible performance. It reduces parasitic
capacitance to a minimum, resulting in the lowest noise
and the best bandwidth.
MAX3664
C1
5pF
15.5nF
15.5nF
RL
100Ω
a) SIMPLE, 1-POLE, 530MHz FILTER
60Ω
60Ω
MAX3664
1.2pF 7.3pF RL
100Ω
b) 3-POLE, 470MHz BESSEL FILTER
60Ω
60Ω
Figure 3. Filter Design Examples
IV C
R C
NOISE NOISE PHOTO
FILT FILTER
=
( )( )
( )( )
C = V
FILT NOISE
( )( )
( )( )
C
R I PHOTO
FILT NOISE
C = 0.1
FILT
( )
−
( ) ( )
−
( )
[ ]
=0 5 12 1000 5 9 10. /E E nF
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
_______________________________________________________________________________________ 9
INREF1 and INREF2
Connect INREF1 and INREF2 as close to the AC
ground of the photodetector diode as possible. The
photodetector AC ground is usually the ground of the
filter capacitor from the photodetector anode. The total
loop (from INREF1/INREF2, through the bypass capaci-
tor and the diode, and back to IN) should be no more
than 2 cm. long.
Wire Bonding
For high current density and reliable operation, the
MAX3664 uses gold metallization. Make connections to
the die with gold wire only, and use ball bonding tech-
niques (wedge bonding is not recommended). Die-pad
size is 4 mils square, with a 6 mil pitch. Die thickness is
12 mils.
V
CC
and Ground
Use good high-frequency design and layout tech-
niques. The use of a multilayer circuit board with sepa-
rate ground and VCC planes is recommended. Take
care to bypass VCC and to connect the GND pin to the
ground plane with the shortest possible traces.
FILTER
CAP
OUT+ OUT-
OUT+ OUT-
IN
COMP
VCC
PIN DIODE
Figure 4. Suggested Layout for TO-46 Header
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
10 ______________________________________________________________________________________
___________________Pin Configuration ___________________Chip Topography
1
2
3
4
8
7
6
5
COMP
OUT-
OUT+
GND
INREF2
INREF1
IN
VCC
MAX3664
SO/µMAX
TOP VIEW
TRANSISTOR COUNT: 73
SUBSTRATE CONNECTED TO GND
OUT+
GND
INREF2
IN FILT INREF1
OUT-
COMP
VCC
0.032"
(0.81mm)
0.037"
(0.94mm)
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
______________________________________________________________________________________ 11
________________________________________________________Package Information
8LUMAXD.EPS
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SOICN.EPS
___________________________________________Package Information (continued)