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2007 Fairchild Semiconductor Corporation FDS6612A Rev D1 (W)
FDS6612A
Single N-Channel, Logic-Level, PowerTrench
MOSFET
General Description
This N-Channel Logic Level MOSFET is produced
using Fairchild Semiconductor’s advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
Features
• 8.4 A, 30 V. R
DS(ON)
= 22 mΩ @ V
GS
= 10 V
R
DS(ON)
= 30 mΩ @ V
GS
= 4.5 V
• Fast switching speed
• Low gate charge
• High performance trench technology for extremely
low R
DS(ON)
• High power and current handling capability
S
D
S
S
SO-8
D
D
D
G
D
DDD
SSSG
Pin 1
SO-8
4
3
2
1
5
6
7
8
Absolute Maximum Ratings T
A
=25
o
C unless otherwise noted
Symbol
Parameter Ratings Units
V
DSS
Drain-Source Voltage 30 V
V
GSS
Gate-Source Voltage ±20 V
I
D
Drain Current – Continuous
(Note 1a)
8.4 A
– Pulsed 40
Power Dissipation for Single Operation
(Note 1a)
2.5
P
D
(Note 1b)
1.0
W
E
AS
Single Pulse Avalanche Energy
(Note 3)
24 mJ
T
J
, T
STG
Operating and Storage Junction Temperature Range –55 to +150 °C
Thermal Characteristics
R
θJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
50 °C/W
R
θJA
Thermal Resistance, Junction-to-Ambient
(Note 1b)
125
R
θJC
Thermal Resistance, Junction-to-Case
(Note 1)
25
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS6612A FDS6612A 13’’ 12mm 2500 units
FDS6612A Single N-Channel, Logic-Level, PowerTrench
MOSFET
tm
April 2007
FDS6612A Rev D1 (W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol
Parameter Test Conditions Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 µA 30 V
∆BV
DSS
∆T
J
Breakdown Voltage Temperature
Coefficient I
D
= 250 µA, Referenced to 25°C
26 mV/°C
I
DSS
Zero Gate Voltage Drain Current V
DS
= 24 V, V
GS
= 0 V 1 µA
V
DS
= 24 V, V
GS
= 0 V, T
J
=55°C 10 µA
I
GSS
Gate–Body Leakage V
GS
= ±20 V, V
DS
= 0 V ±100
nA
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 250 µA 1 1.9
3 V
∆V
GS(th)
∆T
J
Gate Threshold Voltage
Temperature Coefficient I
D
= 250 µA, Referenced to 25°C
–4.4
mV/°C
R
DS(on)
Static Drain–Source
On–Resistance V
GS
= 10 V, I
D
= 8.4 A
V
GS
= 4.5 V, I
D
= 7.2 A
V
GS
= 10 V, I
D
= 8.4 A, T
J
=125°C
19
24
25
22
30
37
mΩ
I
D(on)
On–State Drain Current V
GS
= 10 V, V
DS
= 5 V 20 A
g
FS
Forward Transconductance V
DS
= 15 V, I
D
= 8.4 A 30 S
Dynamic Characteristics
C
iss
Input Capacitance 560
pF
C
oss
Output Capacitance 140
pF
C
rss
Reverse Transfer Capacitance
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
55 pF
R
G
Gate Resistance V
GS
= 15 mV, f = 1.0 MHz 2.5
Ω
Switching Characteristics
(Note 2)
t
d(on)
Turn–On Delay Time 7 14 ns
t
r
Turn–On Rise Time 5 10 ns
t
d(off)
Turn–Off Delay Time 22 35 ns
t
f
Turn–Off Fall Time
V
DD
= 15 V, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 6 Ω
3 6 ns
Q
g
Total Gate Charge 5.4
7.6 nC
Q
gs
Gate–Source Charge 1.7
nC
Q
gd
Gate–Drain Charge
V
DS
= 15 V, I
D
= 8.4 A,
V
GS
= 5 V
1.9
nC
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current 2.1 A
V
SD
Drain–Source Diode Forward
Voltage V
GS
= 0 V, I
S
= 2.1 A
(Note 2)
0.77
1.2 V
t
rr
Diode Reverse Recovery Time 19 nS
Q
rr
Diode Reverse Recovery Charge I
F
= 8.4 A, d
iF
/d
t
= 100 A/µs
9 nC
Notes:
1. R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θJC
is guaranteed by design while R
θCA
is determined by the user's board design.
a) 50°C/W when mounted
on a 1in
2
pad of 2 oz
copper
b) 125°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2 Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3 Starting TJ = 25°C, L = 1mH, I
AS
= 7A, V
DD
= 27V, V
GS
= 10V
FDS6612A Single N-Channel, Logic-Level, PowerTrench
MOSFET
FDS6612A Rev D1 (W)
Typical Characteristics
0
10
20
30
40
0 0.5 1 1.5 2 2.5 3
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
V
GS
= 10V 4.5V
3.5V
3.0V
6.0V
4.0V
0.8
1
1.2
1.4
1.6
1.8
2
0 10 20 30 40
I
D
, DRAIN CURRENT (A)
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 3.5V
4.5V
5.0V
10V
4.0V
6.0V
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.6
0.8
1
1.2
1.4
1.6
-50 -25 0 25 50 75 100 125 150
T
J
, JUNCTION TEMPERATURE (
o
C)
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I
D
= 8.4A
V
GS
= 10V
0
0.02
0.04
0.06
0.08
0.1
2 4 6 8 10
V
GS
, GATE TO SOURCE VOLTAGE (V)
R
DS(ON)
, ON-RESISTANCE (OHM)
I
D
= 4.2A
T
A
= 125
o
C
T
A
= 25
o
C
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
10
20
30
40
1.5 2 2.5 3 3.5 4 4.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
T
A
= 125
o
C
-55
o
C
25
o
C
V
DS
= 5V
0.0001
0.001
0.01
0.1
1
10
100
0 0.2 0.4 0.6 0.8 1 1.2
V
SD
,
BODY DIODE FORWARD VOLTAGE (V)
I
S
, REVERSE DRAIN CURRENT (A)
V
GS
= 0V
T
A
= 125
o
C
25
o
C
-55
o
C
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS6612A Single N-Channel, Logic-Level, PowerTrench
MOSFET
FDS6612A Rev D1 (W)
Typical Characteristics
0
2
4
6
8
10
0 2 4 6 8 10 12
Q
g
, GATE CHARGE (nC)
V
GS
, GATE-SOURCE VOLTAGE (V)
I
D
= 8.4A
V
DS
= 10V
15V
20V
0
200
400
600
800
0 5 10 15 20 25 30
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
C
oss
C
rss
f = 1 MHz
V
GS
= 0 V
C
iss
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.01 0.1 1 10 100
VDS, DRAIN-SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
DC
10s 1s
100ms
100
µ
s
R
DS(ON)
LIMIT
V
GS
= 10V
SINGLE PULSE
R
θJA
= 125
o
C/W
T
A
= 25
o
C
10ms
1ms
1
10
100
0.001 0.01 0.1 1 10 100
t
AV
, TIME IN AVALANCHE (mS)
I
AS
, AVALANCHE CURRENT (A)
25
125
Figure 9. Maximum Safe Operating Area. Figure 10. Unclamped Inductive Switching
Capability
0
10
20
30
40
50
0.001 0.01 0.1 1 10 100
t
1
, TIME (sec)
P(pk),PEAK TRANSIENT POWER (W)
SINGLE PULSE
R
θJA
= 125
o
C/W
T
A
= 25
o
C
Figure 11. Single Pulse Maximum Power Dissipation.
FDS6612A Single N-Channel, Logic-Level, PowerTrench
MOSFET
FDS6612A Rev D1 (W)
Typical Characteristics
0.001
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10 100 1000
t
1
, TIME (sec)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
R
θJA
(t) = r(t) * R
θJA
R
θJA
= 125
o
C/W
T
J
- T
A
= P * R
θJA
(t)
Duty Cycle, D = t
1
/ t
2
P(pk)
t
1
t
2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 12. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS6612A Single N-Channel, Logic-Level, PowerTrench
MOSFET
FDS6612A Rev D1 (W)
PSPICE Electrical Model N-Channel
.SUBCKT FDS6612A 2 1 3
*NOM TEMP=25 DEG C
*REV A - JULY 2003
CA 12 8 1E-9
CB 15 14 4.0E-10
CIN 6 8 5.1E-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 34.2
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LGATE 1 9 3.84E-9
LDRAIN 2 5 1.00E-9
LSOURCE 3 7 4E-9
RLGATE 1 9 38.4
RLDRAIN 2 5 10
RLSOURCE 3 7 40
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 8E-3
RGATE 9 20 4.2
RSLC1 5 51 RSLCMOD 1E-6
RSLC2 5 50 1E3
RSOURCE 8 7 RSOURCEMOD 7.5E-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1E-6*105),3))}
.MODEL DBODYMOD D (IS=7E-15 RS=6.1E-3 N=0.84 TRS1=1.7E-3 TRS2=1.0E-6
+ CJO=3.2E-10 TT=10E-9 M=0.5 IKF=0.3 XTI=3.0)
.MODEL DBREAKMOD D (RS=1E-1 TRS1=1.12E-3 TRS2=1.25E-6)
.MODEL DPLCAPMOD D (CJO=14E-11 IS=1E-30 N=10 M=0.34)
.MODEL MWEAKMOD NMOS (VTO=1.82 KP=0.05 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=42 RS=.1)
.MODEL MMEDMOD NMOS (VTO=2.1 KP=6 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=4.2)
.MODEL MSTROMOD NMOS (VTO=2.55 KP=50 IS=1E-30 N=10 TOX=1 L=1U W=1U)
.MODEL RBREAKMOD RES (TC1=0.83E-3 TC2=1E-7)
.MODEL RDRAINMOD RES (TC1=6E-3 TC2=5E-6)
.MODEL RSLCMOD RES (TC1=2.5E-3 TC2=4.5E-6)
.MODEL RSOURCEMOD RES (TC1=1.0E-3 TC2=1E-6)
.MODEL RVTHRESMOD RES (TC1=-2.013E-3 TC2=-7E-6)
.MODEL RVTEMPMOD RES (TC1=-1.5E-3 TC2=1E-6)
.MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.3 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-0.5 VOFF=-1.3)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURC E
RLSOU RCE
CIN
RDRAIN
EVTH RES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLC AP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
FDS6612A Single N-Channel, Logic-Level, PowerTrench
MOSFET
FDS6612A Rev D1 (W)
RTHERM6
RTHERM8
RTHERM7
RTHERM5
RTHERM4
RTHERM3
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
7
JUNCTION
AMBIENT
8
th
RTHERM2
RTHERM1
CTHERM7
CTHERM8
SPICE Thermal Model
.SUBCKT FDS6612A_THERM TH TL
*THERMAL MODEL SUBCIRCUIT
*REV A - JULY 2003
*MIN PAD RJA
CTHERM1 TH 8 0.005
CTHERM2 8 7 0.05
CTHERM3 7 6 0.10
CTHERM4 6 5 0.35
CTHERM5 5 4 0.45
CTHERM6 4 3 0.50
CTHERM7 3 2 0.55
CTHERM8 2 TL 3.00
RTHERM1 TH 8 5.000
RTHERM2 8 7 6.250
RTHERM3 7 6 7.500
RTHERM4 6 5 8.750
RTHERM5 5 4 10.625
RTHERM6 4 3 11.875
RTHERM7 3 2 31.250
RTHERM8 2 TL 43.750
.ENDS
FDS6612A Single N-Channel, Logic-Level, PowerTrench
MOSFET
©2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
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intended to be an exhaustive list of all such trademarks.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
ACEx®
Across the board. Around the world™
ActiveArray™
Bottomless™
Build it Now™
CoolFET™
CROSSVOLT™
CTL™
Current Transfer Logic™
DOME™
E2CMOS™
EcoSPARK®
EnSigna™
FACT Quiet Series™
FACT®
FAST®
FASTr™
FPS™
FRFET®
GlobalOptoisolator™
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IntelliMAX™
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MicroPak™
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PACMAN™
PDP-SPM™
POP™
Power220®
Power247®
PowerEdge™
PowerSaver™
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
ScalarPump™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TCM™
The Power Franchise®
™
TinyBoost™
TinyBuck™
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TruTranslation™
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UniFET™
VCX™
Wire™
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner
without notice.
Preliminary First Production This datasheet contains preliminary data; supplementary data will
be published at a later date. Fairchild Semiconductor reserves the
right to make changes at any time without notice to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at any time
without notice to improve design.
Obsolete Not In Production This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor.The datasheet is printed
for reference information only.
Rev. I26
tm
tm
HiSeC™
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