M95128 M95128-W M95128-R 128 Kbit Serial SPI bus EEPROM with high speed clock Feature summary Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Single Supply Voltage: - 4.5 to 5.5V for M95128 - 2.5 to 5.5V for M95128-W - 1.8 to 5.5V for M95128-R High Speed - 5MHz Clock Rate, 5ms Write Time Status Register Hardware Protection of the Status Register BYTE and PAGE WRITE (up to 64 Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection More than 100,000 Write Cycles More than 40-Year Data Retention Packages - ECOPACK(R) (RoHS compliant) June 2006 SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width Rev 7 1/41 www.st.com 1 Contents M95128, M95128-W, M95128-R Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7.1 4 5 2/41 3.7.2 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7.3 Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Data Protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 M95128, M95128-W, M95128-R 5.6.1 Contents ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 22 6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3/41 List of tables M95128, M95128-W, M95128-R List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. 4/41 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write-Protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating conditions (M95128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M95128-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M95128-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M95128, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M95128-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M95128-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC characteristics (M95128-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AC characteristics (M95128, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC characteristics (M95128-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC characteristics (M95128-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC characteristics (M95128-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP8 - 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 37 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 M95128, M95128-W, M95128-R List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 36 TSSOP8 - 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 37 5/41 Summary description 1 M95128, M95128-W, M95128-R Summary description These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized as 16384 x 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD). In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram VCC D Q C S M95128 W HOLD VSS AI12805 Figure 2. SO and TSSOP connections M95128 S Q W VSS 1 2 3 4 8 7 6 5 VCC HOLD C D AI12806 1. See Section 10: Package mechanical for package dimensions, and how to identify pin-1. 6/41 M95128, M95128-W, M95128-R Table 1. Summary description Signal names C Serial Clock D Serial Data Input Q Serial Data Output S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground 7/41 Memory organization 2 M95128, M95128-W, M95128-R Memory organization The memory is organized as shown in Figure 3. Figure 3. Block diagram HOLD W High Voltage Generator Control Logic S C D I/O Shift Register Q Address Register and Counter Data Register Size of the Read only EEPROM area Y Decoder Status Register 1 Page X Decoder AI01272C 8/41 M95128, M95128-W, M95128-R 3 Signal description Signal description See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device. 3.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 3.2 Serial Data Input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C). 3.3 Serial Clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). 3.4 Chip Select (S) When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. 3.5 Hold (HOLD) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 9/41 Signal description 3.6 M95128, M95128-W, M95128-R Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write instructions. 3.7 Supply voltage (VCC) 3.7.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage must be applied: this voltage must be a DC voltage within the specified [VCC(min), VCC(max)] range, as defined in Table 7, Table 8 and Table 9. In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package pins. The VCC voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 3.7.2 Power-up conditions When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip Select (S) signal is not allowed to float and must follow the VCC voltage. The S line should therefore be connected to VCC via a suitable pull-up resistor. In addition, the Chip Select (S) input offers a built-in safety feature, as it is both edge sensitive and level sensitive. Practically this means that after power-up, the device cannot become selected until a falling edge has first been detected on Chip Select (S). So the Chip Select (S) signal must first have been High and then gone Low before the first operation can be started. 3.7.3 Internal device reset In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any instruction until the VCC has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Section 9: DC and AC parameters). When VCC has passed the POR threshold voltage, the device is reset and in the following state: 10/41 in Standby Power mode deselected (at next Power-up, a falling edge is required on Chip Select (S) before any instructions can be executed) not in the Hold Condition Status Register state: - the Write Enable Latch (WEL) bit is reset to 0 - the Write In Progress (WIP) bit is reset to 0. The SRWD, BP1 and BP0 bits of the Status Register are at the same logic level as when the device was last powered down (they are non-volatile bits). M95128, M95128-W, M95128-R 3.7.4 Operating features Power-down At Power-down, the device must be deselected and in Standby Power mode (that is, there should be no internal Write cycle in progress). Chip Select (S) should be allowed to follow the voltage applied on VCC. 4 Operating features 4.1 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as Serial Clock (C) already being Low (as shown in Figure 4). The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 4 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being Low. Figure 4. Hold condition activation C HOLD Hold Condition Hold Condition AI02029D 11/41 Operating features 4.2 M95128, M95128-W, M95128-R Status Register Figure 3 shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. For a detailed description of the Status Register bits, see Section 5.3: Read Status Register (RDSR). 4.3 Data Protection and protocol control Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms: Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Write (WRITE) instruction completion The Block Protect (BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode (SPM). The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits to be protected. This is the Hardware Protected Mode (HPM). For any instruction to be accepted, and executed, Chip Select (S) must be driven High after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence: The `last bit of the instruction' can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). The `next rising edge of Serial Clock (C)' might (or might not) be the next bus transaction for some other device on the SPI bus. Table 2. Write-Protected block size Status Register Bits Array Addresses Protected Protected Block 12/41 BP1 BP0 M95128, M95128-W, M95128-R 0 0 none none 0 1 Upper quarter 3000h - 3FFFh 1 0 Upper half 2000h - 3FFFh 1 1 Whole memory 0000h - 3FFFh M95128, M95128-W, M95128-R 5 Instructions Instructions Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3. Instruction set Instruction 5.1 Description Instruction Format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 5, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. Figure 5. Write Enable (WREN) sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI02281E 13/41 Instructions 5.2 M95128, M95128-W, M95128-R Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 6, to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Figure 6. Write Disable (WRDI) sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI03750D 14/41 M95128, M95128-W, M95128-R 5.3 Instructions Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 7. The status and control bits of the Status Register are as follows: 5.3.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 5.3.2 WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted. 5.3.3 BP1, BP0 bits The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 4) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. 5.3.4 SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format b7 SRWD b0 0 0 0 BP1 BP0 WEL WIP Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit 15/41 Instructions M95128, M95128-W, M95128-R Figure 7. Read Status Register (RDSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Status Register Out Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB AI02031E 16/41 M95128, M95128-W, M95128-R 5.4 Instructions Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 8. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as readonly, as defined in Table 4. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at their current values from just before the start of the execution of Write Status Register (WRSR) instruction. The new, updated, values take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction. 17/41 Instructions M95128, M95128-W, M95128-R Table 5. Protection modes W Signal SRWD Bit 1 0 0 0 1 0 1 1 Mode Write Protection of the Status Register Status Register is Writable (if the WREN Software instruction has set the Protected WEL bit) (SPM) The values in the BP1 and BP0 bits can be changed Memory Content Protected Area(1) Unprotected Area(1) Write Protected Ready to accept Write instructions Status Register is Hardware write Hardware protected Protected Write Protected (HPM) The values in the BP1 and BP0 bits cannot be changed Ready to accept Write instructions 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5. The protection features of the device are summarized in Table 2. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W): If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used. 18/41 M95128, M95128-W, M95128-R Figure 8. Instructions Write Status Register (WRSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction Status Register In 7 D High Impedance 6 5 4 3 2 1 0 MSB Q AI02282D 19/41 Instructions 5.5 M95128, M95128-W, M95128-R Read from Memory Array (READ) As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven Low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Figure 9. Read from Memory Array (READ) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 1 0 MSB Data Out 1 High Impedance Q 7 6 5 4 3 2 Data Out 2 1 0 7 MSB AI01793D 1. The most significant address bits (b15, b14) are Don't Care. 20/41 M95128, M95128-W, M95128-R 5.6 Instructions Write to Memory Array (WRITE) As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input data. In the case of Figure 10, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period tWC (as specified in Table 16 to Table 19), at the end of which the Write in Progress (WIP) bit is reset to 0. If, though, Chip Select (S) continues to be driven Low, as shown in Figure 11, the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 64 bytes). The instruction is not accepted, and is not executed, under the following conditions: if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) if a Write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven High, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits. Figure 10. Byte Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 Data Byte 1 0 7 6 5 4 3 2 1 0 High Impedance Q AI01795D 1. The most significant address bits (b15, b14) are Don't Care. 21/41 Instructions M95128, M95128-W, M95128-R Figure 11. Page Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 Data Byte 1 1 0 7 6 5 4 3 2 0 1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 D 7 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte N 1 0 6 5 4 3 2 1 0 AI01796D 1. The most significant address bits (b15, b14) are Don't Care. 5.6.1 ECC (Error Correction Code) and Write cycling The M95128 (5V version, processed in F6DP26%, identified with letter "V") offers an ECC (Error Correction Code) logic which compares each 4-Byte packet with its associated ECC Word (6 EEPROM bits). As a result, if a single bit out of 4 Bytes of data happens to be erroneous during a Read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even though a single Byte has to be written, 4 Bytes are internally modified (plus the ECC Word), that is, the addressed Byte is cycled together with the three other Bytes making up the packet. It is therefore recommended to Write by packets of 4 Bytes in order to benefit from the larger amount of Write cycles. The maximum number of Write cycles for the M95128 device (5V version, processed in F6DP26%, identified with letter "V") is qualified as 100,000 Write cycles, using a cycling routine that writes to the device Page by Page (that is, by multiples of 4-Byte packets). The M95128-W and M95128-R devices (2.5V and 1.8V versions, processed in F6DP36% and identified with the letter "A") do not offer the ECC logic and are qualified for a maximum number of 100,000 Write cycles. 22/41 M95128, M95128-W, M95128-R 6 Delivery state Delivery state The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0. 7 Connecting to the SPI bus These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 12 shows three devices, connected to an MCU, on a SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance. Figure 12. Bus master and memory devices on the SPI bus VSS VCC R(2) SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C Q D Bus Master SPI Memory Device R(2) CS3 VCC C Q D VSS VCC C Q D VSS SPI Memory Device R(2) VSS SPI Memory Device R(2) CS2 CS1 S W HOLD S W HOLD S W HOLD AI12304b 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. 2. These pull-up resistors, R, ensure that the M95128, M95128-W, M95128-R are not selected if the Bus Master leaves the S line in the high-impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (that is when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). 23/41 Connecting to the SPI bus 7.1 M95128, M95128-W, M95128-R SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 13, is the clock polarity when the bus master is in Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 13. SPI modes supported CPOL CPHA 0 0 C 1 1 C D Q MSB MSB AI01438B 24/41 M95128, M95128-W, M95128-R 8 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 6 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute maximum ratings Symbol TA TSTG Parameter Min. Max. Unit Ambient Operating Temperature -40 130 C Storage Temperature -65 150 C VO Output Voltage -0.50 VCC+0.6 V VI Input Voltage -0.50 6.5 V VCC Supply Voltage -0.50 6.5 V VESD Electrostatic Discharge Voltage (Human Body model)(1) -4000 4000 V 1. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500W, R2=500). 25/41 DC and AC parameters 9 M95128, M95128-W, M95128-R DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7. Operating conditions (M95128) Symbol VCC TA Table 8. Parameter Min. Max. Unit Supply Voltage 4.5 5.5 V Ambient Operating Temperature (Device Grade 3) -40 125 C Operating conditions (M95128-W) Symbol VCC TA Table 9. Parameter Min. Max. Unit Supply Voltage 2.5 5.5 V Ambient Operating Temperature (Device Grade 6) -40 85 C Ambient Operating Temperature (Device Grade 3) -40 125 C Operating conditions (M95128-R) Symbol VCC TA 26/41 Parameter Min. Max. Unit Supply Voltage 1.8 5.5 V Ambient Operating Temperature -40 85 C M95128, M95128-W, M95128-R Table 10. DC and AC parameters AC measurement conditions(1) Symbol CL Parameter Min. Load Capacitance Max. Unit 100 Input Rise and Fall Times pF 50 ns Input Pulse Voltages 0.2VCC to 0.8VCC V Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 14. AC measurement I/O waveform Input Levels Input and Output Timing Reference Levels 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI00825B Table 11. Symbol COUT CIN Capacitance(1) Parameter Output Capacitance (Q) Test Condition Min. Max. Unit VOUT = 0V 8 pF Input Capacitance (D) VIN = 0V 8 pF Input Capacitance (other pins) VIN = 0V 6 pF 1. Sampled only, not 100% tested, at TA=25C and a frequency of 5 MHz. 27/41 DC and AC parameters Table 12. M95128, M95128-W, M95128-R DC characteristics (M95128, Device Grade 3) Symbol Parameter Test Condition ILI Input Leakage Current ILO Min. Max. Unit VIN = VSS or VCC 2 A Output Leakage Current S = VCC, VOUT = VSS or VCC 2 A ICC Supply Current C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5 V, Q = open 4 mA ICC1 Supply Current (Standby Power mode) S = VCC, VCC = 5 V, VIN = VSS or VCC 5 A VIL Input Low Voltage -0.45 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC+1 V VOL(1) Output Low Voltage IOL = 2 mA, VCC = 5 V 0.4 V VOH(1) Output High Voltage IOH = -2 mA, VCC = 5 V 0.8 VCC V 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards. Table 13. Symbol DC characteristics (M95128-W, Device Grade 6) Parameter ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current (Read) Test Condition Max. Unit VIN = VSS or VCC 2 A S = VCC, VOUT = VSS or VCC 2 A C = 0.1VCC/0.9VCC at 5MHz, VCC = 2.5V, Q = open 3 mA C = 0.1VCC/0.9VCC at 5MHz, VCC = 5V, Q = open 5 mA ICC0(1) Supply Current (Write) During tW, S = VCC, 2.5V < VCC < 5.5V 5 mA ICC1 Supply Current (Standby Power mode) S = VCC, VIN = VSS or VCC, 2.5V < VCC < 5.5V 5 A VIL Input Low Voltage -0.45 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC+1 V VOL Output Low Voltage 0.4 V VOH Output High Voltage VCC = 2.5V and IOL = 1.5mA or VCC = 5V and IOL = 2mA VCC = 2.5V and IOH = -0.4mA or 0.8 VCC VCC = 5V and IOH = -2mA 1. Characterized value, not tested in production. 28/41 Min. V M95128, M95128-W, M95128-R Table 14. Symbol DC and AC parameters DC characteristics (M95128-W, Device Grade 3) Parameter Test Condition Min. Max. Unit VIN = VSS or VCC 2 A ILI Input Leakage Current ILO Output Leakage Current S = VCC, VOUT = VSS or VCC 2 A ICC Supply Current (Read) C = 0.1VCC/0.9VCC at 5MHz, VCC = 2.5V, Q = open 3 mA ICC0(1) Supply Current (Write) During tW, S = VCC, 2.5V < VCC < 5.5V 6 mA ICC1 Supply Current (Standby Power mode) S = VCC, VIN = VSS or VCC 2.5V < VCC < 5.5V, 5 A VIL Input Low Voltage -0.45 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC+1 V VOL Output Low Voltage VCC = 2.5V and IOL = 1.5mA or VCC = 5V and IOL = 2mA 0.4 V VOH Output High Voltage VCC = 2.5V and IOH = -0.4mA or VCC = 5V and IOH = -2mA 0.8 VCC V 1. Characterized value, not tested in production. Table 15. Symbol DC characteristics (M95128-R) Parameter Test Condition Min Max Unit VIN = VSS or VCC 2 A S = VCC, VOUT = VSS or VCC 2 A ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current (Read) C = 0.1VCC/0.9VCC at 2 MHz, VCC = 1.8 V, Q = open 1 (1) mA ICC0(2) Supply Current (Write) During tW, S = VCC, 1.8V < VCC < 5.5V 3 mA S = VCC, VIN = VSS or VCC, 1.8V < VCC < 5.5V 3(1) A ICC1 Supply Current (Standby Power mode) VIL Input Low Voltage -0.45 0.25 VCC V VIH Input High Voltage 0.7 VCC VCC+1 V VOL Output Low Voltage IOL = 0.15 mA, VCC = 1.8 V 0.3 V VOH Output High Voltage IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC V 1. This is preliminary data. 2. Characterized value, not tested in production. 29/41 DC and AC parameters Table 16. M95128, M95128-W, M95128-R AC characteristics (M95128, Device Grade 3) Test conditions specified in Table 10 and Table 7 Symbol Alt. fC fSCK Clock Frequency tSLCH tCSS1 S Active Setup Time 90 ns tSHCH tCSS2 S Not Active Setup Time 90 ns tSHSL tCS S Deselect Time 100 ns tCHSH tCSH S Active Hold Time 90 ns S Not Active Hold Time 90 ns tCHSL Parameter Min. Max. Unit D.C. 5 MHz tCH (1) tCLH Clock High Time 90 ns (1) 90 ns tCLL Clock Low Time tCLCH (2) tRC Clock Rise Time 1 s tCHCL (2) tFC Clock Fall Time 1 s tCL tDVCH tDSU Data In Setup Time 20 ns tCHDX tDH Data In Hold Time 30 ns tHHCH Clock Low Hold Time after HOLD not Active 70 ns tHLCH Clock Low Hold Time after HOLD Active 40 ns tCLHL Clock Low Set-up Time before HOLD Active 0 ns tCLHH Clock Low Set-up Time before HOLD not Active 0 ns tSHQZ (2) tDIS tCLQV tV tCLQX Output Disable Time 100 ns Clock Low to Output Valid 60 ns tHO Output Hold Time tQLQH (2) tRO Output Rise Time 50 ns tQHQL (2) tFO Output Fall Time 50 ns tHHQV tLZ HOLD High to Output Valid 50 ns tHLQZ (2) tHZ HOLD Low to Output High-Z 100 ns tW tWC Write Time 5 ms 1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production. 30/41 0 ns M95128, M95128-W, M95128-R Table 17. DC and AC parameters AC characteristics (M95128-W, Device Grade 6) Test conditions specified in Table 10 and Table 8 Symbol Alt. fC fSCK Clock Frequency tSLCH tCSS1 S Active Setup Time 90 ns tSHCH tCSS2 S Not Active Setup Time 90 ns tSHSL tCS S Deselect Time 100 ns tCHSH tCSH S Active Hold Time 90 ns S Not Active Hold Time 90 ns tCHSL Parameter Min. Max. Unit D.C. 5 MHz tCH (1) tCLH Clock High Time 90 ns (1) 90 ns tCLL Clock Low Time tCLCH (2) tRC Clock Rise Time 1 s tCHCL (2) tFC Clock Fall Time 1 s tCL tDVCH tDSU Data In Setup Time 20 ns tCHDX tDH Data In Hold Time 30 ns tHHCH Clock Low Hold Time after HOLD not Active 70 ns tHLCH Clock Low Hold Time after HOLD Active 40 ns tCLHL Clock Low Set-up Time before HOLD Active 0 ns tCLHH Clock Low Set-up Time before HOLD not Active 0 ns tSHQZ (2) tDIS tCLQV tV tCLQX Output Disable Time 100 ns Clock Low to Output Valid 60 ns tHO Output Hold Time tQLQH (2) 0 ns tRO Output Rise Time 50 ns tQHQL (2) tFO Output Fall Time 50 ns tHHQV tLZ HOLD High to Output Valid 50 ns tHLQZ (2) tHZ HOLD Low to Output High-Z 100 ns tW tWC Write Time 5 ms 1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production. 31/41 DC and AC parameters Table 18. M95128, M95128-W, M95128-R AC characteristics (M95128-W, Device Grade 3) Test conditions specified in Table 10 and Table 8 Symbol Alt. fC fSCK Clock Frequency tSLCH tCSS1 S Active Setup Time 90 ns tSHCH tCSS2 S Not Active Setup Time 90 ns tSHSL tCS S Deselect Time 100 ns tCHSH tCSH S Active Hold Time 90 ns S Not Active Hold Time 90 ns tCHSL Parameter Max. Unit D.C. 5 MHz tCH (1) tCLH Clock High Time 90 ns (1) 90 ns tCLL Clock Low Time tCLCH (2) tRC Clock Rise Time 1 s tCHCL (2) tFC Clock Fall Time 1 s tCL tDVCH tDSU Data In Setup Time 20 ns tCHDX tDH Data In Hold Time 30 ns tHHCH Clock Low Hold Time after HOLD not Active 70 ns tHLCH Clock Low Hold Time after HOLD Active 40 ns tCLHL Clock Low Set-up Time before HOLD Active 0 ns tCLHH Clock Low Set-up Time before HOLD not Active 0 ns tSHQZ (2) tDIS tCLQV tV tCLQX Output Disable Time 100 ns Clock Low to Output Valid 60 ns tHO Output Hold Time tQLQH (2) tRO Output Rise Time 50 ns tQHQL (2) tFO Output Fall Time 50 ns tHHQV tLZ HOLD High to Output Valid 50 ns tHLQZ (2) tHZ HOLD Low to Output High-Z 100 ns tW tWC Write Time 5 ms 1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production. 32/41 Min. 0 ns M95128, M95128-W, M95128-R Table 19. DC and AC parameters AC characteristics (M95128-R) Test conditions specified in Table 10 and Table 9 Min.(1) Max.(1) Unit Clock Frequency D.C. 2 MHz tCSS1 S Active Setup Time 200 ns tSHCH tCSS2 S Not Active Setup Time 200 ns tSHSL tCS S Deselect Time 200 ns tCHSH tCSH S Active Hold Time 200 ns S Not Active Hold Time 200 ns Symbol Alt. fC fSCK tSLCH tCHSL Parameter tCH (2) tCLH Clock High Time 200 ns (2) 200 ns tCLL Clock Low Time tCLCH (3) tRC Clock Rise Time 1 s tCHCL (3) tFC Clock Fall Time 1 s tCL tDVCH tDSU Data In Setup Time 40 ns tCHDX tDH Data In Hold Time 50 ns tHHCH Clock Low Hold Time after HOLD not Active 140 ns tHLCH Clock Low Hold Time after HOLD Active 90 ns tCLHL Clock Low Set-up Time before HOLD Active 0 ns tCLHH Clock Low Set-up Time before HOLD not Active 0 ns tSHQZ (3) tDIS tCLQV tV tCLQX tHO Output Hold Time tQLQH (3) tRO Output Rise Time 100 ns (3) tFO Output Fall Time 100 ns tLZ HOLD High to Output Valid 100 ns tHZ HOLD Low to Output High-Z 250 ns tWC Write Time 10 ms tQHQL tHHQV tHLQZ tW (3) Output Disable Time 250 ns Clock Low to Output Valid 150 ns 0 ns 1. This is preliminary data. 2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 3. Value guaranteed by characterization, not 100% tested in production. 33/41 DC and AC parameters M95128, M95128-W, M95128-R Figure 15. Serial input timing tSHSL S tCHSL tSLCH tCHSH tSHCH C tDVCH tCHCL tCHDX LSB IN MSB IN D Q tCLCH High Impedance AI01447C Figure 16. Hold timing S tHLCH tCLHL tHHCH C tCLHH tHLQZ tHHQV Q D HOLD AI01448B 34/41 M95128, M95128-W, M95128-R DC and AC parameters Figure 17. Output timing S tCH C tCLQV tCLQX tCLQV tCL tSHQZ tCLQX LSB OUT Q tQLQH tQHQL D ADDR.LSB IN AI01449e 35/41 Package mechanical 10 M95128, M95128-W, M95128-R Package mechanical Figure 18. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package outline h x 45 A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 A1 L L1 SO-A 1. Drawing is not to scale. Table 20. SO8N - 8 lead Plastic Small Outline, 150 mils body width, package mechanical data millimeters inches Symbol Typ Min A Typ Min 1.75 Max 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.25 0.004 0.010 0.049 0.10 0.004 D 4.90 4.80 5.00 0.193 0.189 0.197 E 6.00 5.80 6.20 0.236 0.228 0.244 E1 3.90 3.80 4.00 0.154 0.150 0.157 e 1.27 - - 0.050 - - h 0.25 0.50 0.010 0.020 k 0 8 0 8 L 0.40 1.27 0.016 0.050 L1 36/41 Max 1.04 0.041 M95128, M95128-W, M95128-R Package mechanical Figure 19. TSSOP8 - 8 lead Thin Shrink Small Outline, package outline D 8 5 c E1 1 E 4 A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 21. TSSOP8 - 8 lead Thin Shrink Small Outline, package mechanical data millimeters inches Symbol Typ Min A Max Min 1.200 A1 0.050 0.150 0.800 1.050 b 0.190 c 0.090 A2 Typ 1.000 CP Max 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 0 8 0.0394 0 N 8 8 8 37/41 Part numbering 11 M95128, M95128-W, M95128-R Part numbering Table 22. Ordering information scheme Example: M95128 - W MN 6 T P /P Device Type M95 = SPI serial access EEPROM Device Function 128 = 128 Kbit (16384 x 8) Operating Voltage blank = VCC = 4.5 to 5.5V(1) W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V Package MN = SO8 (150 mils width) DW = TSSOP8 (169 mils width) Device Grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Device tested with High Reliability Certified Flow(2) Automotive temperature range (-40 to 125 C) Option blank = Standard Packing T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating P or G = ECOPACK(R) (RoHs compliant) Process P = F6DP26% Chartered V = F6DP26% Rsst 1. The M95128 5V part is offered in "V" process (F6DP26%) only. 2. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 38/41 M95128, M95128-W, M95128-R 12 Revision history Revision history Table 23. Document revision history Date Revision Changes 17-Nov-1999 2.1 New -V voltage range added (including the tables for DC characteristics, AC characteristics, and ordering information). 07-Feb-2000 2.2 New -V voltage range extended to M95256 (including AC characteristics, and ordering information). 22-Feb-2000 2.3 tCLCH and tCHCL, for the M95xxx-V, changed from 1s to 100ns 15-Mar-2000 2.4 -V voltage range changed to 2.7-3.6V 29-Jan-2001 2.5 Lead Soldering Temperature in the Absolute Maximum Ratings table amended Illustrations and Package Mechanical data updated 12-Jun-2001 2.6 Correction to header of Table 12B TSSOP14 Illustrations and Package Mechanical data updated Document promoted from Preliminary Data to Full Data Sheet 08-Feb-2002 2.7 Announcement made of planned upgrade to 10 MHz clock for the 5V, -40 to 85C, range. 09-Aug-2002 2.8 M95128 split off to its own datasheet. Data added for new and forthcoming products, including availability of the SO8 narrow package. 24-Feb-2003 2.9 Omission of SO8 narrow package mechanical data remedied 26-Jun-2003 2.10 -V voltage range removed 21-Nov-2003 3.0 Table of contents, and Pb-free options added. -S voltage range extended to -R. VIL(min) improved to -0.45V 17-Mar-2004 4.0 Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified 21-Oct-2004 5.0 M95128 datasheet merged back in. Product List summary table added. AEC-Q100-002 compliance. Device Grade information clarified. tHHQX corrected to tHHQV. 10MHz product becomes standard 39/41 Revision history Table 23. Date 13-Apr-2006 27-Jun-2006 40/41 M95128, M95128-W, M95128-R Document revision history (continued) Revision Changes 6 New M95128 datasheet extracted from the M95128/256 datasheet. Order of sections modified. ECC (Error Correction Code) and Write cycling paragraph added. Section 3.7: Supply voltage (VCC) added and information removed below Section 4: Operating features. Power up state removed below Section 6: Delivery state. Figure 13: SPI modes supported modified and Note 2 added. ICC1 specified over the whole VCC range and ICC0 added to Table 13, Table 14 and Table 15. ICC specified over the whole VCC range in Table 13. tCHHL and tCHHH replaced by tCLHL and tCLHH, respectively. Figure 16: Hold timing modified. Process letter and Note 1 added to Table 22: Ordering information scheme. "AC Characteristics (M95128, Device Grade 6)" Table (for 10MHz frequency) removed. Note 1 removed from Table 19: AC characteristics (M95128-R). TA added to Table 6: Absolute maximum ratings. PDIP8 (BN) and SO8 wide (MW) packages removed. M95128-W and M95128-R are no longer under development. Test conditions changed for VOL and VOH in Section Table 14.: DC characteristics (M95128-W, Device Grade 3). 7 Figure 12: Bus master and memory devices on the SPI bus modified. SO8N package specifications updated (see Table 20 and Figure 18). V Process specified and A Process replaced by P in Table 22: Ordering information scheme. M95128, M95128-W, M95128-R Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 41/41 STMicroelectronics | Part Number Search About ST Products Page 1 of 1 Applications Support Buy News & Events ST Worldwide Contact Us Login search the site Part Number Search Search For Part #: M95128-MN3TP/P Example: *74*00* Matching Documents: 1 - 1 of 1 Generic Part Number(s) M95128 Orderable Part Number(s) M95128-MN3TP/P Status Active Product Page/ Datasheet Description 128 Kbit Serial SPI bus EEPROM with high speed clock Memories|EEPROM, Serial|Serial EEPROM, SPI Bus, M95 Search time: 0.075s All rights reserved (c) 2007 STMicroelectronics :: Terms Of Use :: Privacy Policy mhtml:file://C:\TEMP\SGST\M95128-MN3TP%20P.mht 27-Aug-2007