Rev. A – 29-Oct-01
1
Features
•High perf ormance ULC family suitable for larg e-si zed CPLDs and FPGAs
•Conversions to over 2,000,000 FPGA gates
•Pin counts to over 976 pins
•Any pin–out matched due to limited number of dedicated pads
•Full range of packages: LCC/PLCC, PQ FP/TQFP, fine pitch BGA, PGA/PPGA
•2.5V I/O and 3.3V tolerant/com pliant
•Low quiescent current: <0.3 nA/gate
•Avai labl e in commercial and indu strial grade s
•0.25 mm Dra wn CMOS, 5 Met al Layers
•Library Optimised for Synt hesis, Stati c Timing Analysi s & Automati c Test Pattern
Generation (ATPG)
•High Speed Performance :
–100 ps Typical Gate Delay @2.5V
–Typical 280 MHz Flip-Flop Toggle Frequency @2.5V
•High System Frequency Skew Control:
–Clock Tree Synthesis Software
•2.5Volts & 3.3Volts Operation; Single or Dual Supply Modes
•Low Power Consump ti on:
–<0.18 µW/G a te/M H z @ 2 . 5 V
•Power on Reset
•S tandard 2, 4, 6, 8,10, 12 and 18 mA I/O s
•CMOS/ TTL/PCI Int erface, LVCMOS, LVTTL, PECL, PCI (33/66 M Hz) levels, GTL/GTL+,
HSTL, SSTL2, SSTL3, CCT, AGP, LVDS
•ESD (2 kV) and Latch-up Protected I/O
•High Nois e & EMC Immunity:
–I/O with Slew Rate Control
–Internal Decoupling
–Signal Filtering between Periphery & Core
Description
The UA2 series of ULC s is well suited for co nversion of large sized CPLDs and
FPGAs. Devices are i mp lem ented in high–performance CMO S techn ology wi th 0.2 5–
µm (drawn) channel lengths, and are capable of supporting flip–flo p to ggl e r a te s o f
280 MHz at 2.5V, an d input to out put delay cells as fa st as 100ps at 2 .5V. T he arch i-
tecture of the UA2 series allows for efficient conversion of many PLD architecture and
FPGA device types with higher IO count. A com pact RAM cell, along with the large
number of available gates allows the implementation of RAM in FP GA architectures
that support this fea ture, as well as JTAG boundary–scan and scan–path testing.
Conve rsi on to the UA2 s eries of ULC can prov ide a significant red uction in operatin g
power when compared to the original PLD or FPGA. This is especially true when com-
pa red to many PLD and CPLD archi tecture devices , wh ich typically cons ume 100mA
or more even when not being clocked. The UA2 series has a very low standby con-
sumption of less than 0.3 nA/gate typically commercial temp, which would yield a
standby current of 0.3 nA/gat e, 0.42µA on a 144,000 gates design. Operating c on-
sumption is a strict fu nction of clock frequency, which typically results in a po wer
reduction of 50% to 90% depending on the device being com pared.
The UA2 series provides several options for output buffers, including a variety of drive
levels up t o 18mA. Sch mitt trigge r inputs are also a n optio n. A numb er of t echniqu es
are used for improved noise immunity and reduced EMC emissions, including: several
independent power sup ply bu sses and internal decoupling for isolation ; slew rate lim-
ited outputs are also av ailable if required.
0.25 µm ULC
Series
UA2
Preliminary