UA2388-PLCC - Atmel Corporation - Datasheet.Directory

Rev. A – 29-Oct-01

Features

•High perf ormance ULC family suitable for larg e-si zed CPLDs and FPGAs

•Conversions to over 2,000,000 FPGA gates

•Pin counts to over 976 pins

•Any pin–out matched due to limited number of dedicated pads

•Full range of packages: LCC/PLCC, PQ FP/TQFP, fine pitch BGA, PGA/PPGA

•2.5V I/O and 3.3V tolerant/com pliant

•Low quiescent current: <0.3 nA/gate

•Avai labl e in commercial and indu strial grade s

•0.25 mm Dra wn CMOS, 5 Met al Layers

•Library Optimised for Synt hesis, Stati c Timing Analysi s & Automati c Test Pattern

Generation (ATPG)

•High Speed Performance :

–100 ps Typical Gate Delay @2.5V

–Typical 280 MHz Flip-Flop Toggle Frequency @2.5V

•High System Frequency Skew Control:

–Clock Tree Synthesis Software

•2.5Volts & 3.3Volts Operation; Single or Dual Supply Modes

•Low Power Consump ti on:

–<0.18 µW/G a te/M H z @ 2 . 5 V

•Power on Reset

•S tandard 2, 4, 6, 8,10, 12 and 18 mA I/O s

•CMOS/ TTL/PCI Int erface, LVCMOS, LVTTL, PECL, PCI (33/66 M Hz) levels, GTL/GTL+,

HSTL, SSTL2, SSTL3, CCT, AGP, LVDS

•ESD (2 kV) and Latch-up Protected I/O

•High Nois e & EMC Immunity:

–I/O with Slew Rate Control

–Internal Decoupling

–Signal Filtering between Periphery & Core

Description

The UA2 series of ULC s is well suited for co nversion of large sized CPLDs and

FPGAs. Devices are i mp lem ented in high–performance CMO S techn ology wi th 0.2 5–

µm (drawn) channel lengths, and are capable of supporting flip–flo p to ggl e r a te s o f

280 MHz at 2.5V, an d input to out put delay cells as fa st as 100ps at 2 .5V. T he arch i-

tecture of the UA2 series allows for efficient conversion of many PLD architecture and

FPGA device types with higher IO count. A com pact RAM cell, along with the large

number of available gates allows the implementation of RAM in FP GA architectures

that support this fea ture, as well as JTAG boundary–scan and scan–path testing.

Conve rsi on to the UA2 s eries of ULC can prov ide a significant red uction in operatin g

power when compared to the original PLD or FPGA. This is especially true when com-

pa red to many PLD and CPLD archi tecture devices , wh ich typically cons ume 100mA

or more even when not being clocked. The UA2 series has a very low standby con-

sumption of less than 0.3 nA/gate typically commercial temp, which would yield a

standby current of 0.3 nA/gat e, 0.42µA on a 144,000 gates design. Operating c on-

sumption is a strict fu nction of clock frequency, which typically results in a po wer

reduction of 50% to 90% depending on the device being com pared.

The UA2 series provides several options for output buffers, including a variety of drive

levels up t o 18mA. Sch mitt trigge r inputs are also a n optio n. A numb er of t echniqu es

are used for improved noise immunity and reduced EMC emissions, including: several

independent power sup ply bu sses and internal decoupling for isolation ; slew rate lim-

ited outputs are also av ailable if required.

0.25 µm ULC

Series

UA2

Preliminary

UA2

Rev. A – 29-Oct-01

The UA2 series is designed to allow conversion of high performance 2.5V devices. Sup-

port of mixed su pply co nversions (2.5V co re, 3.3V periphe ry) is also poss ible, allo wing

optimal trade–of fs between speed and power c onsum ption.

Array Organi zati on

Architecture

The basic element of the UA2 family is called a cell. One cell can typically implement

between one to four FPGA gates. Cells are located contiguously through out the core of

the device, with rout ing resources provided in three to four metal layers above the c ells.

Some cell blockage does occur due to routing, and utilization will be significantly greater

with th ree met al routing than tw o. The sizes list ed in the P roduct Ou tline are estim ated

us able a mou nts usi ng three met al lay ers. I/O ce lls are prov ided a t each pad, and m ay

be configured as inputs, outputs, I/Os, VDD or VSS as required to match any FPGA or

PLD pinout.

Device Number 4LM Routable Gates 5LM Routable Gates Full Programmable

us a ble pads

UA2044 9,535 10,727 36

UA2/68 30,096 33,858 60

UA2084 50,410 56,712 76

UA2100 75,472 84,906 92

UA2120 106,278 120,449 112

UA2132 131,670 149,226 124

UA2144 159,778 181,081 136

UA2160 200,998 227,797 152

UA2184 270,663 306,751 176

UA2208 329,281 376,321 200

UA2228 401,010 458,298 220

UA2256 512,398 585,598 248

UA2304 733,635 838,440 296

UA2352 925,815 1,068,248 344

UA2388 1,133,594 1,307,994 380

UA2432 1,417,125 1,635,145 424

UA2484 1,651,406 1,926,640 476

UA2540 2,069,052 2,413,894 532

UA2600 2,567,790 2,995,755 592

UA2700 3,520,954 4,107,780 692

UA2800 4,231,979 5,001,430 792

UA2900 5,378,257 6,356,122 892

UA2976 5,765,320 6,918,384 968

3UA2 Rev. A – 29-Oct-01

In order t o imp rove noi s e imm unity wi thin t he dev ice, s eparate VDD and VSS busses are

provided for the internal cells and the I/O cells.

I/O buffer interfacing

I/O Fl ex ib ili ty Al l I/O buf fers may be conf igured as input , outpu t, bi-direc tional , oscilla tor or sup ply. A

level translator could be located close to each buffer.

I/O Option s Inputs

Each input can be programmed as TTL, CMOS, or Schmitt Trigger, wi th or without a pull

up or pull down resistor.

Fast Output Buffer

Fast output buffers are able to source or sink 2 to 18mA at 3.3V according to the chosen

option. 36mA achievable, using 2 pads.

Slew Rate Controlled Output Buffer

In this mode, the p– an d n–outp ut tr ansist ors comm ands a re de layed, so th at they a re

never set “ON” simultaneously, resulting in a low switching current and low noise. These

buffers are dedicated to very high load drive.

2. 5V Compatibility

The UA2 series of ULC’s is fully capable of supporting high–performance operation at

2.5V for core or 3.3V for periphery. The performance specifications of any given ULC

design howev er, must be explicitly specified as 2.5V, 3.3V or both.

Power Supply and Noise Protection

The speed and density of the UA 2 te chnolog y caus e large switching current sp ikes, for

exampl e, when:

•16 high current output buffers swi tch simultaneously, or

•10% of the 700 000 gates are switching within a window of 1ns.

Sharp edges and high currents cause some pa rasitic elements in the packaging to

become significant. In this frequency range, the package inductance and series resis-

tance shoul d be taken into acc ount. It is k nown that an inductor slows down the setting

time of the current and causes voltage drops on the power supply lines. These drops

can affect the behavior of the circuit itself or disturb the external application (ground

bounce).

In order to improve the noise immunity of the UA2 core matrix, several mechanisms

have been implemented inside the UA2 arrays. Two types of protection have been

added: one t o limit the I/O buf fer switchin g noise and the o ther to protec t the I/O buffers

against the switching noise coming from the matrix.

I/O buffers switching prote ction Three fea tures are implement ed to limit t he noise gene rated by the switching current:

•The power supplies of the input and output buffers are separated.

•The rise and fall times of the output buffe rs can be controlled by an internal

regulator.

•A design rule concerning the number of buffers connected on the same power

supply line has been imposed.

UA2

Rev. A – 29-Oct-01

Matrix switching curren t

protection This no ise disturba nce is caused by a l arge numbe r o f gates switchi ng simultan eously.

To allo w this without impacting the functionality of the circuit, three new fea tures have

been added:

•Decoupling capacitors are integrated directly on the si licon to reduce the power

supply drop.

•A power supply network has been implemented in the matrix. This solution reduces

the number of parasitic elements such as inductance and resistance and constitutes

an artificial VDD and Ground plane. One mesh of the network supplies

approximately 150 cells.

•A low pass filter has been added betwe en the matrix and the input to the output

buffer. This limits the tran smission of the noise com ing from the ground or the VDD

supply of the matrix to the external world via the output buffers.

5UA2 Rev. A – 29-Oct-01

Electrical Characteristics

Ab solu te Maximum Rati ngs

Max Supply Voltage (VDD)....................................................2.7V

Max Supply Voltage (VDD5)...................................................3.6V

Input Voltag e (VIN)VDD VDD...................................................+ 0.5V

3.3V Tole rant/Com plia ntVDD5 ..............................................+ 0.5V

Storage Tem perature .......... .................. ................... ...........-65° to 150°C

Operating Ambient Temperature..........................................-40° to 85°C

Recommended Operating Range

VDD .. ..................... .......... .......................... ......... .......... ..2.5V ± 5% or 3.3V ± 5%

Operat ing Temperature:

Commercial..........................................................................0° to 70°C

Industrial...............................................................................-40° to 85°C

UA2

Rev. A – 29-Oct-01

DC Characteristics

2.5V Specified at VDD = +2.5V +/- 5%

Symbol Parameter Buffer Min. Typ Max Unit Conditions

TA Opera ting Temperature All -40 +85 °C

VDD Su pply Voltage All 2.3 2 .5 2.7 V

IIH High level input current CM OS 10 µA VIN=VDD,VDD=VDD(max)

PCI 10

IIL Low Level input current CMOS -10 µA VIN=VSS,VDD=VDD (max)

PCI

IOZ High-Impedance State

Output Current All -10 10 µA VIN = VDD or VSS,

VDD = VDD (max), No Pull-up

IOS Output short-circuit curre nt P O 11 9 mA VOUT = VDD, VDD = VDD (max)

VOUT = VSS, VDD= VDD (max)

PO11 6

VIH High-level Input Voltage

CMOS 0.7VDD V

PCI 0.475VDD

CMOS Schmitt 0.7VDD 1.5

VIL Low-Level Input Voltage

CMOS 0.3VDD V

PCI 0.325VDD

CMOS Schmitt 1.0 0.3VDD

Vhys Hysteresis CMOS Schmitt 0.5 V

VOH Hi gh - Le v el ou t p ut vo lt a ge PO11 0.7VDD VIOH = 1.4m A, VDD = VDD (min )

IOH = -500 µA

PCI 0.9VDD

VOL Low-Le vel output voltage PO11 0.4 V IOL = 1.4 mA, VDD = VDD (min)

IOL = 1.5 m A

PCI 0.1VDD

7UA2 Rev. A – 29-Oct-01

3.3V Specified at VDD = +3.3V +/- 5%

I/O Buffer

Symbol Parameter Buffer Min Typ Max Unit Conditions

TA Opera ting Temperature All -40 +85 °C

VDD Su pply Voltage All 3.0 3 .3 3.6 V

IIH Hi gh lev el in put cur r ent CMO S 1 0 µA VIN=VDD,VDD=VDD(max)

PCI 10

IIL Low Level input current CMOS -10 µA VIN=VSS,VDD=VDD (ma x)

PCI

IOZ High-Impedance State

Output Current All -10 10 µA VIN = VDD or VSS,

VDD = VDD (max), No Pull-up

IOS O u tp u t s ho r t - c i r c u i t c u r r e n t P O 11 14 mA VOUT = VDD, VDD = VDD (max)

VOUT = VSS, VDD= VDD (max)

PO11 -9

VIH High-level Input Voltage CMOS,LVTTL 2.0 V

PCI 0.475VDD

CMOS Schmitt 2.0 1.7

VIL Low-Level In put Volt age C MO S 0.8 V

PCI 0.325VDD

CMOS/TTL-l evel

Schmitt 1.1 0.8

Vhys Hys ter e s is TTL -le vel Sc hm itt 0. 6 V

VOH Hi gh - Le v el ou t p ut vo lt a ge PO11 0. 7V DD V

IOH = 2mA , VDD = VDD (min)

IOH = -500 µA

PCI 0.9VDD

VOL Low-Le vel output voltage PO11 0.4 V

IOL = 2 mA, VDD = VDD (min)

IOL = 1.5 m A

PCI 0.1VDD

Symbol Parameter Typ Unit Conditions

C IN Capacitance, Input Buffer (Die) 2.4 pF 3.3V

C OUT Ca pac itanc e, O utp ut Bu ffer (D ie ) 5 .6 pF 3.3 V

C I/O Capacitance, Bidirectional 6.6 pF 3.3V

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