See mechanical drawings for dimensions.
NC No internal connection
DBV PACKAGE
(TOP VIEW)
2
5
34Y
1
B
GND
AVCC
DCK PACKAGE
(TOP VIEW)
34
GND
2
B
Y
1
A5VCC
DRL PACKAGE
(TOP VIEW)
2
B
1
A
34
GND Y
5VCC
YZP PACKAGE
(BOTTOM VIEW)
2
B
1
A
GND 4
3Y
5VCC
DRY PACKAGE
(TOP VIEW)
B NC
A6
5
4
2
3
GND Y
VCC
16
5
4
2
3
1
DSF PACKAGE
(TOP VIEW)
B
A
GND
NC
Y
VCC
A
GND
DPK PACKAGE
(TOP VIEW)
B
VCC
Y
5
4
2
3
1
Y = A + B or Y = A B
SN74LVC1G32
www.ti.com
SCES219S APRIL 1999REVISED JULY 2013
SINGLE 2-INPUT POSITIVE-OR GATE
Check for Samples: SN74LVC1G32
1FEATURES DESCRIPTION
This single 2-input positive-OR gate is designed for
2 Available in the Texas Instruments NanoStar™ 1.65-V to 5.5-V VCC operation.
and NanoFree™ Packages The SN74LVC1G32 performs the Boolean function
Supports 5-V VCC Operation in positive logic.
Inputs Accept Voltages to 5.5 V NanoStar™ and NanoFree™ package technology is
Max tpd of 3.6 ns at 3.3 V a major breakthrough in IC packaging concepts,
Low Power Consumption, 10-μA Max IC C using the die as the package.
±24-mA Output Drive at 3.3 V This device is fully specified for partial-power-down
Ioff Supports Partial-Power-Down Mode applications using Ioff. The Ioff circuitry disables the
Operation outputs, preventing damaging current backflow
Latch-Up Performance Exceeds 100 mA Per through the device when it is powered down.
JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1G32
SCES219S APRIL 1999REVISED JULY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTION TABLE
INPUTS OUTPUT
Y
A B
H X H
X H H
L L L
LOGIC DIAGRAM (POSITIVE LOGIC)
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VIInput voltage range(2) –0.5 6.5 V
VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VOVoltage range applied to any output in the high or low state(2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous ouput current ±50 mA
Continuous current through VCC or GND ±100 mA
DBV package 206
DCK package 252
θJA Package thermal impedance(4) DRL package 142 °C/W
DRY package 234
YZP package 132
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32
SN74LVC1G32
www.ti.com
SCES219S APRIL 1999REVISED JULY 2013
Recommended Operating Conditions(1)
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V –24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V 24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TAOperating free-air temperature –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: SN74LVC1G32
SN74LVC1G32
SCES219S APRIL 1999REVISED JULY 2013
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) –40°C to 125°C
–40°C to 85°C
PARAMETER TEST CONDITIONS VCC Recommended UNIT
MIN TYP(1) MAX MIN TYP MAX
IOH = –100 μA 1.65 V to 5.5 V VCC 0.1 VCC 0.1
IOH = –4 mA 1.65 V 1.2 1.2
IOH = –8 mA 2.3 V 1.9 1.9
VOH V
IOH = –16 mA 2.4 2.4
3 V
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
IOL = 100 μA 1.65 V to 5.5 V 0.1 0.1
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.4
VOL V
IOL = 16 mA 0.4 0.5
3 V
IOL = 24 mA 0.55 0.65
IOL = 32 mA 4.5 V 0.55 0.65
A or B
IIVI= 5.5 V or GND 0 to 5.5 V ±5 ±5 μA
inputs
Ioff VIor VO= 5.5 V 0 ±10 ±25 μA
ICC VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 10 μA
One input at Other inputs at VCC or
ΔICC 3 V to 5.5 V 500 500 μA
VCC 0.6 V, GND
CiVI= VCC or GND 3.3 V 4 4 pF
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
Switching Characteristics
over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 1)
SN74LVC1G32
–40°C to 85°C
FROM TO
PARAMETER UNIT
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y 1.9 7.2 0.8 4.4 0.9 3.6 0.8 3.4 ns
Switching Characteristics(1)
over recommended operating free-air temperature range, CL= 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
–40°C to 125°C –40°C to 125°C
–40°C to 85°C –40°C to 85°C
Recommended Recommended
FROM TO
PARAMETER UNIT
VCC = 1.8 V VCC = 1.8 V VCC = 2.5 V VCC = 2.5 V
(INPUT) (OUTPUT) ± 0.15 V ± 0.15 V ± 0.2 V ± 0.2 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y 2.8 8 2.8 9 1.2 5.5 1.2 6 ns
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested
4Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32
SN74LVC1G32
www.ti.com
SCES219S APRIL 1999REVISED JULY 2013
Switching Characteristics(1)
over recommended operating free-air temperature range, CL= 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
–40°C to 125°C –40°C to 125°C
–40°C to 85°C –40°C to 85°C
Recommended Recommended
FROM TO
PARAMETER UNIT
VCC = 3.3 V VCC = 3.3 V VCC = 5 V VCC = 5 V
(INPUT) (OUTPUT) ± 0.3 V ± 0.3 V ± 0.5 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y 1.1 4.5 1 4 1 4 1 4.5 ns
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested
Operating Characteristics
TA= 25°C VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
TEST
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 20 20 21 22 pF
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: SN74LVC1G32
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
t /t
PLH PHL Open
TEST S1
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1MW
1MW
1MW
1MW
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
15pF
15pF
15pF
15pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
SN74LVC1G32
SCES219S APRIL 1999REVISED JULY 2013
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 1. Load Circuit and Voltage Waveforms
6Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1kW
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
30pF
30pF
50pF
50pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
SN74LVC1G32
www.ti.com
SCES219S APRIL 1999REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 2. Load Circuit and Voltage Waveforms
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: SN74LVC1G32
SN74LVC1G32
SCES219S APRIL 1999REVISED JULY 2013
www.ti.com
REVISION HISTORY
Changes from Revision R (June 2013) to Revision S Page
Added parameter values for –40 to 125°C temperature ratings. .......................................................................................... 4
8Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC1G32DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C322 ~ C325 ~
C32F ~ C32K ~
C32R)
SN74LVC1G32DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C322 ~ C325 ~
C32F ~ C32K ~
C32R)
SN74LVC1G32DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C322 ~ C325 ~
C32F ~ C32K ~
C32R)
SN74LVC1G32DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C325 ~ C32F ~
C32K ~ C32R)
SN74LVC1G32DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C325 ~ C32F ~
C32K ~ C32R)
SN74LVC1G32DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C325 ~ C32F ~
C32K ~ C32R)
SN74LVC1G32DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CG5 ~ CGF ~ CGK ~
CGR)
SN74LVC1G32DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CG5 ~ CGF ~ CGK ~
CGR)
SN74LVC1G32DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CG5 ~ CGF ~ CGK ~
CGR)
SN74LVC1G32DCKT ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CG5 ~ CGF ~ CGK ~
CGR)
SN74LVC1G32DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CG5 ~ CGF ~ CGK ~
CGR)
SN74LVC1G32DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CG5 ~ CGF ~ CGK ~
CGR)
SN74LVC1G32DRLR ACTIVE SOT DRL 5 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CG7 ~ CGR)
SN74LVC1G32DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CG7 ~ CGR)
SN74LVC1G32DRY2 ACTIVE SON DRY 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CG
SN74LVC1G32DRYR ACTIVE SON DRY 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CG
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC1G32DRYRG4 ACTIVE SON DRY 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CG
SN74LVC1G32DSF2 ACTIVE SON DSF 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CG
SN74LVC1G32DSFR ACTIVE SON DSF 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CG
SN74LVC1G32YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 (CG ~ CG2 ~ CG7)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2013
Addendum-Page 3
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G32 :
Automotive: SN74LVC1G32-Q1
Enhanced Product: SN74LVC1G32-EP
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G32DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3
SN74LVC1G32DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G32DBVR SOT-23 DBV 5 3000 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3
SN74LVC1G32DBVT SOT-23 DBV 5 250 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3
SN74LVC1G32DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G32DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3
SN74LVC1G32DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G32DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G32DCKR SC70 DCK 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC1G32DCKT SC70 DCK 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC1G32DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G32DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G32DRLR SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1G32DRLR SOT DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
SN74LVC1G32DRY2 SON DRY 6 5000 180.0 9.5 1.6 1.15 0.75 4.0 8.0 Q3
SN74LVC1G32DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC1G32DSF2 SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3
SN74LVC1G32DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Oct-2013
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G32YZPR DSBGA YZP 5 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G32DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G32DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74LVC1G32DBVR SOT-23 DBV 5 3000 205.0 200.0 33.0
SN74LVC1G32DBVT SOT-23 DBV 5 250 205.0 200.0 33.0
SN74LVC1G32DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G32DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G32DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G32DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G32DCKR SC70 DCK 5 3000 205.0 200.0 33.0
SN74LVC1G32DCKT SC70 DCK 5 250 205.0 200.0 33.0
SN74LVC1G32DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G32DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G32DRLR SOT DRL 5 4000 202.0 201.0 28.0
SN74LVC1G32DRLR SOT DRL 5 4000 180.0 180.0 30.0
SN74LVC1G32DRY2 SON DRY 6 5000 180.0 180.0 30.0
SN74LVC1G32DRYR SON DRY 6 5000 180.0 180.0 30.0
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Oct-2013
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G32DSF2 SON DSF 6 5000 180.0 180.0 30.0
SN74LVC1G32DSFR SON DSF 6 5000 180.0 180.0 30.0
SN74LVC1G32YZPR DSBGA YZP 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Oct-2013
Pack Materials-Page 3