IS62WV51216EFALL/BLL
IS65WV51216EFALL/BLL
Integrated Silicon Solution, Inc.- www.issi.com 1
Rev. A3
11/26/2018
512Kx16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM with ECC
KEY FEATURES
High-speed access time: 45ns, 55ns
CMOS low power operation
– Operating Current: 35mA (max.)
– CMOS standby Current: 5.5uA (typ.)
TTL compatible interface levels
Single power supply
–1.65V-2.2V VDD (IS62/65WV51216EFALL)
– 2.2V-3.6V VDD (IS62/65WV51216EFBLL)
Optional ERR1/ERR2 pin:
ERR1: indicates 1-bit error detection and
correction.
ERR2: indicates 2-bit error detection
Three state outputs
Commercial, Industrial and Automotive
temperature support
Lead-free available
FUNCTIONAL BLOCK DIAGRAM
COLUMN I/O
CS2
WE#
UB#
OE#
LB#
CONTROL
CIRCUIT
I/O
DATA
CIRCUIT
DECODER
VDD
VSS
A0 – A18
I/O0 – I/O7
I/O8 – I/O15
Memory
Upper IO
Array
512Kx8
ECC
Array
512Kx4
Column I/O
8 5 8 5
ECC
Array
512Kx4
ECC
ECC
8
8
13
13
Memory
Lower IO
Array
512Kx8
ERR1
ERR2
CS1#
DESCRIPTION
The ISSI IS62/65WV51216EFALL/BLL are high-speed, low
power, 8M bit static RAMs organized as 512K words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology and implemented ECC function to improve
reliability.
This highly reliable process coupled with innovative circuit
design techniques including ECC (SEC-DEC: Single Error
Correcting-Double Error Detecting),yields high-performance
and low power consumption devices. When CS1# is HIGH
(deselected) or when CS2 is LOW (deselected), or when
CS1# is LOW, CS2 is HIGH and both LB# and UB# are
HIGH, the device assumes a standby mode at which the
power dissipation can be reduced down with CMOS input
levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE#) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB#) and Lower Byte (LB#)
access.
The IS62/65WV51216EFALL/BLL are packaged in the
JEDEC standard 48-pin mini BGA (6mm x 8mm), and 44-pin
TSOP (TYPE II)
Copyright © 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
NOVEMBER 2018
IS62WV51216EFALL/BLL
IS65WV51216EFALL/BLL
Integrated Silicon Solution, Inc.- www.issi.com 2
Rev. A3
11/26/2018
PIN CONFIGURATIONS
48-Pin mini BGA(6mm x 8mm), 2CS, No ERR
LB# A0OE# A1 A2 CS2
I/O8 A3UB# A4 CS1# I/O0
I/O9 A5I/O10 A6 I/O1 I/O2
VSS A17I/O11 A7 I/O3 VDD
VDD NCI/O12 A16 I/O4 GND
I/O14 A14I/O13 A15 I/O5 I/O6
I/O15 A12NC A13 WE# I/O7
A18 A9A8 A10 A11 NC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
48-Pin mini BGA (6mm x 8mm),2CS, ERR1, ERR2
LB# A0OE# A1 A2 CS2
I/O8 A3UB# A4 CS1# I/O0
I/O9 A5I/O10 A6 I/O1 I/O2
VSS A17I/O11 A7 I/O3 VDD
VDD ERR1I/O12 A16 I/O4 VSS
I/O14 A14I/O13 A15 I/O5 I/O6
I/O15 A12ERR2 A13 WE# I/O7
A18 A9A8 A10 A11 NC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
PIN DESCRIPTIONS
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control
(I/O0-I/O7)
Upper-byte Control
(I/O8-I/O15)
Single ERR Correction Signal
Double ERR Detection Signal
No Connection
Power
Ground
IS62WV51216EFALL/BLL
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Rev. A3
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48-Pin mini BGA (6mm x 8mm),1CS, ERR
LB# A0OE# A1 A2 ERR
I/O8 A3UB# A4 CS1# I/O0
I/O9 A5I/O10 A6 I/O1 I/O2
VSS A17I/O11 A7 I/O3 VDD
VDD NCI/O12 A16 I/O4 GND
I/O14 A14I/O13 A15 I/O5 I/O6
I/O15 A12NC A13 WE# I/O7
A18 A9A8 A10 A11 NC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
44-Pin TSOP-II , 1CS, No ERR
A4
A3
A2
A1
A0
CS#
I/O0
I/O1
I/O2
I/O3
VDD
VSS
I/O4
I/O5
I/O6
I/O7
WE#
A16
A15
A14
A13
A12
A5
A6
A7
OE#
UB#
LB#
I/O15
I/O14
I/O13
I/O12
VDD
VSS
I/O11
I/O10
I/O9
I/O8
A18
A8
A9
A10
A11
A17
1
2
3
4
5
6
7
8
9
10
12
11
13
14
15
16
32
31
30
29
28
27
26
25
24
23
21
22
20
19
18
17
42
41
40
39
38
37
36
35
34
33
44
43
IS62WV51216EFALL/BLL
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Rev. A3
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FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM
has three different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS1# HIGH or CS2 LOW or both UB# and LB# are HIGH). The input
and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be ISB1 or
ISB2. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input
and output pins (I/O0-15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB#
and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the
location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written
into the location.
READ MODE
Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When
OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB#
and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB#
being LOW, data from memory appears on I/O8-15.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
ERROR DETECTION AND ERROR CORRECTION
Independent ECC per each byte
- detect and correct one bit error per byte or detect 2-bit error per byte
Optional ERR1 output signal indicates 1-bit error detection and correction
Optional ERR2 output signal indicates 2-bit error detection.
Controller can use either ERR1 or ERR2 to monitor ECC event. Unused pins (ERR1 or ERR2) can be left
floating.
Better reliability than parity code schemes which can only detect an error but not correct an error
Backward Compatible: Drop in replacement to current in industry standard devices (without ECC)
ERR1, ERR2 OUTPUT SIGNAL BEHAVIOR
ERR1
ERR2
DQ pin
Status
Remark
0
0
Valid Q
No Error
1
0
Valid Q
1-Bit Error only
1-bit error per byte detected and corrected
0
1
In-Valid Q
2-Bit Error only
No 1-bit error. 2-bit error per byte detected
(out of 4 bytes)
1
1
In-Valid Q
1-Bit & 2-Bit Error
1-bit error detected and corrected, but 2-bit error detected at another byte.
High-Z
High-Z
Valid D
Non-Read
Write operation or Output Disabled
IS62WV51216EFALL/BLL
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Rev. A3
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TRUTH TABLE
Mode
CS1#
CS2
WE#
OE#
LB#
UB#
I/O0-I/O7
I/O8-I/O15
VDD Current
Not Selected
H
X
X
X
X
X
High-Z
High-Z
ISB2
X
L
X
X
X
X
High-Z
High-Z
X
X
X
X
H
H
High-Z
High-Z
Output Disabled
L
H
H
H
L
X
High-Z
High-Z
ICC,ICC1
L
H
H
H
X
L
High-Z
High-Z
Read
L
H
H
L
L
H
DOUT
High-Z
ICC,ICC1
L
H
H
L
H
L
High-Z
DOUT
L
H
H
L
L
L
DOUT
DOUT
Write
L
H
L
X
L
H
DIN
High-Z
ICC,ICC1
L
H
L
X
H
L
High-Z
DIN
L
H
L
X
L
L
DIN
DIN
IS62WV51216EFALL/BLL
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Rev. A3
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ABSOLUTE MAXIMUM RATINGS
AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
Vterm
Terminal Voltage with Respect to GND
–0.5 to 3.9 (VDD + 0.3V)
V
VDD
VDD Related to GND
–0.3 to 3.9 (VDD + 0.3V)
V
tStg
Storage Temperature
–65 to +150
C
IOUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE(1)
Range
Ambient Temperature
PART
NUMBER
SPEED (MAX)
VDD(MIN)
VDD(TYP)
VDD(MAX)
Commercial
0C to +70C
~ALL
55 ns
1.65V
1.8V
2.2V
Industrial
-40C to +85C
55 ns
1.65V
1.8V
2.2V
Automotive
-40C to +125C
55 ns
1.65V
1.8V
2.2V
Commercial
0C to +70C
~BLL
45ns
2.2V
3.0V
3.6V
Industrial
-40C to +85C
45ns
2.2V
3.0V
3.6V
Automotive
-40C to +125C
55ns
2.2V
3.0V
3.6V
Note:
1. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE (1)
Parameter
Symbol
Test Condition
Max
Units
Input capacitance
CIN
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
6
pF
DQ capacitance (IO0–IO15)
CI/O
8
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS (1)
Parameter
Symbol
Test Conditions
48-ball BGA
44-pin TSOP II
Units
Thermal resistance (junction to ambient)
RθJA
Still air, four-layer
printed circuit board
48.4
47.7
°C/W
Thermal resistance (junction to pins)
RθJB
23.3
30.1
°C/W
Thermal resistance (junction to case)
RθJC
10.8
9.1
°C/W
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
IS62WV51216EFALL/BLL
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Rev. A3
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AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Unit
(1.65V~2.2V)
Unit
(2.2V~3.6V)
Input Pulse Level
0V to VDD
0V to VDD
Input Rise and Fall Time
1V/ns
1V/ns
Output Timing Reference Level
0.9V
½ VDD
R1
13500
1005
R2
10800
820
VTM
1.8V
VDD
Output Load Conditions
Refer to Figure 1 and 2
OUTPUT LOAD CONDITIONS FIGURES
R1
R2
VTM
OUTPUT 30pF,
Including
jig
and scope
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
FIGURE 1 FIGURE 2
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Rev. A3
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DC ELECTRICAL CHARACTERISTICS
IS62(5)WV51216EFALL
DC ELECTRICAL CHARACTERISTICS-I
(OVER THE OPERATING RANGE)
VDD = 1.65V ~ 2.2V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.4
—
V
VOL
Output LOW Voltage
IOL = 0.1 mA
—
0.2
V
VIH
(1)
Input HIGH Voltage
1.4
VDD + 0.2
V
VIL
(1)
Input LOW Voltage
–0.2
0.4
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV51216EFBLL
DC ELECTRICAL CHARACTERISTICS-I
(OVER THE OPERATING RANGE)
VDD = 2.2V ~ 3.6V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
2.2 ≤ VDD < 2.7, IOH = -0.1 mA
2.0
—
V
2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA
2.4
—
V
VOL
Output LOW Voltage
2.2 ≤ VDD < 2.7, IOL = 0.1 mA
—
0.4
V
2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA
—
0.4
V
VIH
(1)
Input HIGH Voltage
2.2 ≤ VDD < 2.7
1.8
VDD + 0.3
V
2.7 ≤ VDD ≤ 3.6
2.0
VDD + 0.3
V
VIL
(1)
Input LOW Voltage
2.2 ≤ VDD < 2.7
–0.3
0.6
V
2.7 ≤ VDD ≤ 3.6
–0.3
0.8
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
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Rev. A3
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IS62(5)WV51216EFALL
DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
Typ(1)
Max
Unit
ICC
VDD Dynamic
Operating Supply
Current
VDD = VDD(max), IOUT = 0mA,
f = fmax,
Com.
-
35
mA
Ind.
-
35
Auto. A3
-
35
ICC1
VDD Static
Operating Supply
Current
VDD = VDD(max), IOUT = 0mA,
f = 0
Com.
-
5
mA
Ind.
-
5
Auto. A3
-
5
ISB2
CMOS Standby
Current (CMOS
Inputs)
VDD = VDD(max), f = 0,
CS1# ≥ VDD - 0.2V or
CS2 < 0.2V or
(LB# and UB#) ≥ VDD - 0.2V,
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Com.
25°C
5.5
8(2)
µA
40°C
6.0
10(2)
70°C
7.5
14
Ind.
85°C
10.5
16
Auto. A3
125°C
25
40
Notes:
1. Typical value indicates the value for the center of distribution at VDD=VDD (Typ.), and not 100% tested.
2. Maximum value at 25°C, 40°C are guaranteed by design, and not 100% tested
IS62(5)WV51216EFBLL
DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
Typ(1)
Max
Unit
ICC
VDD Dynamic
Operating Supply
Current
VDD = VDD(max), IOUT = 0mA,
f = fmax,
Com.
-
35
mA
Ind.
-
35
Auto. A3
-
35
ICC1
VDD Static
Operating Supply
Current
VDD = VDD(max), IOUT = 0mA,
f = 0
Com.
-
5
mA
Ind.
-
5
Auto. A3
-
5
ISB2
CMOS Standby
Current (CMOS
Inputs)
VDD = VDD(max), f = 0,
CS1# ≥ VDD - 0.2V or
CS2 < 0.2V or
(LB# and UB#) ≥ VDD - 0.2V,
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Com.
25°C
5.5
8(2)
µA
40°C
6.0
10(2)
70°C
7.5
14
Ind.
85°C
10.5
16
Auto. A3
125°C
25
40
Notes:
1. Typical value indicates the value for the center of distribution at VDD=VDD (Typ.), and not 100% tested.
2. Maximum value at 25°C, 40°C are guaranteed by design, and not 100% tested
IS62WV51216EFALL/BLL
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Rev. A3
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AC CHARACTERISTICS
(6)
(OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
45ns
55ns
unit
notes
Min
Max
Min
Max
Read Cycle Time
tRC
45
-
55
-
ns
1,5
Address, ERR Access Time
tAA
-
45
-
55
ns
1
Output, ERR Hold Time
tOHA
10
-
10
-
ns
1
CS1#, CS2 Access Time
tACS1/ACS2
-
45
-
55
ns
1
UB#, LB# Access Time
tBA
-
45
-
55
ns
1
OE# Access Time
tDOE
-
20
-
25
ns
1
OE# to High-Z Output
tHZOE
-
15
-
20
ns
2
OE# to Low-Z Output
tLZOE
5
-
5
-
ns
2
CS1#, CS2 to High-Z Output
tHZCS
-
15
-
20
ns
2
CS1#, CS2 to Low-Z Output
tLZCS
10
-
10
-
ns
2
UB#, LB# to High-Z Output
tHZB
-
15
-
20
ns
2
UB#, LB# to Low-Z Output
tLZB
10
-
10
-
ns
2
WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
45ns
55ns
unit
notes
Min
Max
Min
Min
Write Cycle Time
tWC
45
-
55
-
ns
1,3,5
CS1#, CS2 to Write End
tSCS1/SCS2
35
-
40
-
ns
1,3
Address Setup Time to Write End
tAW
35
-
40
-
ns
1,3
UB#,LB# to Write End
tPWB
35
-
40
-
ns
1,3
Address Hold from Write End
tHA
0
-
0
-
ns
1,3
Address Setup Time
tSA
0
-
0
-
ns
1,3
WE# Pulse Width
tPWE
35
-
40
-
ns
1,3,4
Data Setup to Write End
tSD
20
-
25
-
ns
1,3
Data Hold from Write End
tHD
0
-
0
-
ns
1,3
WE# LOW to High-Z Output
tHZWE
-
15
-
20
ns
2,3
WE# HIGH to Low-Z Output
tLZWE
5
-
5
-
ns
2,3
Notes:
1 Tested with the load in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are
measured when the output enters a high impedance state. Not 100% tested.
3. The internal write time is defined by the overlap of CS1# = LOW, CS2=HIGH, UB# or LB# = LOW, and WE# = LOW. All four conditions must be
in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
4. tPWE > tHZWE + tSD when OE# is LOW.
5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby
mode is acceptable.
6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS.
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Timing Diagram
READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED, CS1# = OE# = UB# = LB# = LOW, CS2 = WE# = HIGH)
tRC
Address
DQ 0-15
tOHA tOHA
tAA
PREVIOUS DATA VALID DATA VALID
PREVIOUS ERROR VALID ERROR1 VALID
ERR1
LOW-Z
LOW-Z
PREVIOUS ERROR VALID ERROR2 VALID
ERR2 LOW-Z
Notes:
1. The device is continuously selected.
2. ERR1, ERR2 signasls act like a Read Data Q during Read Operation.
READ CYCLE NO. 2(1) (OE# CONTROLLED, WE# = HIGH)
OE#
CS1#
DOUT
tAA
ADDRESS
tRC
tOHA
tDOE
tLZOE
tACS1/tACS2
tLZCS1/
tLZCS2
tHZOE
tHZCS1/
tHZCS2
HIGH-Z DATA VALID
tLZB tHZB
tBA
UB#,LB#
CS2
LOW-Z
Notes:
1. Address is valid prior to or coincident with CS1# LOW or CS2 HIGH transition.
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WRITE CYCLE NO. 1(1,2) (CS1# , CS2 CONTROLLED, OE# = HIGH OR LOW)
ADDRESS
CS1#
CS2
WE#
UB#, LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS1
(1)
(2)
tSCS2
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before
Write Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 2(1,2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
ADDRESS
CS1#
CS2
WE#
UB#, LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZOE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS1
(1)
(2)
tSCS2
OE#
Notes:
1. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
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WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE)
ADDRESS
CS1#
CS2
WE#
UB#, LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS1
(1)
(2)
tSCS2
Notes:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
IS62WV51216EFALL/BLL
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Rev. A3
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WRITE CYCLE NO. 4(1,2,3) (UB# & LB# Controlled, OE# = LOW)
ADDRESS
CS2=HIGH
WE#
DOUT
DIN
tSA
tHZWE
tPWB
tHA
DATA IN
VALID
ADDRESS 1 ADDRESS 2
tWC
DATA IN
VALID
DATA UNDEFINED tHD
tSD
HIGH-Z tLZWE
WORD 1 WORD 2
UB#, LB#
tHA
OE#=LOW
CS1#=LOW
tSA
tPWB
tWC
Notes:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
2. Due to the restriction of note1, OE# is recommended to be HIGH during write period.
3. WE# stays LOW in this example. If WE# toggles, tPWE and tHZWE must be considered.
IS62WV51216EFALL/BLL
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Rev. A3
11/26/2018
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
VDR
VDD for Data Retention
See Data Retention Waveform
1.5
-
-
V
IDR
Data Retention Current
VDD = VDR (min),
CS1# ≥ VDD – 0.2V or CS2 ≤ 0.2V or
(LB# and UB#) ≥ VDD - 0.2V,
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
25°C
-
5.5
13
uA
85°C
-
-
15
125°C
-
-
38
tSDR (2)
Data Retention Setup
Time
See Data Retention Waveform
0
-
-
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
-
-
ns
Notes:
1. Typical value indicates the value for the center of distribution at VDD = VDR (min.), and not 100% tested.
2. VDD power down slope must be longer than 100 us/volt when enter into Data Retention Mode.
DATA RETENTION WAVEFORM (CS1# CONTROLLED)
GND CS1#
VDR
VDD
CS1# > VDD – 0.2V
Data Retention Mode
tSDR tRDR
DATA RETENTION WAVEFORM (CS2 CONTROLLED)
VSS
VDR
VDD
CS2 < 0.2V
Data Retention Mode
tSDR tRDR
CS2
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Rev. A3
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DATA RETENTION WAVEFORM (UB# AND LB# CONTROLLED)
GND
UB#/LB#
VDR
VDD
UB# and LB# > VDD – 0.2V
Data Retention Mode
tSDR tRDR
IS62WV51216EFALL/BLL
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Rev. A3
11/26/2018
ORDERING INFORMATION
IS62/65WV51216EFALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
55
IS62WV51216EFALL-55TLI
TSOP (Type II), Lead-free
55
IS62WV51216EFALL-55BI
mini BGA (6mm x 8mm)
55
IS62WV51216EFALL-55BLI
mini BGA (6mm x 8mm), Lead-free
55
IS62WV51216EFALL-55B2I
mini BGA (6mm x 8mm), ERR1/2 Pins
55
IS62WV51216EFALL-55B2LI
mini BGA (6mm x 8mm), ERR1/2 Pins, Lead-free
55
IS62WV51216EFALL-55B3I
mini BGA (6mm x 8mm), 1 CS Option, ERR Pin
55
IS62WV51216EFALL-55B3LI
mini BGA (6mm x 8mm), 1 CS Option, ERR Pin Lead-free
AUTOMOTIVE RANGE (A3): –40°C TO +125°C
Speed (ns)
Order Part No.
Package
55
IS65WV51216EFALL-55CTLA3
TSOP (Type II), Copper Lead-frame, Lead-free
55
IS65WV51216EFALL-55BA3
mini BGA (6mm x 8mm)
55
IS65WV51216EFALL-55BLA3
mini BGA (6mm x 8mm), Lead-free
55
IS65WV51216EFALL-55B2A3
mini BGA (6mm x 8mm), ERR1/2 Pins
55
IS65WV51216EFALL-55B2LA3
mini BGA (6mm x 8mm), ERR1/2 Pins, Lead-free
55
IS65WV51216EFALL-55B3A3
mini BGA (6mm x 8mm), 1 CS Option, ERR Pin
55
IS65WV51216EFALL-55B3LA3
mini BGA (6mm x 8mm), 1 CS Option, ERR Pin, Lead-free
IS62WV51216EFALL/BLL
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Integrated Silicon Solution, Inc.- www.issi.com 18
Rev. A3
11/26/2018
IS62/65WV51216EBLL (2.2V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
45
IS62WV51216EFBLL-45TLI
TSOP (Type II), Lead-free
45
IS62WV51216EFBLL-45BI
mini BGA (6mm x 8mm)
45
IS62WV51216EFBLL-45BLI
mini BGA (6mm x 8mm), Lead-free
45
IS62WV51216EFBLL-45B2I
mini BGA (6mm x 8mm), ERR1/2 Pins
45
IS62WV51216EFBLL-45B2LI
mini BGA (6mm x 8mm), ERR1/2 Pins, Lead-free
45
IS62WV51216EFBLL-45B3I
mini BGA (6mm x 8mm), 1 CS Option, ERR Pin
45
IS62WV51216EFBLL-45B3LI
mini BGA (6mm x 8mm), 1 CS Option, ERR Pin, Lead-free
55
IS62WV51216EFBLL-55TLI
TSOP (Type II), Lead-free
55
IS62WV51216EFBLL-55BI
mini BGA (6mm x 8mm)
55
IS62WV51216EFBLL-55BLI
mini BGA (6mm x 8mm), Lead-free
55
IS62WV51216EFBLL-55B2I
mini BGA (6mm x 8mm), ERR1/2 Pins
55
IS62WV51216EFBLL-55B2LI
mini BGA (6mm x 8mm), ERR1/2 Pins, Lead-free
55
IS62WV51216EFBLL-55B3I
mini BGA (6mm x 8mm), 1 CS Option, ERR Pin
55
IS62WV51216EFBLL-55B3LI
mini BGA (6mm x 8mm), 1 CS Option, ERR Pin, Lead-free
Automotive Range (A3): –40°C to +125°C
Speed (ns)
Order Part No.
Package
55
IS65WV51216EFBLL-55CTLA3
TSOP (Type II), Copper Lead-frame, Lead-free
55
IS65WV51216EFBLL-55BA3
mini BGA (6mm x 8mm)
55
IS65WV51216EFBLL-55BLA3
mini BGA (6mm x 8mm), Lead-free
55
IS65WV51216EFBLL-55B2A3
mini BGA (6mm x 8mm), ERR1/2 Pins
55
IS65WV51216EFBLL-55B2LA3
mini BGA (6mm x 8mm), ERR1/2 Pins, Lead-free
55
IS65WV51216EFBLL-55B3A3
mini BGA (6mm x 8mm), 1 CS Option, ERR Pin
55
IS65WV51216EFBLL-55B3LA3
mini BGA (6mm x 8mm), 1 CS Option, ERR Pin, Lead-free
IS62WV51216EFALL/BLL
IS65WV51216EFALL/BLL
Integrated Silicon Solution, Inc.- www.issi.com 19
Rev. A3
11/26/2018
PACKAGE INFORMATION
IS62WV51216EFALL/BLL
IS65WV51216EFALL/BLL
Integrated Silicon Solution, Inc.- www.issi.com 20
Rev. A3
11/26/2018