ACPL-061L, ACPL-C61L and ACNW261L
Ultra Low Power 10 MBd Digital CMOS Optocoupler
Data Sheet
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
A 0.1 μF bypass capacitor must be connected between pins VDD and GND
TRUTH TABLE
(POSITIVE LOGIC)
LED ENABLE OUTPUT
ON H L
OFF H H
ON L Z
OFF L Z
ON NC L
OFF NC H
Features
• Ultra low current IDD consumption: 1.5 mA max
• Low input current capability: 1.6 mA min (ACPL-061L),
3 mA min (ACPL-C61L), 4 mA min (ACNW261L)
• Available packages: SO-8, Stretched SO-8 and 400 mil
widebody
• Built-in slew-rate controlled output
• Tri-state output with enable pin VE
• Glitch free power-up and power-down
• 20 kV/μs minimum Common Mode Rejection (CMR) at
VCM = 1000 V
• High Speed: 10 MBd min
• Guaranteed AC and DC performance over wide
temperature: -40° C to +105° C
• Safety and Regulatory Approval
– UL 1577 recognized – 3750 Vrms for 1 minute for
ACPL-061L and 5000 Vrms for 1 minute for
ACPL-C61L/ACNW261L
– CSA Approval
– IEC/EN/DIN EN 60747-5-5 Approval for Reinforced
Insulation
Applications
• Communication Interface: RS485, CANBus, I2C
• Microprocessor System Interfaces
• Digital isolation for A/D, D/A conversion
Description
The ACPL-061L/ACPL-C61L/ACNW261L is an optically
coupled optocoupler that combines an AlGaAs light
emitting diode and an integrated high gain photo
detector addresses the low power need. The optocoupler
consumes extremely low power, at maximum 1.5 mA IDD
per channel across temperature. The forward current is as
low as 1.6 mA to 4 mA and allows direct current drive by
most microprocessors.
These optocouplers support both 3.3 V and 5 V supply
voltage with guaranteed AC and DC operational parame-
ters from temperature range -40° C to +105° C. The output
of the detector IC is a CMOS output. An enable input
allows the detector output to be strobed. The internal
Faraday shield provides a guaranteed common mode
transient immunity specication of 20 kV/μs.
The CMOS output is slew-rate controlled and is designed
to allow the rise time and fall time to be controlled over a
wide range of the load capacitance.
This unique design provides maximum AC and DC circuit
isolation while achieving TTL/CMOS compatibility. These
optocouplers are suitable for high speed logic interfacing,
while consuming extremely low power.
Functional Diagram
2
3
8
5
6
Anode
VDD
GND
VO
Shield
1
NC
NC 4
7VE
Cathode
2
Ordering Information
ACPL-061L is UL Recognized with 3750 Vrms for 1 minute per UL1577. ACPL-C61L and ACNW261L are UL Recognized
with 5000 Vrms for 1 minute per UL1577.
Part number
Option
Package
Surface
Mount Gull Wing
Tape &
Reel
UL 1577
5000 Vrms /
1 Minute rating
IEC/EN/DIN EN
60747-5-5 Quantity(RoHS Compliant)
ACPL-061L -000E SO-8 X 100 per tube
-060E X X 100 per tube
-500E X X 1500 per reel
-560E X X X 1500 per reel
ACPL-C61L -000E Stretched
SO-8
X X 80 per tube
-060E X X X 80 per tube
-500E X X X 1000 per reel
-560E X X X X 1000 per reel
ACNW261L -000E 400 mil
DIP-8
X X 42 per tube
-300E X X X X 42 per tube
-500E X X X X X 750 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-061L-560E to order product of Small Outline SO-8 package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
3
Package Outline Drawing
ACPL-061L SO-8 Package
ACPL-C61L Stretched SO-8 Package
5.850 ± 0.254
(0.230 ± 0.010)
5
678
4321
Dimensions in millimeters (inches)
Notes:
Lead coplanarity = 0.1 mm (0.004 inches)
Floating lead protrusion is 0.25mm (10mils) max
6.807 ± 0.127
(0.268 ± 0.005)
RECOMMENDED LAND PATTERN
12.650
(0.498)
1.905
(0.075)
3.180 ± 0.127
(0.125 ± 0.005)
0.381 ± 0.130
(0.015 ± 0.005)
1.270
(0.050) BSG
7°
0.254 ± 0.100
(0.010 ± 0.004)
0.750 ± 0.250
(0.0295 ± 0.010)
11.50 ± 0.250
(0.453 ± 0.010)
1.590 ± 0.127
(0.063 ± 0.005)
(0.018)
0.450 45°
RoHS-COMPLIANCE
INDICATOR
PART NUMBER
DATE CODE
C61L
YWW
0.64
(0.025)
0.200 ± 0.100
(0.008 ± 0.004)
XXXV
YWW
8765
4321
5.994 ± 0.203
(0.236 ± 0.008)
3.937 ± 0.127
(0.155 ± 0.005)
0.406 ± 0.076
(0.016 ± 0.003) 1.270
(0.050) BSC
5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005) 1.524
(0.060)
45° X 0.432
(0.017)
0.228 ± 0.025
(0.009 ± 0.001)
PART NUMBER
(LAST 3 DIGITS)
DATE CODE
0.305
(0.012) MIN.
0.203 ± 0.102
(0.008 ± 0.004)
7°
PIN ONE
0 ~ 7°
*
Total package length (inclusive of mold ash)
5.207 ± 0.254 (0.205 ± 0.010)
Dimensions in Millimeters (Inches)
Notes:
Lead coplanarity = 0.10 mm (0.004 inches) max.
Floating lead protrusion is 0.15 mm (6 mils) max.
Option number 500 not marked
*
7.49 (0.295)
1.9 (0.075)
0.64 (0.025)
LAND PATTERN RECOMMENDATION
4
ACNW261L 8-Pin Widebody DIP Package
ACNW261L 8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300E
A
ACNWXXX
YYWWX
DATE CODE
TYPE NUMBER
Dimensions in millimeters (inches)
Note:
Floating lead protrusion is 0.25 mm (10 mils) max.
67
32
1 4
7° TYP.
8 5
11.15 ± 0.15
(0.442 ± 0.006)
9.00 ± 0.15
(0.354 ± 0.006)
+0.076
0.254
- 0.0051
+0.003)
(0.010
- 0.002)
MAX.
11.00
(0.433)
MAX.
1.55
(0.061)
MAX.
5.10
(0.201)
MIN.
0.51
(0.021)
TYP.
10.16
(0.400)
TYP.
2.54
(0.100)
3.10 (0.122)
3.90 (0.154)
0.40 (0.016)
0.56 (0.022)
1.78 ± 0.15
(0.070 ± 0.006)
7° NOM.
6
7
3
2
LAND PATTERN RECOMMENDATION
85
14
Dimensions in millimeters (inches)
11.15 ± 0.15
(0.442 ± 0.006)
9.00 ± 0.15
(0.354 ± 0.006)
13.56
(0.534)
1.3
(0.051)
2.29
(0.09)
MAX.
1.55
(0.061)
MAX.
4.00
(0.158)
MAX.
11.00
(0.433)
BSC
2.54
(0.100)
1.78 ± 0.15
(0.070 ± 0.006)
12.30 ± 0.30
(0.484 ± 0.012)
0.75 ± 0.25
(0.030 ± 0.010)
+0.076
0.254
- 0.0051
+0.003)
(0.010
- 0.002)
1.00 ± 0.15
(0.039 ± 0.006)
Notes:
Lead coplanarity = 0.10 mm (0.004 inches)
Floating lead protrusion is 0.25 mm (10 mils) max.
5
Solder Reow Prole
Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-061L, ACPL-C61L, ACNW261L and are pending approval by the following organizations:
IEC/EN/DIN EN 60747-5-5 (Option 060E only)
UL
Approval under UL 1577, component recognition program up to VISO = 3750 VRMS for ACPL-061L and VISO = 5000 VRMS
for ACPL-C61L/ACNW261L File E55361.
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324.
Insulation and Safety Related Specications
Parameter Symbol ACPL-061L ACPL-C61L ACNW261L Unit Conditions
Minimum External Air Gap
(External Clearance)
L(101) 4.9 8 9.6 mm Measured from input terminals to
output terminals, shortest distance
through air.
Minimum External
Tracking (External Creepage)
L(102) 4.8 8 10 mm Measured from input terminals to
output terminals, shortest distance
path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08 0.5 1.0 mm Through insulation distance conductor
to conductor, usually the straight line
distance thickness between the
emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI 175 175 175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa IIIa IIIa Material Group (DIN VDE 0110, 1/89,
Table 1)
6
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060)
Description Symbol
Characteristic
UnitACPL-061L ACPL-C61L ACNW261L
Installation classication per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000 Vrms
I – IV
I – III
I – II
I – IV
I – IV
I – IV
I – III
I – IV
I – IV
I – IV
I – III
Climatic Classication 55/105/21 55/105/21 55/105/21
Pollution Degree (DIN VDE 0110/39) 2 2 2
Maximum Working Insulation Voltage VIORM 567 1414 1414 Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial discharge < 5 pC
VPR 1063 2651 2651 Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial discharge < 5 pC
VPR 907 2262 2262 Vpeak
Highest Allowable Overvoltage
(Transient Overvoltage tini = 60 sec)
VIOTM 6000 8000 8000 Vpeak
Safety-limiting values – maximum values allowed in the
event of a failure.
Case Temperature
Input Current**
Output Power**
TS
IS, INPUT
PS, OUTPUT
150
150
600
175
230
600
150
400
700
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V RS>109>109>109W
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test proles.
** Refer to the following gure for dependence of PS and IS on ambient temperature.
0
TS – CASE TEMPERATURE – °C
400
600
200
100
300
500
700
PS (mW)
IS (mA)
Surface Mount SO-8 Product
0
200
400
600
800
1000
0 25 50 75 100 125 150 175
TS – CASE TEMPERATURE – °C
PS (mW)
IS (mA)
POWER OUTPUT – PS, INPUT CURRENT – IS
Surface Mount SSO-8 Product
0
400
600
800
200
100
300
500
700
PS (mW)
IS (mA)
Widebody 400mil DIP-8 Product
1000
900
POWER OUTPUT – PS, INPUT CURRENT – IS
POWER OUTPUT – PS, INPUT CURRENT – IS
0 25 50 75 100 125 150 175 0 25 50 75 100 125 150 175200
TS – CASE TEMPERATURE – °C
7
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-55 125 °C
Operating Ambient Temperature TA-40 105 °C
Reversed Input Voltage VR5 V
Supply Voltage VDD 6.5 V
Average Forward Input Current IF– 8 mA
Peak Transient Input Current IFTRAN – 1 A < 1 μs Pulse Width,
< 300 pulses per second
80 mA < 1 μs Pulse Width,
<10% Duty Cycle
Output Current IO10 mA
Output Voltage VO-0.5 VDD + 0.5 V
Input Power Dissipation PI14 mW per channel
Output Power Dissipation PO20 mW per channel
Lead Solder Temperature TLS 260°C for 10 sec., 1.6 mm below seating plane
Solder Reow Temperature Prole Refer to Solder Reow Prole section
Recommended Operating Conditions
Parameter Symbol Part Number Min Max Units
Operating Temperature TA-40 105 °C
Input Current, Low Level IFL 0 250 μA
Input Current, High Level IFH ACPL-061L 1.6 6 mA
ACPL-C61L 3 8 mA
ACNW261L 4 8 mA
Power Supply Voltage VDD 2.7 5.5 V
Forward Input Voltage VF (OFF) 0.8 V
8
Electrical Specications (DC)
Over recommended temperature (TA = -40° C to 105° C) and supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specications
are at VDD = 5 V, TA = 25° C.
Parameter Symbol Part Number Min Typ Max Units Test Conditions
Input Forward Voltage VFACPL-061L 0.95 1.3 1.7 V IF = 2 mA, Figure 1a, 2a
ACPL-C61L 1.2 1.5 1.9 V IF = 5 mA, Figure 1b, 2b
ACNW261L 1.2 1.5 1.9 V IF = 5 mA, Figure 1b, 2b
Input Reverse
Breakdown Voltage
BVRACPL-061L 3 5 V IR = 10 μA
ACPL-C61L 7 10 V IR = 10 μA
ACNW261L 7 10 V IR = 10 μA
Logic High Output Voltage VOH VDD - 0.1 VDD V IF = 0 mA, VI = 0 V,
IO = -20 μA
VDD - 1.0 VDD V IF = 0 mA, VI = 0 V,
IO = -3.2mA
Logic Low Output Voltage VOL 0.03 0.1 V IF = 2 mA, VI = 5 V/3.3 V,
IO = 20 μA
0.18 0.4 V IF = 2 mA, VI = 5 V/3.3 V,
IO = 3.2 mA
Input Threshold Current ITH ACPL-061L 0.7 1.3 mA Figure 3a
ACPL-C61L 1.5 2.2 mA Figure 3b
ACNW261L 1.5 3 mA Figure 3b
Logic Low Output Supply
Current
IDDL 0.8 1.5 mA Figure 4
Logic High Output Supply
Current
IDDH 0.8 1.5 mA Figure 5
Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V
High Level Enable Current IEH -0.7 -1.6 mA VDD = 5.5 V, VE = 3.0 V
Low Level Enable Current [4] IEL -0.9 -1.6 mA VDD = 5.5 V, VE = 0.5 V
High Level Enable Voltage [10] VEH 0.7 x VDD V3.0 V ≤ VDD ≤ 5.5 V
Low Level Enable Voltage [10] VEL 0.3 x VDD V3.0 V ≤ VDD ≤ 5.5 V
Input Diode Temperature
Coecient
ΔVF/ΔTAACPL-061L -1.6 mV/°C IF = 2 mA
ACPL-C61L -1.9 mV/°C IF = 3 mA
ACNW261L -1.9 mV/°C IF = 5 mA
9
Switching Specications (AC)
Over recommended temperature (TA = -40° C to +105° C), supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specications
are at VDD = 5 V, TA = 25° C
Parameter Symbol Part Number Min Typ Max Units Test Conditions
Propagation Delay Time to
Logic Low Output [1]
tPHL ACPL-061L 46 80 ns IF = 2 mA, VI = 5 V, RT = 1.68 kW,
CL= 15 pF, CMOS Signal Levels.
IF = 2 mA, VI = 3.3 V, RT = 870 W,
CL= 15 pF, CMOS Signal Levels.
Figure 6a, 7a
Propagation Delay Time to
Logic High Output [1]
tPLH 40 80 ns
Pulse Width tPW 100 ns
Pulse Width Distortion [2] PWD 6 30 ns
Propagation Delay Skew [3] tPSK 30 ns
Output Rise Time
(10% – 90%)
tR12 ns IF = 2 mA, VI = 5 V, RT = 1.68 kW,
CL= 15 pF, CMOS Signal Levels.
10 ns IF = 2 mA, VI = 3.3 V, RT = 870 W,
CL= 15 pF, CMOS Signal Levels.
Output Fall Time
(90% – 10%)
tF12 ns IF = 2 mA, VI = 5 V, RT = 1.68 kW,
CL= 15 pF, CMOS Signal Levels.
10 ns IF = 2 mA, VI = 3.3 V, RT = 870 W,
CL= 15 pF, CMOS Signal Levels.
Propagation Delay Time to
Logic Low Output [1]
tPHL ACPL-C61L
47 90 ns IF = 5 mA, VI = 5 V, RT = 680 W,
CL= 15 pF, CMOS Signal Levels.
IF = 5 mA, VI = 3.3 V, RT = 340 W,
CL= 15 pF, CMOS Signal Levels.
Figure 6b, 7b
Propagation Delay Time to
Logic High Output [1]
tPLH 38 90 ns
Pulse Width tPW 100 ns
Pulse Width Distortion [2] PWD 9 40 ns
Propagation Delay Skew [3] tPSK 30 ns
Output Rise Time (10% – 90%) tR12 ns IF = 5 mA, VI = 5 V, RT = 680 Ω,
CL= 15 pF, CMOS Signal Levels.
10 ns IF = 5 mA, VI = 3.3 V, RT = 340 Ω,
CL= 15 pF, CMOS Signal Levels.
Output Fall Time (90% - 10%) tF12 ns IF = 5 mA, VI = 5 V, RT = 680 Ω,
CL= 15 pF, CMOS Signal Levels.
10 ns IF = 5 mA, VI = 3.3 V, RT = 340 Ω,
CL= 15 pF, CMOS Signal Levels.
Propagation Delay Time
to Logic Low Output [1]
tPHL ACNW261L 66 95 ns IF = 5 mA, VI = 5 V, RT = 680 W,
CL= 15 pF, CMOS Signal Levels.
IF = 5 mA, VI = 3.3 V, RT = 340 W,
CL= 15 pF, CMOS Signal Levels.
Figure 6c, 7c
Propagation Delay Time
to Logic High Output [1]
tPLH 47 95 ns
Pulse Width tPW 100 ns
Pulse Width Distortion [2] PWD 19 40 ns
Propagation Delay Skew [3] tPSK 30 ns
Output Rise Time
(10% – 90%)
tR12 ns IF = 5 mA, VI = 5 V, RT = 680 W,
CL= 15 pF, CMOS Signal Levels.
10 ns IF = 5 mA, VI = 3.3 V, RT = 340 W,
CL= 15 pF, CMOS Signal Levels.
Output Fall Time
(90% - 10%)
tF12 ns IF = 5 mA, VI = 5 V, RT = 680 W,
CL= 15 pF, CMOS Signal Levels.
10 ns IF = 5 mA, VI = 3.3 V, RT = 340 W,
CL= 15 pF, CMOS Signal Levels.
Propagation Delay Time of
Enable from VEH to VEL [5]
tELH 9 ns VEL = 0 V, VEH = 3 V, CL= 15 pF
Figure 8
Propagation Delay Time of
Enable from VEL to VEH [6]
tEHL 12 ns
10
Switching Specications (AC) (Continued)
Parameter Symbol Part Number Min Typ Max Units Test Conditions
Static Common Mode
Transient Immunity at
Logic High Output [7]
| CMH | ACPL-061L 20 35 kV/μsVCM = 1000 V, TA = 25° C, IF = 0 mA,
VI = 0V, CL= 15 pF, CMOS Signal
Levels. Figure 9
Static Common Mode
Transient Immunity at
Logic Low Output [8]
| CML | 20 35 kV/μsVCM = 1000 V, TA = 25° C, IF = 2 mA,
VI = 5 V/3.3 V, CL= 15 pF, CMOS
Signal Levels. Figure 9
Dynamic Common Mode
Transient Immunity [9]
CMRD35 kV/μsVCM = 1000 V, TA = 25° C, IF = 2 mA,
VI = 5 V/3.3 V, 10 MBd data rate,
the absolute increase of PWD <10
ns. Figure 9
Static Common Mode
Transient Immunity at
Logic High Output [7]
| CMH | ACPL-C61L 20 35 kV/μsVCM = 1000 V, TA = 25° C, IF = 0 mA,
VI = 0 V, CL= 15 pF, CMOS Signal
Levels. Figure 9
Static Common Mode
Transient Immunity at
Logic Low Output [8]
| CML | 20 35 kV/μsVCM = 1000 V, TA = 25° C, IF = 5 mA,
VI = 5 V/3.3 V, CL= 15 pF, CMOS
Signal Levels.
Dynamic Common Mode
Transient Immunity [9]
CMRD35 kV/μsVCM = 1000 V, TA = 25° C, IF = 5 mA,
VI = 5 V/3.3 V, 10 MBd datarate, the
absolute increase of PWD <10 ns.
Figure 9
Static Common Mode
Transient Immunity at
Logic High Output [7]
| CMH | ACNW261L 20 35 kV/μsVCM = 1000 V, TA = 25° C, IF = 0 mA,
VI = 0 V, CL= 15 pF, CMOS Signal
Levels. Figure 9
Static Common Mode
Transient Immunity at
Logic Low Output [8]
| CML | 20 35 kV/μsVCM = 1000 V, TA = 25° C, IF = 5 mA,
VI = 5 V/3.3 V, CL= 15pF, CMOS
Signal Levels. Figure 9
Dynamic Common Mode
Transient Immunity [9]
CMRD35 kV/μsVCM = 1000 V, TA = 25° C, IF = 5 mA,
VI = 5 V/3.3 V, 10 MBd datarate, the
absolute increase of PWD <10 ns.
Figure 9
Package Characteristics
All typical at TA = 25° C.
Parameter Symbol Part Number Min Typ Max Units Test Conditions
Input-Output Insulation VISO ACPL-061L 3750 Vrms RH < 50% for 1 min. TA = 25° C
ACPL-C61L
ACNW261L
5000
Input-Output Resistance RI-O 1012 W VI-O = 500 V
Input-Output Capacitance CI-O 0.6 pF f = 1 MHz, TA = 25° C
Notes:
1. tPHL propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% VDD of the falling edge of the VO
signal. tPLH propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% level of the rising edge of the
VO signal.
2. PWD is dened as |tPHL - tPLH|.
3. tPSK is equal to the magnitude of the worst case dierence in tPHL and/or tPLH that will be seen between units at any given temperature within the
recommended operating conditions.
4. The JEDEC registration for the ACPL-061L/ACPL-C61L/ACNW261L species a maximum IEL of -2.0 mA. Avago guarantees a maximum IEL of -1.6
mA.
5. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising
edge of the output pulse.
6. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling
edge of the output pulse.
7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
9. CMD is the maximum tolerable rate of the common mode voltage during data transmission to assure that the absolute increase of the PWD is less
than 10 ns.
10. When VE pin is not used, connects VE to VDD will result in improved CMR performance.
11
Figure 1a. Typical input diode forward characteristic (ACPL-061L) Figure 1b. Typical input diode forward characteristic (ACPL-C61L/ACNW261L)
Figure 2a. Typical VF versus temperature (ACPL-061L) Figure 2b. Typical VF versus temperature (ACPL-C61L/ACNW261L)
Figure 3a. Typical input threshold current ITH versus temperature
(ACPL-061L)
Figure 3b. Typical input threshold current ITH versus temperature
(ACPL-C61L/ACNW261L)
0.01
0.1
1
10
1.1 1.2 1.3 1.4 1.5
VF - FORWARD VOLTAGE - V
IF - FORWARD CURRENT - mA
IF
VF
TA = 25° C
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
-40 -20 0 20 40 60 80 100
TA - TEMPERATURE - °C
VF - FORWARD VOLTAGE - V
TA - TEMPERATURE - °C
VF - FORWARD VOLTAGE - V
0.01
0.1
1
10
1.2 1.3 1.4 1.5 1.7
VF - FORWARD VOLTAGE - V
1.6
I
F
- FORWARD CURRENT - mA
1.35
1.4
1.45
1.5
1.55
1.6
1.65
1.7
-40 -20 0 20 40 60 80 100 120
0
0.2
0.4
0.6
0.8
1
-40 -20 0 20 40 60 80 100 120
TA - TEMPERATURE - °C
Ith - INPUT THRESHOLD CURRENT - mA
3.3 V
5 V
TA - TEMPERATURE - °C
Ith - INPUT THRESHOLD CURRENT - mA
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
-40 -20 0 20 40 60 80 100 120
ITH_5.0 V
ITH_3.3 V
12
Figure 4. Typical logic low output supply current IDDL versus temperature Figure 5. Typical logic high output supply current IDDH versus temperature
Figure 6a. Typical switching speed versus pulse input current at 5 V supply
voltage (ACPL-061L)
Figure 6b. Typical switching speed versus pulse input current at 5 V supply
voltage (ACPL-C61L)
TA - TEMPERATURE - °C
IDDL - LOGIC LOW OUTPUT SUPPLY
CURRENT - mA
IDDH - LOGIC HIGH OUTPUT SUPPLY
CURRENT - mA
TA - TEMPERATURE - °C
-10
0
10
20
30
40
50
60
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
IF - PULSE INPUT CURRENT - mA
tp - PROPAGATION DELAY;
PWD-PULSE WIDTH DISTORTION - ns
IF - PULSE INPUT CURRENT - mA
tp - PROPAGATION DELAY;
PWD-PULSE WIDTH DISTORTION - ns
TPHL_5.0 V
TPLH_5.0 V
PWD_5.0 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-40 -20 0 20 40 60 80 100 120
0
10
20
30
40
50
60
70
3456789
0
0.2
0.4
0.6
0.8
1
1.2
-40 -20 0 20 40 60 80 100 120
IDDL _5.0 V
IDDL _3.3 V
IDDH _5.0 V
IDDH _3.3 V
TPLH_5.0 V
PWD_5.0 V
TPHL_5.0 V
IF - PULSE INPUT CURRENT -mA
tp - PROPAGATION DELAY;
PWD-PULSE WIDTH DISTORTION - ns
TPLH_5.0 V
PWD_5.0 V
TPHL_5.0 V
-10
0
10
20
30
40
50
60
70
80
3456789
Figure 6c. Typical switching speed versus pulse input current at 5 V supply
voltage (ACNW261L)
13
Figure 7a. Typical switching speed versus pulse input current at 3.3 V supply
voltage (ACPL-061L)
Figure 7b. Typical switching speed versus pulse input current at 3.3 V supply
voltage (ACPL-C61L)
Figure 8. Timing diagrams for tEHL and tELH
Figure 7c. Typical switching speed versus pulse input current at 3.3 V supply
voltage (ACNW261L)
-10
0
10
20
30
40
50
60
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
IF - PULSE INPUT CURRENT -mA
tp - PROPAGATION DELAY;
PWD-PULSE WIDTH DISTORTION - ns
IF - PULSE INPUT CURRENT -mA
tp - PROPAGATION DELAY;
PWD-PULSE WIDTH DISTORTION - ns
IF - PULSE INPUT CURRENT -mA
tp - PROPAGATION DELAY;
PWD-PULSE WIDTH DISTORTION - ns
TPHL_3.3 V
TPLH_3.3 V
PWD_3.3 V
TPLH_3.3 V
PWD_3.3 V
TPHL_3.3 V
TPLH_3.3 V
PWD_3.3 V
TPHL_3.3 V
0
10
20
30
40
50
60
70
3456789
-10
0
10
20
30
40
50
60
70
80
3456789
1.5 V
tPHL tPLH
IF
INPUT
VO
OUTPUT
3.0 V
1.5 V
14
Figure 9. Recommended printed circuit board layout
Pulse-width distortion (PWD) results when tPLH and tPHL
dier in value. PWD is dened as the dierence between
tPLH and tPHL and often PWD is dened as the dierence
between tPLH and tPHL. This parameter determines the
maximum data rate capability of a transmission system.
PWD can be expressed in percent by dividing the PWD (in
ns) by the minimum pulse width (in ns) being transmitted.
Typically, PWD in the order of 20-30% of the minimum
pulse width is tolerable; the exact gure depends on the
particular application (RS232, RS422, T-1, etc.).
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applications where synchroni-
zation of signals on parallel data lines is a concern. If the
parallel data is being sent through a group of optocou-
plers, dierences in propagation delays will cause the data
to arrive at the outputs of the optocouplers at dierent
times. If this dierence in propagation delays is large
enough, it will determine the maximum rate at which
parallel data can be sent through the optocouplers.
Propagation delay skew is dened as the dierence
between the minimum and maximum propagation delays,
either tPLH or tPHL, for any given group of optocouplers
which are operating under the same conditions (i.e., the
same supply voltage, output load, and operating temper-
ature). As illustrated in Figure 10, if the inputs of a group of
optocouplers are switched either ON or OFF at the same
time, tPSK is the dierence between the shortest propaga-
tion delay, either tPLH or tPHL, and the longest propagation
Bypassing and PC Board Layout
The ACPL-061L/ACPL-C61L/ACNW261L optocouplers are
extremely easy to use. ACPL-061L/ACPL-C61L/ACNW261L
provide CMOS logic output due to the high-speed CMOS
IC technology used.
The external components required for proper operation
are the input limiting resistors and the output bypass
capacitor. Capacitor values should be 0.1 μF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm.
Propagation Delay, Pulse-Width Distortion and
Propagation Delay Skew
Propagation delay is a gure of merit which describes how
quickly a logic signal propagates through a system. The
propagation delay from low to high (tPLH) is the amount
of time required for an input signal to propagate to the
output, causing the output to change from low to high.
Similarly, the propagation delay from high to low (tPHL)
is the amount of time required for the input signal to
propagate to the output, causing the output to change
from high to low (see Figure 9).
Figure 10. Propagation delay skew waveform
50%
50%
tPSK
VI
VO
VI
VO
2.5 V,
CMOS
2.5 V,
CMOS
DATA
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
tPSK
tPSK
Figure 11. Parallel data transmission example
Anode
Cathode
V
CM
Pulse Gen
C = 0.1µF
Output
Monitoring
node
VOGND
O
V (min.)
VDD
0 V SWITCH AT A: I = 0 mA
F
SWITCH AT B: I = 2 mA (ACPL-061L) / 5 mA (ACPL-C61L/ACNW261L)
F
CM
V
H
CM
CM L
O
V (max.)
CM
V (PEAK)
VO
5
3
4
27
6
8
1
XXX
YWW
IF
GND1
VDD
C = 0.1 µF
GND2
VI
R1
R2
VE
VO
RT = R1 + R2, R1/R2 ≈ 1.5
ACPL-061L / ACPL-C61L / ACNW261L
3.3V / 5V
B
IF
2
3
8
5
6
VDD
GND
VO
Shield
1
4
7VE
−
+
A
15
delay, either tPLH or tPHL. As mentioned earlier, tPSK can
determine the maximum parallel data transmission rate.
Figure 10 is the timing diagram of a typical parallel data
application with both the clock and the data lines being
sent through optocouplers. The gure shows data and
clock signals at the inputs and outputs of the optocou-
plers. To obtain the maximum data transmission rate, both
edges of the clock signal are being used to clock the data;
if only one edge were used, the clock signal would need
to be twice as fast.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an
optocoupler. Figure 10 shows that there will be uncer-
tainty in both the data and the clock lines. It is important
that these two areas of uncertainty not overlap, otherwise
the clock signal might arrive before all of the data outputs
have settled, or some of the data outputs may start to
change before the clock signal has arrived.
From these considerations, the absolute minimum pulse
width that can be sent through optocouplers in a parallel
application is twice tPSK. A cautious design should use a
slightly longer pulse width to ensure that any additional un-
certainty in the rest of the circuit does not cause a problem.
The tPSK specied optocouplers oer the advantages of
guaranteed specications for propagation delays, pulse-
width distortion and propagation delay skew over the
recommended temperature, and power supply ranges.
Optocoupler CMR performance
The principal protection against common mode noise
comes down to the fundamental isolation properties of
the optocoupler, this in turn is directly related to the input-
output leakage capacitance of the optocoupler.
To provide maximum protection to circuitry connected to
the input or output of the optocoupler the leakage capac-
itance is minimized by having large separation distances
at all points in the optocoupler construction, including
the LED/photodiode interface.
In addition to the constructional design, additional circuit
design steps are taking to further mitigate the eects of
common mode noise. The most important of these is the use
of a Faraday shield on the photodetector stage. This faraday
shield is eective in optocouplers because the internal
modulation frequency (light) is many orders of magnitude
higher than the common mode noise frequency.
Application level CMR Performance
In application, it desirable that the optocoupler’s common
mode isolation perform as close as possible to that
indicated in the data sheets specications.
The rst step in meeting this goal is to ensure maintain-
ing maximum separation between PCB interconnects on
either side of the optocoupler and avoid routing tracks
beneath the optocoupler. Nonetheless, it is inevitable that
a certain amount of CMR noise will be coupled into the
inputs which can potentially result in false-triggering of
the input.
This problem is frequently observed in devices with input
high input impedence such as CMOS buered inputs in
either optocoupler or alternate isolator technologies.
In some cases, this not only causes momentary missing
pulses but in some technologies may even cause input
circuitry to latch-up.
ACPL-061L/ACPL-C61L/ACNW261L optocoupler family
does not face input latch up issue even at very high CMR
levels, such as those experienced in end equipment level
tests (for example IEC61004-4-4) due to the simple diode
structure of the LED.
In some cases achieving the rated data sheet CMR perfor-
mance levels is not possible in the intended application,
often because of the practical need to actually connect
the isolator input to the output of a dynamically changing
signal rather than tying the input statically to VDD1 or
GND1.
This specsmanship issue is often observable with alterna-
tive isolators utilizing AC encoding techniques.
To address this requirement for clear transparency on the
achievable end application performance, the ACPL-061L/
ACPL-C61L/ACNW261L series of optocouplers includes an
additional typical performance indication of the dynamic
CMR in the electrical parameter table. What this informa-
tion indicates is the achievable CMR performance whilst
the input is being toggled on or o during the occurrence
of a CMR transient. The logic output of the optocoupler
is mainly controlled by the level of the LED current due
to the short transition rise/fall time of the LED current
(approximately 10ns), the dynamic noise immunity is
essentially the same as the static noise immunity.
To achieve this goal of meeting the maximum inherent
CMR capabilities of the ACPL-061L/ACPL-C61L/ACNW261L
family, some simple consideration needs to be given to
the operation of the LED at the application level.
In particular ensuring that the LED stays either on or o
during a CMR transient.
Some common design techniques which are sometimes
used to meet this goal:
Keeping LED On:
i) Overdrive the LED with a higher than required forward
current.
Keeping LED O:
i) Reverse bias the LED during the o state.
ii) Minimize the o state impedance across the anode and
cathode of the LED during the o state.
All these methods are fully capability of enabling the
full CMR capabilities o the ACPL-061L/ACPL-C61L/
ACNW261L family to be achieved. But they do come at the
cost of practical implementation issues or a compromise
on power consumption.
An eective method to meet the goal of maintaining
the LED status during a CMR event with no other design
compromises other the addition of a single low cost
component (resistor).
16
Table 1 indicates the directions of ILP and ILN ow
depending on the direction of the common-mode
transient. For transients occurring when the LED is on,
common-mode rejection (CML, since the output is in the
“low” state) depends upon the amount of LED current
drive (IF). For conditions where IF is close to the switching
threshold (ITH), CML also depends on the extent which ILP
and ILN balance each other. In other words, any condition
where common-mode transients cause a momentary
decrease in IF (i.e. when dVCM/dt>0 and |IFP| > |IFN|,
referring to Table 1) will cause common-mode failure for
transients which are fast enough.
Likewise for common-mode transients which occur when
the LED is o (i.e. CMH, since the output is “high”), if an
imbalance between ILP and ILN results in a transient IF
equal to or greater than the switching threshold of the
optocoupler, the transient “signal” may cause the output
to spike below 2 V (which constitutes a CMH failure).
The balanced ILED-setting resistors help equalize the
common mode voltage change at anode and cathode
to reduce the amount by which ILED is modulated from
transient coupling through CLA and CLC.
Figure 12. Recommended drive circuit for ACPL-061L/ACPL-C61L/ACNW261L for high-CMR
Figure 13. AC equivalent of ACPL-061L/ACPL-C61L/ACNW261L
This CMR optimization method fundamentally makes
use of the dierential input capability of the LED input.
By ensuring the common mode impedance on both the
cathode and anode of the LED are balanced, it eectively
nullies the eect of a CMR transient on the LED. This is
most easily achieved by splitting the input bias resistor
into two (as shown in Figure 9).
Split resistor conguration for ACPL-061L/ACPL-C61L/
ACNW261L
Figure 12 shows the recommended drive circuit for the
ACPL-061L/ACPL-C61L/ACNW261L for optimal common-
mode rejection performance. Two LED-current setting
resistors are used to balance the common mode impe-
dance at LED anode and cathode. Common-mode tran-
sients can capacitively couple from the LED anode (or
cathode) to the output-side ground causing current to be
shunted away from the LED (which can be bad if the LED
is on) or conversely cause current to be injected into the
LED (bad if the LED is meant to be o). Figure12 shows the
parasitic capacitances which exists between LED anode/
cathode and output ground (CLA and CLC).
8
5
6
Anode
VDD
VO
Shield
Cathode
7VE
0.1 µF
R1
R2
CLA
CLC
2
3
1
4
8
5
6
Shield
7
0.1 µF
R1
R2
GND2
RT = R1 + R2, R1/R2 ≈ 1.5
2
3
1
4
Anode
Cathode
VI
GND1
VDD
VO
VE
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Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-3195EN - May 13, 2013
Table 1. Eects of Common Mode Pulse Direction on Transient ILED
If dVCM/dt Is: then ILP Flows: and ILN Flows:
If |ILP| < |ILN|,
LED IF Current
Is Momentarily:
If |ILP| > |ILN|,
LED IF Current
Is Momentarily:
positive (>0) away from LED
anode through CLA
away from LED
cathode through CLC
increased decreased
negative (<0) toward LED
anode through CLA
toward LED
cathode through CLC
decreased increased
Glitch free power-up and power-down
Upon power-up or power-down of the optocoupler,
glitches produced in the output are undesirable. Glitches
can lead to false data in the optocoupler application.
ACPL-061L/ACPL-C61L/ACNW261L has a feature that
holds the output in a known state until VDD is at a safe
level. Figure 14 and 15 show typical output waveforms
during power-up and power-down.
Slew-rate controlled output
Typically, the output slew rate (rise and fall time) will vary
with the output load, as more time is needed to charge up
the higher load. The propagation delay and the PWD will
increase with the load capacitance. This will be an issue
especially in parallel communication because dierent
communication line will have dierent load capacitances.
However, ACPL-061L/ACPL-C61L/ACNW261L has built in
slew-rate controlled feature, to ensure that the output rise
and fall time remain stable across wide load capacitance.
Figure 14. VDD Ramp when LED is o. Figure 15. VDD Ramp when LED is on.
500 µs
VDD2 = 1 V (typ)
VDD2
High
Impedence
High
Impedence
i. LED is o.
Output
500 µs
ii. LED is on.
VDD2
Output
VDD2 = 1 V (typ)
High
Impedence
High
Impedence
VDD2 = 2 V (typ)
discharge delay,
depending on the power
supply slew rate