KAI-2001 IMAGE SENSOR 1600 (H) X 1200 (V) INTERLINE CCD IMAGE SENSOR JUNE 22, 2012 DEVICE PERFORMANCE SPECIFICATION REVISION 1.0 PS-0018 KAI-2001 Image Sensor TABLE OF CONTENTS Summary Specification ......................................................................................................................................................................................... 5 Description .................................................................................................................................................................................................... 5 Features ......................................................................................................................................................................................................... 5 Applications .................................................................................................................................................................................................. 5 Ordering Information ............................................................................................................................................................................................ 6 Device Description ................................................................................................................................................................................................. 7 Architecture .................................................................................................................................................................................................. 7 Pixel................................................................................................................................................................................................................. 8 Vertical to Horizontal Transfer ................................................................................................................................................................ 9 Horizontal Register to Floating Diffusion .......................................................................................................................................... 10 Horizontal Register Split......................................................................................................................................................................... 11 Single Output Operation .................................................................................................................................................................... 11 Dual Output Operation ....................................................................................................................................................................... 11 Output ......................................................................................................................................................................................................... 12 Pin Description and Physical Orientation ........................................................................................................................................... 13 Imaging Performance .......................................................................................................................................................................................... 14 Typical Operational Conditions............................................................................................................................................................. 14 Specifications............................................................................................................................................................................................. 14 All Configurations ................................................................................................................................................................................ 14 KAI-2001-ABA Configuration ............................................................................................................................................................. 15 KAI-2001-CBA Configuration ............................................................................................................................................................. 15 Typical Performance Curves ............................................................................................................................................................................ 16 Quantum Efficiency.................................................................................................................................................................................. 16 Monochrome with Microlens ............................................................................................................................................................. 16 Monochrome without Microlens ...................................................................................................................................................... 16 Color (Bayer RGB) with Microlens .................................................................................................................................................... 17 Angular Quantum Efficiency .................................................................................................................................................................. 18 Monochrome with Microlens ............................................................................................................................................................. 18 Dark Current versus Temperature ....................................................................................................................................................... 18 Power - Estimated .................................................................................................................................................................................... 19 Frame Rates ............................................................................................................................................................................................... 19 Defect Definitions ................................................................................................................................................................................................ 20 Defect Map ................................................................................................................................................................................................. 20 Test Definitions ..................................................................................................................................................................................................... 21 Test Regions of Interest ......................................................................................................................................................................... 21 OverClocking ............................................................................................................................................................................................. 21 Tests ............................................................................................................................................................................................................. 22 Dark Field Center Non-Uniformity ................................................................................................................................................... 22 Dark Field Global Non-Uniformity .................................................................................................................................................... 22 Global Non-Uniformity ........................................................................................................................................................................ 22 Global Peak to Peak Non-Uniformity............................................................................................................................................... 22 Center Non-Uniformity ....................................................................................................................................................................... 23 Dark Field Defect Test ........................................................................................................................................................................ 23 Bright Field Defect Test ...................................................................................................................................................................... 23 Test Sub Regions of Interest ............................................................................................................................................................. 24 Operation .................................................................................................................................................................................................................. 25 Maximum Ratings ..................................................................................................................................................................................... 25 Maximum Voltage Ratings Between Pins .......................................................................................................................................... 25 www.truesenseimaging.com Revision 1.0 PS-0018 Pg 2 KAI-2001 Image Sensor DC Bias Operating Conditions ............................................................................................................................................................... 26 AC Operating Conditions ........................................................................................................................................................................ 27 Clock Levels ........................................................................................................................................................................................... 27 Clock Line Capacitances ...................................................................................................................................................................... 27 Timing Requirements .............................................................................................................................................................................. 28 Timing Modes ............................................................................................................................................................................................ 29 Progressive Scan ................................................................................................................................................................................... 29 Frame Timing ............................................................................................................................................................................................. 30 Frame Timing without Binning - Progressive Scan ...................................................................................................................... 30 Frame Timing for Vertical Binning by 2 - Progressive Scan ....................................................................................................... 30 Frame Timing Edge Alignment .......................................................................................................................................................... 31 Line Timing ................................................................................................................................................................................................. 32 Line Timing Single Output - Progressive Scan .............................................................................................................................. 32 Line Timing Dual Output - Progressive Scan ................................................................................................................................. 32 Line Timing Vertical Binning by 2 - Progressive Scan ................................................................................................................. 33 Line Timing Detail - Progressive Scan ............................................................................................................................................. 33 Line Timing Binning by 2 Detail - Progressive Scan ..................................................................................................................... 34 Line Timing Edge Alignment .............................................................................................................................................................. 34 Pixel Timing ................................................................................................................................................................................................ 35 Pixel Timing Detail ............................................................................................................................................................................... 35 Fast Line Dump Timing ............................................................................................................................................................................ 36 Electronic Shutter ..................................................................................................................................................................................... 37 Electronic Shutter Line Timing .......................................................................................................................................................... 37 Electronic Shutter - Integration Time Definition ......................................................................................................................... 37 Electronic Shutter - DC and AC Bias Definition ............................................................................................................................ 37 Electronic Shutter Description .......................................................................................................................................................... 38 Large Signal Output ................................................................................................................................................................................. 39 Storage and Handling .......................................................................................................................................................................................... 40 Storage Conditions................................................................................................................................................................................... 40 ESD ............................................................................................................................................................................................................... 40 Cover Glass Care and Cleanliness ......................................................................................................................................................... 40 Environmental Exposure ........................................................................................................................................................................ 40 Soldering Recommendations ................................................................................................................................................................ 40 Mechanical Drawings ........................................................................................................................................................................................... 41 Completed Assembly ............................................................................................................................................................................... 41 Die to Package Alignment ...................................................................................................................................................................... 42 Glass ............................................................................................................................................................................................................. 43 Glass Transmission ................................................................................................................................................................................... 44 Quality Assurance and Reliability .................................................................................................................................................................. 45 Quality and Reliability ............................................................................................................................................................................. 45 Replacement .............................................................................................................................................................................................. 45 Liability of the Supplier ........................................................................................................................................................................... 45 Liability of the Customer ........................................................................................................................................................................ 45 Test Data Retention ................................................................................................................................................................................. 45 Mechanical.................................................................................................................................................................................................. 45 Life Support Applications Policy .................................................................................................................................................................... 45 Revision Changes................................................................................................................................................................................................... 46 MTD/PS-0609 ............................................................................................................................................................................................. 46 PS-0018 ....................................................................................................................................................................................................... 46 www.truesenseimaging.com Revision 1.0 PS-0018 Pg 3 KAI-2001 Image Sensor TABLE OF FIGURES Figure 1: Sensor Architecture ...................................................................................................................................................................... 7 Figure 2: Pixel Architecture .......................................................................................................................................................................... 8 Figure 3: Vertical to Horizontal Transfer Architecture ......................................................................................................................... 9 Figure 4: Horizontal Register to Floating Diffusion Architecture ....................................................................................................10 Figure 5: Horizontal Register .....................................................................................................................................................................11 Figure 6: Output Architecture ...................................................................................................................................................................12 Figure 7: Package Pin Designations - Top View ....................................................................................................................................13 Figure 8: Monochrome with Microlens Quantum Efficiency..............................................................................................................16 Figure 9: Monochrome without Microlens Quantum Efficiency .......................................................................................................16 Figure 10: Color Quantum Efficiency .......................................................................................................................................................17 Figure 11: Angular Quantum Efficiency ..................................................................................................................................................18 Figure 12: Dark Current versus Temperature ........................................................................................................................................18 Figure 13: Power ...........................................................................................................................................................................................19 Figure 14: Frame Rates ................................................................................................................................................................................19 Figure 15: Overclock Regions of Interest ...............................................................................................................................................21 Figure 16: Test Sub Regions of Interest ..................................................................................................................................................24 Figure 17: Clock Line Capacitances ..........................................................................................................................................................27 Figure 18: Progressive Scan Operation ...................................................................................................................................................29 Figure 19: Progressive Scan Flow Chart ..................................................................................................................................................29 Figure 20: Framing Timing without Binning ...........................................................................................................................................30 Figure 21: Frame Timing for Vertical Binning by 2 ...............................................................................................................................30 Figure 22: Frame Timing Edge Alignment ..............................................................................................................................................31 Figure 23: Line Timing Single Output ......................................................................................................................................................32 Figure 24: Line Timing Dual Output .........................................................................................................................................................32 Figure 25: Line Timing Vertical Binning by 2 ..........................................................................................................................................33 Figure 26: Line Timing Detail .....................................................................................................................................................................33 Figure 27: Line Timing by 2 Detail ............................................................................................................................................................34 Figure 28: Line Timing Edge Alignment ..................................................................................................................................................34 Figure 29: Pixel Timing ................................................................................................................................................................................35 Figure 30: Pixel Timing Detail ....................................................................................................................................................................35 Figure 31: Fast Line Dump Timing ............................................................................................................................................................36 Figure 32: Electronic Shutter Line Timing ..............................................................................................................................................37 Figure 33: Integration Time Definition ....................................................................................................................................................37 Figure 34: Completed Assembly ...............................................................................................................................................................41 Figure 35: Die to Package Alignment ......................................................................................................................................................42 Figure 36: Glass Drawing.............................................................................................................................................................................43 Figure 37: Glass Transmission ....................................................................................................................................................................44 www.truesenseimaging.com Revision 1.0 PS-0018 Pg 4 KAI-2001 Image Sensor Summary Specification KAI-2001 Image Sensor DESCRIPTION The KAI-2001 Image Sensor is a high-performance 2million pixel sensor designed for a wide range of medical, scientific and machine vision applications. The 7.4 m square pixels with microlenses provide high sensitivity and the large full well capacity results in high dynamic range. The split horizontal register offers a choice of single or dual output allowing either 15 or 30 frame per second (fps) video rate for the progressively scanned images. Also included is a fast line dump for sub-sampling at higher frame rates. The vertical overflow drain structure provides antiblooming protection and enables electronic shuttering for precise exposure control. Other features include low dark current, negligible lag and low smear. FEATURES Parameter Value Architecture Interline CCD; Progressive Scan Total Number of Pixels 1640 (H) x 1214 (V) Number of Effective Pixels 1608 (H) x 1208 (V) Number of Active Pixels 1600 (H) x 1200 (V) Pixel Size 7.4 m (H) x 7.4 m (V) Imager Size 14.803mm (diagonal) Chip Size 13.38mm (H) x 9.52mm (V) Aspect Ratio 4:3 Number of Outputs 1 or 2 High resolution High sensitivity Saturation Signal 40,000 e- High dynamic range Output Sensitivity 16 V/e Low noise architecture High frame rate Quantum Efficiency -ABA -CBA (BGR) 55% 45%, 42%, 35% Binning capability for higher frame rate Total System Noise 40MHZ 20MHz 40 e23 e- Electronic shutter Dark Current < 0.5 nA/cm2 Dark Current Doubling Temperature 7 C Dynamic Range 60 dB Charge Transfer Efficiency > 0.99999 Blooming Suppression 300X Smear 80 dB Image Lag <10 e- APPLICATIONS Machine Vision Scientific Maximum Data Rate 40 MHz All parameters above are specified at T = 40 C www.truesenseimaging.com Revision 1.0 PS-0018 Pg 5 KAI-2001 Image Sensor Ordering Information Catalog Number Product Name 4H0309 KAI-2001-AAA-CR-BA Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Standard Grade 4H0310 KAI-2001-AAA-CR-AE Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR coating (2 sides), Engineering Sample 4H0318 KAI-2001-AAA-CF-BA Monochrome, No Microlens, CERDIP Package (sidebrazed), Quartz Cover Glass (no coatings), Standard Grade 4H0319 KAI- 2001-AAA-CF-AE Monochrome, No Microlens, CERDIP Package (sidebrazed), Quartz Cover Glass (no coatings), Engineering Sample 4H0312 KAI-2001-CBA-CD-BA Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Standard Grade 4H0313 KAI-2001-CBA-CD-AE Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Engineering Sample 4H0315 KAI-2001-ABA-CD-BA Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Standard Grade 4H0316 KAI-2001-ABA-CD-AE Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR coating (both sides), Engineering Sample 4H0354 KAI-2001-ABA-CP-BA Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass, no coatings, Standard Grade 4H0355 KAI-2001-ABA-CP-AE Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass, no coatings, Engineering Sample 4H0691 KEK-4H0691-KAI-2001/2020-12-20 Evaluation Board, 12 Bit, 20 MHz (Complete Kit) 4H0692 KEK-4H0692-KAI-2001/2020-10-40 Evaluation Board, 10 Bit, 40 MHz (Complete Kit) Description Marking Code KAI-2001 S/N KAI-2001CM S/N KAI-2001M S/N N/A See Application Note Product Naming Convention for a full description of the naming convention used for Truesense Imaging image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.truesenseimaging.com. Please address all inquiries and purchase orders to: Truesense Imaging, Inc. 1964 Lake Avenue Rochester, New York 14615 Phone: (585) 784-5500 E-mail: info@truesenseimaging.com Truesense Imaging reserves the right to change any information contained herein without notice. All information furnished by Truesense Imaging is believed to be accurate. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 6 KAI-2001 Image Sensor Device Description ARCHITECTURE 4 Dark Rows Single or Dual Output Pixel 1,1 16 Dark Columns 4 Buffer Columns 4 Buffer Columns 4Buffer Rows 1600 (H) x 1200 (H) Active Pixels 4 Dummy Pixels Video L 4 Dummy Pixels 16 Dark Columns 4 Buffer Rows B G G R 4 Buffer Rows 2 Dark Rows 4 16 4 4 16 4 1600 800 800 4 16 4 4 16 4 Video R Figure 1: Sensor Architecture There are 2 light shielded rows followed 1208 photoactive rows and finally 4 more light shielded rows. The first 4 and the last 4 photoactive rows are buffer rows giving a total of 1200 lines of image data. In the single output mode all pixels are clocked out of the Video L output in the lower left corner of the sensor. The first 4 empty pixels of each line do not receive charge from the vertical shift register. The next 16 pixels receive charge from the left light shielded edge followed by 1608 photosensitive pixels and finally 16 more light shielded pixels from the right edge of the sensor. The first and last 4 photosensitive pixels are buffer pixels giving a total of 1600 pixels of image data. In the dual output mode the clocking of the right half of the horizontal CCD is reversed. The left half of the image is clocked out Video L and the right half of the image is clocked out Video R. Each row consists of 4 empty pixels followed by 16 light shielded pixels followed by 800 photosensitive pixels. When reconstructing the image, data from Video R will have to be reversed in a line buffer and appended to the Video L data. There are 4 dark reference rows at the top and 2 dark rows at the bottom of the image sensor. The dark rows are not entirely dark and so should not be used for a dark reference level. Use the 16 dark columns on the left or right side of the image sensor as a dark reference. Of the 16 dark columns, the first and last dark columns should not be used for determining the zero signal level. Some light does leak into the first and last dark columns. Only use the center 14 columns of the 16 column dark reference. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 7 KAI-2001 Image Sensor PIXEL Top View Cross Section Down Through VCCD Direction of Charge Transfer V1 V1 V2 V1 7.4 m Photodiode Transfer Gate n- V2 n- Direction of Charge Transfer nn p Well (GND) 7.4 m n Substrate True Two Phase Burried Channel VCCD Lightshield over VCCD not shown Cross Section Through Photodiode and VCCD Phase 2 at Transfer Gate Cross Section Through Photodiode and VCCD Phase 1 Photo diode p p+ n Light Shield p n p Light Shield Transfer Gate V1 p V2 p+ n p n p p p n Substrate n Substrate p Cross Section Showing Lenslet Drawings not scale Lenslet Red Color Filter Light Shield VCCD Light Shield VCCD Photodiode Figure 2: Pixel Architecture An electronic representation of an image is formed when incident photons falling on the sensor plane create electronhole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 8 KAI-2001 Image Sensor VERTICAL TO HORIZONTAL TRANSFER Direction of Vertical Charge Transfer Top View V1 Photo diode Transfer Gate V2 V1 Fast Line Dump V2 Lightshield not shown H H2 1 S B H 2 B H1S Direction of Horizontal Charge Transfer Figure 3: Vertical to Horizontal Transfer Architecture When the V1 and V2 timing inputs are pulsed, charge in every pixel of the VCCD is shifted one row towards the HCCD. The last row next to the HCCD is shifted into the HCCD. When the VCCD is shifted, the timing signals to the HCCD must be stopped. H1 must be stopped in the high state and H2 must be stopped in the low state. The HCCD clocking may begin THD s after the falling edge of the V1 and V2 pulse. Charge is transferred from the last vertical CCD phase into the H1S horizontal CCD phase. Refer to Figure 26 for an example of timing that accomplishes the vertical to horizontal transfer of charge. If the fast line dump is held at the high level (FDH) during a vertical to horizontal transfer, then the entire line is removed and not transferred into the horizontal register. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 9 KAI-2001 Image Sensor HORIZONTAL REGISTER TO FLOATING DIFFUSION RD R n+ n OG H2B H1S n- n+ H1B n- H2S H2B n- H1S H1B n- n (burried channel) Floating Diffusion p (GND) n (SUB) Figure 4: Horizontal Register to Floating Diffusion Architecture The HCCD has a total of 1648 pixels. The 1640 vertical shift registers (columns) are shifted into the center 1640 pixels of the HCCD. There are 4 pixels at both ends of the HCCD, which receive no charge from a vertical shift register. The first 4 clock cycles of the HCCD will be empty pixels (containing no electrons). The next 16 clock cycles will contain only electrons generated by dark current in the VCCD and photodiodes. The next 1608 clock cycles will contain photoelectrons (image data). Finally, the last 16 clock cycles will contain only electrons generated by dark current in the VCCD and photodiodes. Of the 16 dark columns, the first and last dark columns should not be used for determining the zero signal level. Some light does leak into the first and last dark columns. Only use the center 14 columns of the 16 column dark reference. When the HCCD is shifting valid image data, the timing inputs to the electronic shutter (SUB), VCCD (V1, V2), and fast line dump (FD) should be not be pulsed. This prevents unwanted noise from being introduced. The HCCD is a type of charge coupled device known as a pseudo-two phase CCD. This type of CCD has the ability to shift charge in two directions. This allows the entire image to be shifted out to the video L output, or to the video R output (left/right image reversal). The HCCD is split into two equal halves of 824 pixels each. When operating the sensor in single output mode the two halves of the HCCD are shifted in the same direction. When operating the sensor in dual output mode the two halves of the HCCD are shifted in opposite directions. The direction of charge transfer in each half is controlled by the H1BL, H2BL, H1BR, and H2BR timing inputs. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 10 KAI-2001 Image Sensor HORIZONTAL REGISTER SPLIT H1 H2 H2 H1 H1 H2 H2 H1 H1 H2 H1BL H2SL H2BL H1SL H1BL H2SL H1BR H1SR H2BR H2SR Pixel 824 Pixel 825 Single Output H1 H2 H2 H1 H1 H2 H1 H1 H2 H2 H1BL H2SL H2BL H1SL H1BL H2SL H1BR H1SR H2BR H2SR Pixel 824 Pixel 825 Dual Output Figure 5: Horizontal Register Single Output Operation When operating the sensor in single output mode all pixels of the image sensor will be shifted out the Video L output (pin 31). To conserve power and lower heat generation the output amplifier for Video R may be turned off by connecting VDDR (pin 24) and VOUTR (pin 24) to GND (zero volts). The H1 timing from the timing diagrams should be applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing should be applied to H2SL, H2BL, H2SR, and H1BR. In other words, the clock driver generating the H1 timing should be connected to pins 4, 3, 13, and 15. The clock driver generating the H2 timing should be connected to pins 5, 2, 12, and 14. The horizontal CCD should be clocked for 4 empty pixels plus 16 light shielded pixels plus 1608 photoactive pixels plus 16 light shielded pixels for a total of 1644 pixels. Dual Output Operation In dual output mode the connections to the H1BR and H2BR pins are swapped from the single output mode to change the direction of charge transfer of the right side horizontal shift register. In dual output mode both VDDL and VDDR (pins 25, 24) should be connected to 15 V. The H1 timing from the timing diagrams should be applied to H1SL, H1BL, H1SR, H1BR, and the H2 timing should be applied to H2SL, H2BL, H2SR, and H2BR. The clock driver generating the H1 timing should be connected to pins 4, 3, 13, and 14. The clock driver generating the H2 timing should be connected to pins 5, 2, 12, and 15. The horizontal CCD should be clocked for 4 empty pixels plus 16 light shielded pixels plus 804 photoactive pixels for a total of 824 pixels. If the camera is to have the option of dual or single output mode, the clock driver signals sent to H1BR and H2BR may be swapped by using a relay. Another alternative is to have two extra clock drivers for H1BR and H2BR and invert the signals in the timing logic generator. If two extra clock drivers are used, care must be taken to ensure the rising and falling edges of the H1BR and H2BR clocks occur at the same time (within 3 ns) as the other HCCD clocks. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 11 KAI-2001 Image Sensor OUTPUT H1S HCCD Charge Transfer H2B H2S H1B H1S H2B VDD OG R RD VDD Floating Diffusion VSS VOUT Source Follower #1 Source Follower #2 Source Follower #3 Figure 6: Output Architecture Charge packets contained in the horizontal register are dumped pixel by pixel onto the floating diffusion (fd) output node whose potential varies linearly with the quantity of charge in each packet. The amount of potential charge is determined by the expression Vfd=Q/Cfd. A three-stage source-follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. The translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of microvolts per electron (V/e-). After the signal has been sampled off chip, the reset clock (R) removes the charge from the floating diffusion and resets its potential to the reset drain voltage (RD). When the image sensor is operated in the binned or summed interlaced modes there will be more than 40,000 electrons in the output signal. The image sensor is designed with a 16 V/e charge to voltage conversion on the output. This means a full signal of 40,000 electrons will produce a 640 mV change on the output amplifier. The output amplifier was designed to handle an output swing of 640 mV at a pixel rate of 40 MHz. If 80,000 electron charge packets are generated in the binned or summed interlaced modes then the output amplifier output will have to swing 1280 mV. The output amplifier does not have enough bandwidth (slew rate) to handle 1280 mV at 40 MHz. Hence, the pixel rate will have to be reduced to 20 MHz if the full dynamic range of 80,000 electrons is desired. The charge handling capacity of the output amplifier is also set by the reset clock voltage levels. The reset clock driver circuit is very simple if an amplitude of 5 V is used. But the 5 V amplitude restricts the output amplifier charge capacity to 40,000 electrons. If the full dynamic range of 80,000 electrons is desired then the reset clock amplitude will have to be increased to 7 V. If you only want a maximum signal of 40,000 electrons in binned or summed interlaced modes, then a 40 MHz pixel rate with a 5 V reset clock may be used. The output of the amplifier will be unpredictable above 40,000 electrons so be sure to set the maximum input signal level of your analog to digital converter to the equivalent of 40,000 electrons (640 mV). www.truesenseimaging.com Revision 1.0 PS-0018 Pg 12 KAI-2001 Image Sensor VSS VOUTR GND V2 V1 VSUB GND VDDR VDDL GND VSUB V1 V2 ESD VSS VOUTL PIN DESCRIPTION AND PHYSICAL ORIENTATION 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 8 9 10 11 12 13 14 15 16 H2BL H1BL H1SL H2SL GND OGL RDL RDR RR 7 H2BR 6 H1BR 5 H1SR 4 H2SR 3 FD 2 OGR 1 RL Pixel 1,1 Figure 7: Package Pin Designations - Top View Pin Name Description Pin Name Description 1 RL Reset Gate, Left 32 VSS Output Amplifier Return 2 H2BL H2 Barrier, Left 31 VOUTL Video Output, Left 3 H1BL H1 Barrier, Left 30 ESD ESD 4 H1SL H1 Storage, Left 29 V2 Vertical Clock, Phase 2 5 H2SL H2 Storage, Left 28 V1 Vertical Clock, Phase 1 6 GND Ground 27 VSUB Substrate 7 OGL Output Gate, Left 26 GND Ground 8 RDL Reset Drain, Left 25 VDDL Vdd, Left 9 RDR Reset Drain, Right 24 VDDR Vdd, Right 10 OGR Output Gate, Right 23 GND Ground 11 FD Fast Line Dump Gate 22 VSUB Substrate 12 H2SR H2 Storage, Right 21 V1 Vertical Clock, Phase 1 13 H1SR H1 Storage, Right 20 V2 Vertical Clock, Phase 2 14 H1BR H1 Barrier, Right 19 GND Ground 15 H2BR H2 Barrier, Right 18 VOUTR Video Output, Right 16 RR Reset Gate, Right 17 VSS Output Amplifier Return The pins are on a 0.070" spacing www.truesenseimaging.com Revision 1.0 PS-0018 Pg 13 KAI-2001 Image Sensor Imaging Performance TYPICAL OPERATIONAL CONDITIONS Unless otherwise noted, Imaging Performance Specifications are measured using the following conditions. Description Condition Frame Time 237 msec Horizontal Clock Frequency 10 MHz Light Source Continuous red, green and blue illumination centered at 450, 530 and 650 nm Operation Nominal operating voltages and timing Notes: 1. 2. 3. Notes 1 2,3 Electronic shutter is not used. Integration time equals frame time. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP-8115. For monochrome sensor, only green LED used. SPECIFICATIONS All Configurations Min. Nom. Max. Units Sampling Plan Temperature Tested At (C) Dark Center Uniformity n/a n/a 20 e-rms Die 27, 40 Dark Global Uniformity n/a n/a 5.0 mVpp Die 27, 40 Global Uniformity n/a 2.5 5.0 %rms Die 27, 40 1 n/a 10 20 %pp Die 27, 40 1 n/a 1.0 2.0 %rms Die 27, 40 NL n/a 2 % Design 2,3 Maximum Gain Difference Between Outputs G n/a 10 % Design 2,3 Max. Signal Error due to Nonlinearity Dif. NL n/a 1 % Design 2,3 Horizontal CCD Charge Capacity Hne n/a 100 n/a ke- Design Vertical CCD Charge Capacity VNe n/a 50 n/a ke- Die Photodiode Charge Capacity PNe 38 40 n/a ke- Horizontal CCD Charge Transfer Efficiency HCTE 0.99999 n/a n/a Vertical CCD Charge Transfer Efficiency Description Global Peak to Peak Uniformity Symbol PRNU Center Uniformity Maximum Photoresponse Nonlinearity 1 Die Design VCTE 0.99999 n/a n/a Photodiode Dark Current Ipd n/a 40 350 e/p/s Die Photodiode Dark Current Ipd n/a 0.01 0.1 nA/cm2 Die Vertical CCD Dark Current Ivd n/a 400 1711 e/p/s Die Vertical CCD Dark Current Ivd n/a 0.12 0.5 nA/cm2 Die Image Lag Lag n/a <10 50 e- Design Antiblooming Factor Xab 100 300 n/a Vertical Smear Smr n/a 80 75 Total Noise ne-T Total Noise Dynamic Range Design Design dB Design 23 e-rms Design ne-T 40 e-rms Design 6 DR 60 dB Design 6,7 Output Amplifier DC Offset Vodc Output Amplifier Bandwidth F-3db Output Amplifier Impedance ROUT Output Amplifier Sensitivity V/N www.truesenseimaging.com Notes 4 8.5 14 140 100 130 16 200 V Die MHz Design Ohms Die V/e- Design 5 Revision 1.0 PS-0018 Pg 14 KAI-2001 Image Sensor KAI-2001-ABA Configuration Symbol Min. Nom. Max. Units Sampling Plan Peak Quantum Efficiency QEmax 45 55 n/a % Design Peak Quantum Efficiency Wavelength QE n/a 500 n/a nm Design Min. Nom. Max. Units Sampling Plan 45 42 35 n/a % Design n/a nm Design Description Temperature Tested At (C) Notes Temperature Tested At (C) Notes KAI-2001-CBA Configuration Description Symbol Peak Quantum Efficiency Blue Green Red Peak Quantum Efficiency Wavelength Blue Green Red QEmax QE n/a 470 540 620 n/a: not applicable Notes: 1. 2. 3. 4. 5. 6. Per color. Value is over the range of 10% to 90% of photodiode saturation. Value is for the sensor operated without binning Includes system electronics noise, dark pattern noise and dark current shot noise at 20 MHz. Includes system electronics noise, dark pattern noise and dark current shot noise at 40 MHz. Uses 20LOG(PNe/ne-T) www.truesenseimaging.com Revision 1.0 PS-0018 Pg 15 KAI-2001 Image Sensor Typical Performance Curves QUANTUM EFFICIENCY Monochrome with Microlens 0.6 0.5 Measured with glass 0.4 Absolute Quantum Efficiency 0.3 0.2 0.1 0.0 400 500 600 700 800 900 1000 Wavelength (nm) Figure 8: Monochrome with Microlens Quantum Efficiency Monochrome without Microlens Absolute Quantum Efficiency 0.12 0.10 0.08 0.06 0.04 0.02 0.00 240 340 440 540 640 740 840 940 Wavelength (nm) Figure 9: Monochrome without Microlens Quantum Efficiency www.truesenseimaging.com Revision 1.0 PS-0018 Pg 16 KAI-2001 Image Sensor Absolute Quantum Efficiency Color (Bayer RGB) with Microlens 0.50 0.45 0.40 0.35 0.30 Measured with glass 0.25 0.20 0.15 0.10 0.05 0.00 400 500 600 700 800 900 1000 Wavelength (nm) Red Green Blue Figure 10: Color Quantum Efficiency www.truesenseimaging.com Revision 1.0 PS-0018 Pg 17 KAI-2001 Image Sensor ANGULAR QUANTUM EFFICIENCY For the curves marked "Horizontal", the incident light angle is varied in a plane parallel to the HCCD. For the curves marked "Vertical", the incident light angle is varied in a plane parallel to the VCCD. Monochrome with Microlens 100 90 Vertical 80 70 Relative 60 Quantum 50 Efficiency 40 (% ) 30 Horizontal 20 10 0 0 5 10 15 20 25 30 Angle (degrees) Figure 11: Angular Quantum Efficiency DARK CURRENT VERSUS TEMPERATURE 100000 Electrons/second 10000 VCCD 1000 100 Photodiodes 10 1 1000/T(K) 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 T (C) 97 84 72 60 50 40 30 21 Figure 12: Dark Current versus Temperature www.truesenseimaging.com Revision 1.0 PS-0018 Pg 18 KAI-2001 Image Sensor POWER - ESTIMATED Right Output Disabled 500 450 400 Power (mW) 350 300 250 200 150 100 50 0 0 5 10 15 20 25 30 35 40 Horizontal Clock Frequency (MHz) Output Pow er One Output(mW) Horizontal Pow er (mW) Vertical Pow er One Output(mW) Total Pow er One Output (mW) Figure 13: Power FRAME RATES 70 Dual 2x2 binning 60 Frame Rate (fps) 50 Dual output or Single 2x2 binning 40 30 20 Single output 10 0 10 15 20 25 30 35 40 Pixel Clock (MHz) Figure 14: Frame Rates www.truesenseimaging.com Revision 1.0 PS-0018 Pg 19 KAI-2001 Image Sensor Defect Definitions Description Definition Major dark field defective pixel Maximum Temperature(s) tested at (C) 20 27, 40 Defect 179 mV Major bright field defective pixel 1 Defect 15 % Minor dark field defective pixel Notes 1 Defect 57 mV 200 27, 40 Cluster defect A group of 2 to 10 contiguous major defective pixels, but no more than 2 adjacent defects horizontally 8 27, 40 1 Column defect A group of more than 10 contiguous major defective pixels along a single column 0 27, 40 1 Notes: 1. There will be at least two non-defective pixels separating any two major defective pixels. DEFECT MAP The defect map supplied with each sensor is based upon testing at an ambient (27 C) temperature. Minor point defects are not included in the defect map. All defective pixels are reference to pixel 1, 1 in the defect maps. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 20 KAI-2001 Image Sensor Test Definitions TEST REGIONS OF INTEREST Active Area ROI: Pixel (1, 1) to Pixel (1600, 1200) Center 100 by 100 ROI: Pixel (750, 550) to Pixel (849, 649) Only the active pixels are used for performance and defect tests. OVERCLOCKING The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. See Figure 15 for a pictorial representation of the regions. Horizontal Overclock Pixel 1,1 Vertical Overclock Figure 15: Overclock Regions of Interest www.truesenseimaging.com Revision 1.0 PS-0018 Pg 21 KAI-2001 Image Sensor TESTS Dark Field Center Non-Uniformity This test is performed under dark field conditions. Only the center 100 by 100 pixels of the sensor are used for this test - pixel (750, 550) to pixel (849, 649). ( ) Units: mV rms. DPS integration time: Device Performance Specification Integration Time = 33 msec. Dark Field Global Non-Uniformity This test is performed under dark field conditions. The sensor is partitioned into 192 sub regions of interest, each of which is 100 by 100 pixels in size. See Figure 16. The average signal level of each of the 192 sub regions of interest is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Signal of ROI[i] = (ROI Average in ADU - Horizontal overclock average in ADU) * mV per count Where i = 1 to 192. During this calculation on the 192 sub regions of interest, the maximum and minimum signal levels are found. The dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. Units: mVpp (millivolts peak to peak) Global Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 80% of saturation (approximately 32,000 electrons). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 40,000 electrons. Global uniformity is defined as Active Area Standard Deviation Global Uniformit y 100 * Active Area Signal Units: %rms. Active Area Signal = Active Area Average - Horizontal Overclock Average. Global Peak to Peak Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 80% of saturation (approximately 32,000 electrons). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 40,000 electrons. The sensor is partitioned into 192 sub regions of interest, each of which is 100 by 100 pixels in size. See Figure 16. The average signal level of each of the 192 sub regions of interest (ROI) is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Signal of ROI[i] = (ROI Average in ADU - Horizontal overclock average in ADU) * mV per count Where i = 1 to 192. During this calculation on the 192 sub regions of interest, the maximum and minimum signal levels are found. The global peak to peak uniformity is then calculated as: Global Uniformity Maximum Signal - Minimum Signal Active Area Signal Units: %pp www.truesenseimaging.com Revision 1.0 PS-0018 Pg 22 KAI-2001 Image Sensor Center Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 80% of saturation (approximately 32,000 electrons). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 40,000 electrons. Defects are excluded for the calculation of this test. This test is performed on the center 100 by 100 pixels of the sensor (see Figure 16). Center uniformity is defined as: Center ROI Standard Deviation Center ROI Uniformity 100 * Center ROI Signal Units: %rms. Center ROI Signal = Center ROI Average - Horizontal Overclock Average. Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 192 sub regions of interest, each of which is 100 by 100 pixels in size (see Figure 16). In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in "Defect Definitions" section. Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at 80% of saturation (approximately 32,000 electrons). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 40,000 electrons. The average signal level of all active pixels is found. The bright and dark thresholds are set as: Dark defect threshold = Active Area Signal * threshold Bright defect threshold = Active Area Signal * threshold The sensor is then partitioned into 192 sub regions of interest, each of which is 100 by 100 pixels in size (see Figure 16). In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. Example for major bright field defective pixels: Average value of all active pixels is found to be 416 mV (32,000 electrons). Dark defect threshold: 416mV * 15% = 62.4 mV Bright defect threshold: 416mV * 15% = 62.4 mV Region of interest #1 selected. This region of interest is pixels 1, 1 to pixels 100, 100. o Median of this region of interest is found to be 416 mV. o Any pixel in this region of interest that is (416+62.4 mV) 478.4 mV in intensity will be marked defective. o Any pixel in this region of interest that is (416-62.4 mV) 353.6 mV in intensity will be marked defective. All remaining 191 sub regions of interest are analyzed for defective pixels in the same manner. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 23 KAI-2001 Image Sensor Test Sub Regions of Interest Pixel (1,1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 Pixel (1600,1200) Figure 16: Test Sub Regions of Interest www.truesenseimaging.com Revision 1.0 PS-0018 Pg 24 KAI-2001 Image Sensor Operation MAXIMUM RATINGS Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or the condition is exceeded, the device will be degraded and may be damaged. Description Symbol Minimum Maximum Units Notes Operating Temperature TOP -50 70 C 1 Humidity RH 5 90 % 2 Output Bias Current Iout 0.0 10 mA 3 10 pF 4 Off-chip Load Notes: 1. 2. 3. 4. CL Noise performance will degrade at higher temperatures. T=25 C. Excessive humidity will degrade MTTF. Total for both outputs. Current is 5 mA for each output. Note that the current bias affects the amplifier bandwidth. With total output load capacitance of CL = 10 pF between the outputs and AC ground. MAXIMUM VOLTAGE RATINGS BETWEEN PINS Description RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGR, OGL to ESD Pin to Pin with ESD Protection VDDL, VDDR to GND Notes: 1. Minimum Maximum Units 0 17 V -17 17 V 0 25 V Notes 1 Pins with ESD protection are: RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGL, and OGR. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 25 KAI-2001 Image Sensor DC BIAS OPERATING CONDITIONS Maximum Units Maximum DC Current (mA) -2.5 -2.0 V 1 A 12.0 12.5 V 1 A 15.0 15.5 V 1 mA 0.0 0.0 0.0 V SUB 8.0 Vab 17.0 V 2, 4 ESD -8.0 -7.0 -6.0 V 3 VSS 0.0 0.7 1.0 V Description Symbol Output Gate OG -3.0 Reset Drain RD 11.5 Output Amplifier Supply VDD 14.5 Ground GND Substrate ESD Protection Output Amplifier Return Notes: 1. 2. 3. 4. Minimum Nominal Notes 1 The operating value of the substrate voltage, Vab, will be marked on the shipping container for each device. The value Vab is set such that the photodiode charge capacity is 40,000 electrons. VESD must be at least 1 Volt more negative than H1L, H2L and RL during sensors operation AND during camera power turn on. One output, unloaded Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 26 KAI-2001 Image Sensor AC OPERATING CONDITIONS Clock Levels Description Vertical CCD Clock High Vertical CCD Clocks Midlevel Symbol Minimum Nominal Maximum Units V2H 7.5 8.0 8.5 V V1M, V2M -0.2 0.0 0.2 V Vertical CCD Clocks Low V1L, V2L -9.5 -9.0 -8.5 V Horizontal CCD Clocks Amplitude H1H, H2H 4.5 5.0 5.5 V Horizontal CCD Clocks Low H1L, H2L -5.0 -4.0 -3.8 V Reset Clock Amplitude RH V 1 Reset Clock Low RL -4.0 -3.5 -3.0 V 2 Vshutter 44 48 52 V 3 Fast Dump High FDH 4.8 5.0 5.2 V Fast Dump Low FDL -9.5 -9 -8 V Electronic Shutter Voltage Notes: 1. 2. 3. 5.0 Notes Reset amplitude must be set to 7.0 V for 80,000 electrons output in summed interlaced or binning modes. Reset low level must be set to -5.0 V for 80,000 electrons output in summed interlaced or binning modes. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. Clock Line Capacitances V1 H1SL+H1BL 25nF 66pF 5nF 20pF V2 H2SL+H2BL 25nF 58pF H1SR+H1BR 66pF GND 20pF H2SR+H2BR 58pF GND Reset SUB FD 10pF GND 2nF GND 21pF GND Figure 17: Clock Line Capacitances www.truesenseimaging.com Revision 1.0 PS-0018 Pg 27 KAI-2001 Image Sensor TIMING REQUIREMENTS Description Symbol Minimum Nominal Maximum Units THD 1.3 1.5 10.0 s VCCD Transfer time TVCCD 1.3 1.5 20.0 s Photodiode Transfer time TV3rd 8.0 12.0 15.0 s VCCD Pedestal time T3P 20.0 25.0 50.0 s VCCD Delay T3D 15.0 20.0 100.0 s Reset Pulse time TR 5.0 10.0 Shutter Pulse time TS 3.0 5.0 10.0 s Shutter Pulse delay TSD 1.0 1.6 10.0 s HCCD Clock Period TH 25.0 50.0 200.0 ns VCCD rise/fall time TVR 0.0 0.1 1.0 s Fast Dump Gate delay TFD 0.0 0.0 0.5 s Vertical Clock Edge Alignment TVE 0.0 100.0 ns HCCD Delay www.truesenseimaging.com Notes ns Revision 1.0 PS-0018 Pg 28 KAI-2001 Image Sensor TIMING MODES Progressive Scan photodiode CCD shift register 7 6 5 4 3 2 1 0 output HCCD Figure 18: Progressive Scan Operation In progressive scan read out every pixel in the image sensor is read out simultaneously. Each charge packet is transferred from the photodiode to the neighboring vertical CCD shift register simultaneously. The maximum useful signal output is limited by the photodiode charge capacity to 40,000 electrons. Vertical Frame Timing Line Timing Repeat for 1214 Lines Figure 19: Progressive Scan Flow Chart www.truesenseimaging.com Revision 1.0 PS-0018 Pg 29 KAI-2001 Image Sensor FRAME TIMING Frame Timing without Binning - Progressive Scan V1 TL TV3rd TL V2 T3P Line 1213 T3D Line 1214 Line 1 H1 H2 Figure 20: Framing Timing without Binning Frame Timing for Vertical Binning by 2 - Progressive Scan V1 TL TV3rd TL 3 x TVCCD V2 T3P Line 606 T3D Line 607 Line 1 H1 H2 Figure 21: Frame Timing for Vertical Binning by 2 www.truesenseimaging.com Revision 1.0 PS-0018 Pg 30 KAI-2001 Image Sensor Frame Timing Edge Alignment V1M V1 V1L V2H V2M V2 TVE V2L Figure 22: Frame Timing Edge Alignment www.truesenseimaging.com Revision 1.0 PS-0018 Pg 31 KAI-2001 Image Sensor LINE TIMING Line Timing Single Output - Progressive Scan TL V1 TVCCD V2 THD H1 H2 1642 1643 1644 1625 1626 1627 1628 1629 1630 19 20 21 22 23 24 pixel count 1 2 3 4 5 6 7 R Figure 23: Line Timing Single Output Line Timing Dual Output - Progressive Scan TL V1 TVCCD V2 THD H1 H2 816 817 818 819 820 821 822 823 824 825 19 20 21 22 23 24 pixel count 1 2 3 4 5 6 7 R Figure 24: Line Timing Dual Output www.truesenseimaging.com Revision 1.0 PS-0018 Pg 32 KAI-2001 Image Sensor Line Timing Vertical Binning by 2 - Progressive Scan TL V1 3 x TVCCD V2 THD H1 H2 1642 1643 1644 1625 1626 1627 1628 1629 1630 19 20 21 22 23 24 pixel count 1 2 3 4 5 6 7 R Figure 25: Line Timing Vertical Binning by 2 Line Timing Detail - Progressive Scan V1 TVCCD V2 1/2 TH THD H1 H2 R Figure 26: Line Timing Detail www.truesenseimaging.com Revision 1.0 PS-0018 Pg 33 KAI-2001 Image Sensor Line Timing Binning by 2 Detail - Progressive Scan V1 V2 1/2 TH TVCCD TVCCD TVCCD THD H1 H2 R Figure 27: Line Timing by 2 Detail Line Timing Edge Alignment Applies to all modes. TVCCD V1 V2 TVE TVE Figure 28: Line Timing Edge Alignment www.truesenseimaging.com Revision 1.0 PS-0018 Pg 34 KAI-2001 Image Sensor PIXEL TIMING V1 V2 H1 H2 Pixel Count 1 2 3 4 5 19 20 21 R Vout Dummy Pixels Light Shielded Pixels Photosensitive Pixels Figure 29: Pixel Timing Pixel Timing Detail TR R RH RL H1H H1 H1L H2H H2 H2L VOUT Figure 30: Pixel Timing Detail www.truesenseimaging.com Revision 1.0 PS-0018 Pg 35 KAI-2001 Image Sensor FAST LINE DUMP TIMING FD V1 V2 TFD TVCCD TFD TVCCD H1 H2 Figure 31: Fast Line Dump Timing www.truesenseimaging.com Revision 1.0 PS-0018 Pg 36 KAI-2001 Image Sensor ELECTRONIC SHUTTER Electronic Shutter Line Timing V1 V2 TVCCD THD VShutter TS VSUB TSD H1 H2 R Figure 32: Electronic Shutter Line Timing Electronic Shutter - Integration Time Definition V2 Integration Time VShutter VSUB Figure 33: Integration Time Definition Electronic Shutter - DC and AC Bias Definition The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. VShutter VSUB GND www.truesenseimaging.com GND Revision 1.0 PS-0018 Pg 37 KAI-2001 Image Sensor Electronic Shutter Description The voltage on the substrate (SUB) determines the charge capacity of the photodiodes. When SUB is 8 volts the photodiodes will be at their maximum charge capacity. Increasing VSUB above 8 volts decreases the charge capacity of the photodiodes until 48 volts when the photodiodes have a charge capacity of zero electrons. Therefore, a short pulse on SUB, with a peak amplitude greater than 48 volts, empties all photodiodes and provides the electronic shuttering action. It may appear the optimal substrate voltage setting is 8 volts to obtain the maximum charge capacity and dynamic range. While setting VSUB to 8 volts will provide the maximum dynamic range, it will also provide the minimum antiblooming protection. - The KAI-2001 VCCD has a charge capacity of 55,000 electrons (55 ke ). If the SUB voltage is set such that the photodiode holds more than 55 ke , then when the charge is transferred from a full photodiode to VCCD, the VCCD will overflow. This overflow condition manifests itself in the image by making bright spots appear elongated in the vertical direction. The size increase of a bright spot is called blooming when the spot doubles in size. The blooming can be eliminated by increasing the voltage on SUB to lower the charge capacity of the photodiode. This ensures the VCCD charge capacity is greater than the photodiode capacity. There are cases where an extremely bright spot will still cause blooming in the VCCD. Normally, when the photodiode is full, any additional electrons generated by photons will spill out of the photodiode. The excess electrons are drained harmlessly out to the substrate. There is a maximum rate at which the electrons can be drained to the substrate. If that maximum rate is exceeded, (for example, by a very bright light source) then it is possible for the total amount of charge in the photodiode to exceed the VCCD capacity. This results in blooming. The amount of antiblooming protection also decreases when the integration time is decreased. There is a compromise between photodiode dynamic range (controlled by VSUB) and the amount of antiblooming protection. A low VSUB voltage provides the maximum dynamic range and minimum (or no) antiblooming protection. A high VSUB voltage provides lower dynamic range and maximum antiblooming protection. The optimal setting of VSUB is written on the container in which each KAI-2001 is shipped. The given VSUB voltage for each sensor is selected to provide antiblooming protection for bright spots at least 100 times saturation, while maintaining at least 40 ke- of dynamic range. The electronic shutter provides a method of precisely controlling the image exposure time without any mechanical components. If an integration time of TINT is desired, then the substrate voltage of the sensor is pulsed to at least 40 volts TINT seconds before the photodiode to VCCD transfer pulse on V2. Use of the electronic shutter does not have to wait until the previously acquired image has been completely read out of the VCCD. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 38 KAI-2001 Image Sensor LARGE SIGNAL OUTPUT When the image sensor is operated in the binned or summed interlaced modes there will be more than 40,000 electrons in the output signal. The image sensor is designed with a 16V/e charge to voltage conversion on the output. This means a full signal of 40,000 electrons will produce a 640 mV change on the output amplifier. The output amplifier was designed to handle an output swing of 640 mV at a pixel rate of 40 MHz. If 80,000 electron charge packets are generated in the binned or summed interlaced modes then the output amplifier output will have to swing 1280 mV. The output amplifier does not have enough bandwidth (slew rate) to handle 1280 mV at 40 MHz. Hence, the pixel rate will have to be reduced to 20 MHz if the full dynamic range of 80,000 electrons is desired. The charge handling capacity of the output amplifier is also set by the reset clock voltage levels. The reset clock driver circuit is very simple if an amplitude of 5 V is used. But the 5 V amplitude restricts the output amplifier charge capacity to 40,000 electrons. If the full dynamic range of 80,000 electrons is desired then the reset clock amplitude will have to be increased to 7 V. If you only want a maximum signal of 40,000 electrons in binned or summed interlaced modes, then a 40 MHz pixel rate with a 5 V reset clock may be used. The output of the amplifier will be unpredictable above 40,000 electrons so be sure to set the maximum input signal level of your analog to digital converter to the equivalent of 40,000 electrons (640 mV). www.truesenseimaging.com Revision 1.0 PS-0018 Pg 39 KAI-2001 Image Sensor Storage and Handling ENVIRONMENTAL EXPOSURE STORAGE CONDITIONS Description Symbol Minimum Maximum Units Notes Storage Temperature TST -55 80 C 1 Humidity RH 5 90 % 2 Notes: 1. 2. Long-term exposure toward the maximum temperature will accelerate color filter degradation. T=25 C. Excessive humidity will degrade MTTF ESD 1. This device contains limited protection against Electrostatic Discharge (ESD). ESD events may cause irreparable damage to a CCD image sensor either immediately or well after the ESD event occurred. Failure to protect the sensor from electrostatic discharge may affect device performance and reliability. 2. Devices should be handled in accordance with strict ESD procedures for Class 0 (<250V per JESD22 Human Body Model test), or Class A (<200V JESD22 Machine Model test) devices. Devices are shipped in static-safe containers and should only be handled at static-safe workstations. 3. See Application Note Image Sensor Handling Best Practices for proper handling and grounding procedures. This application note also contains workplace recommendations to minimize electrostatic discharge. 4. Store devices in containers made of electroconductive materials. COVER GLASS CARE AND CLEANLINESS 1. The cover glass is highly susceptible to particles and other contamination. Perform all assembly operations in a clean environment. 2. Touching the cover glass must be avoided. 1. Extremely bright light can potentially harm CCD image sensors. Do not expose to strong sunlight for long periods of time, as the color filters and/or microlenses may become discolored. In addition, long time exposures to a static high contrast scene should be avoided. Localized changes in response may occur from color filter/microlens aging. For Interline devices, refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible lighting Conditions. 2. Exposure to temperatures exceeding maximum specified levels should be avoided for storage and operation, as device performance and reliability may be affected. 3. Avoid sudden temperature changes. 4. Exposure to excessive humidity may affect device characteristics and may alter device performance and reliability, and therefore should be avoided. 5. Avoid storage of the product in the presence of dust or corrosive agents or gases, as deterioration of lead solderability may occur. It is advised that the solderability of the device leads be assessed after an extended period of storage, over one year. SOLDERING RECOMMENDATIONS 1. The soldering iron tip temperature is not to exceed 370 C. Higher temperatures may alter device performance and reliability. 2. Flow soldering method is not recommended. Solder dipping can cause damage to the glass and harm the imaging capability of the device. Recommended method is by partial heating using a grounded 30 W soldering iron. Heat each pin for less than 2 seconds duration. 3. Improper cleaning of the cover glass may damage these devices. Refer to Application Note Image Sensor Handling Best Practices. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 40 KAI-2001 Image Sensor Mechanical Drawings COMPLETED ASSEMBLY MARKING CODE Notes: 1. See table for marking code 2. Cover glass is manually placed and visually aligned over die - Location accuracy is not guaranteed DIMENSIONS UNITS: INCH [MM] TOLERANCE: UNLESS OTHERWISE SPECIFIED CERAMIC +/- 1% NO LESS THAN 0.005" L/F +/- 1% NO MORE THAN 0.005" Figure 34: Completed Assembly Configuration Monochrome Monochrome with Lenslets Color with Lenslets www.truesenseimaging.com Marking Code KAI-2001 SN KAI-2001M SN KAI-2001CM SN Revision 1.0 PS-0018 Pg 41 KAI-2001 Image Sensor DIE TO PACKAGE ALIGNMENT Notes: 1. Center of image is offset from center of package by (0.00, 0.00) mm nominal. 2. Die is aligned within +/- 2 degree of any package cavity edge. DIMENSIONS UNITS: IN [MM] TOLERANCES: UNLESS OTHERWISE SPECIFIED CERAMIC +/- 1% NO LESS THAN 0.005" L/F +/- 1% NO MORE THAN 0.005" Figure 35: Die to Package Alignment www.truesenseimaging.com Revision 1.0 PS-0018 Pg 42 KAI-2001 Image Sensor GLASS 4X C 0.020 TYP [C 0.51] EPOXY: NCO-150HB THK.0.002-0.005 8X C 0.002-0.008 TYP [C 0.05-0.20] NOTES: 1. MATERIALS: SUBSTRATE = SCHOTT D263T eco or equivalent EPOXY= NCO-150HB THK= 0.002 - 0.005 2. DUST/SCRATCH COUNT = 10 MICRON MAX 3. DOUBLE SIDED AR COATING REFLECTANCE: 420 - 435 nm < 2.0% 435 - 630 nm < 0.8% 630 - 680 nm < 2.0% UNITS: IN [MM] TOLERANCE: UNLESS OTHERWISE SPECIFIED +/- 1% NO LESS THAN 0.005" Figure 36: Glass Drawing www.truesenseimaging.com Revision 1.0 PS-0018 Pg 43 KAI-2001 Image Sensor GLASS TRANSMISSION 100 90 80 Transmission (%) 70 60 50 40 30 20 10 0 200 300 400 500 600 700 800 900 Wavelength (nm ) Figure 37: Glass Transmission www.truesenseimaging.com Revision 1.0 PS-0018 Pg 44 KAI-2001 Image Sensor Quality Assurance and Reliability QUALITY AND RELIABILITY All image sensors conform to the specifications stated in this document. This is accomplished through a combination of statistical process control and visual inspection and electrical testing at key points of the manufacturing process, using industry standard methods. Information concerning the quality assurance and reliability testing procedures and results are available from Truesense Imaging upon request. For further information refer to Application Note Quality and Reliability. REPLACEMENT All devices are warranted against failure in accordance with the Terms of Sale. Devices that fail due to mechanical and electrical damage caused by the customer will not be replaced. LIABILITY OF THE SUPPLIER A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. Product liability is limited to the cost of the defective item, as defined in the Terms of Sale. LIABILITY OF THE CUSTOMER Damage from mishandling (scratches or breakage), electrostatic discharge (ESD), or other electrical misuse of the device beyond the stated operating or storage limits, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. TEST DATA RETENTION Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for a period of 2 years after date of delivery. MECHANICAL The device assembly drawing is provided as a reference. Truesense Imaging reserves the right to change any information contained herein without notice. All information furnished by Truesense Imaging is believed to be accurate. Life Support Applications Policy Truesense Imaging image sensors are not authorized for and should not be used within Life Support Systems without the specific written consent of Truesense Imaging, Inc. www.truesenseimaging.com Revision 1.0 PS-0018 Pg 45 KAI-2001 Image Sensor Revision Changes MTD/PS-0609 Revision Number Description of Changes 1.0 Initial formal release 1.1 Removed caution for cover glass protective tape. The use of the protective tape has been discontinued. 2.0 Updated format Updated Ordering Information 3.0 Reformatted Ordering Information, Storage and Handling, and Quality Assurance and Reliability pages 4.0 Added the note "Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions" to the following sections o DC Bias Operating Conditions o AC Operating Conditions o Storage and Handling Changed cover glass material to D263T eco or equivalent PS-0018 Revision Number 1.0 Description of Changes Initial release with new document number, updated branding and document template Updated Storage and Handling and Quality Assurance and Reliability sections Reorganized structure for consistency with other Interline Transfer CCD documents www.truesenseimaging.com (c)Truesense Imaging Inc., 2012. TRUESENSE is a registered trademark of Truesense Imaging, Inc. Revision 1.0 PS-0018 Pg 46