KAI-2001 IMAGE SENSOR
1600 (H) X 1200 (V) INTERLINE CCD IMAGE SENSOR
JUNE 22, 2012
DEVICE PERFORMANCE SPECIFICATION
REVISION 1.0 PS-0018
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 2
TABLE OF CONTENTS
Summary Specification ......................................................................................................................................................................................... 5
Description .................................................................................................................................................................................................... 5
Features ......................................................................................................................................................................................................... 5
Applications .................................................................................................................................................................................................. 5
Ordering Information ............................................................................................................................................................................................ 6
Device Description ................................................................................................................................................................................................. 7
Architecture .................................................................................................................................................................................................. 7
Pixel................................................................................................................................................................................................................. 8
Vertical to Horizontal Transfer ................................................................................................................................................................ 9
Horizontal Register to Floating Diffusion .......................................................................................................................................... 10
Horizontal Register Split......................................................................................................................................................................... 11
Single Output Operation .................................................................................................................................................................... 11
Dual Output Operation ....................................................................................................................................................................... 11
Output ......................................................................................................................................................................................................... 12
Pin Description and Physical Orientation ........................................................................................................................................... 13
Imaging Performance .......................................................................................................................................................................................... 14
Typical Operational Conditions............................................................................................................................................................. 14
Specifications............................................................................................................................................................................................. 14
All Configurations ................................................................................................................................................................................ 14
KAI-2001-ABA Configuration ............................................................................................................................................................. 15
KAI-2001-CBA Configuration ............................................................................................................................................................. 15
Typical Performance Curves ............................................................................................................................................................................ 16
Quantum Efficiency.................................................................................................................................................................................. 16
Monochrome with Microlens ............................................................................................................................................................. 16
Monochrome without Microlens ...................................................................................................................................................... 16
Color (Bayer RGB) with Microlens .................................................................................................................................................... 17
Angular Quantum Efficiency .................................................................................................................................................................. 18
Monochrome with Microlens ............................................................................................................................................................. 18
Dark Current versus Temperature ....................................................................................................................................................... 18
Power - Estimated .................................................................................................................................................................................... 19
Frame Rates ............................................................................................................................................................................................... 19
Defect Definitions ................................................................................................................................................................................................ 20
Defect Map ................................................................................................................................................................................................. 20
Test Definitions ..................................................................................................................................................................................................... 21
Test Regions of Interest ......................................................................................................................................................................... 21
OverClocking ............................................................................................................................................................................................. 21
Tests ............................................................................................................................................................................................................. 22
Dark Field Center Non-Uniformity ................................................................................................................................................... 22
Dark Field Global Non-Uniformity .................................................................................................................................................... 22
Global Non-Uniformity ........................................................................................................................................................................ 22
Global Peak to Peak Non-Uniformity............................................................................................................................................... 22
Center Non-Uniformity ....................................................................................................................................................................... 23
Dark Field Defect Test ........................................................................................................................................................................ 23
Bright Field Defect Test ...................................................................................................................................................................... 23
Test Sub Regions of Interest ............................................................................................................................................................. 24
Operation .................................................................................................................................................................................................................. 25
Maximum Ratings ..................................................................................................................................................................................... 25
Maximum Voltage Ratings Between Pins .......................................................................................................................................... 25
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 3
DC Bias Operating Conditions ............................................................................................................................................................... 26
AC Operating Conditions ........................................................................................................................................................................ 27
Clock Levels ........................................................................................................................................................................................... 27
Clock Line Capacitances ...................................................................................................................................................................... 27
Timing Requirements .............................................................................................................................................................................. 28
Timing Modes ............................................................................................................................................................................................ 29
Progressive Scan ................................................................................................................................................................................... 29
Frame Timing ............................................................................................................................................................................................. 30
Frame Timing without Binning – Progressive Scan ...................................................................................................................... 30
Frame Timing for Vertical Binning by 2 – Progressive Scan ....................................................................................................... 30
Frame Timing Edge Alignment .......................................................................................................................................................... 31
Line Timing ................................................................................................................................................................................................. 32
Line Timing Single Output – Progressive Scan .............................................................................................................................. 32
Line Timing Dual Output – Progressive Scan ................................................................................................................................. 32
Line Timing Vertical Binning by 2 – Progressive Scan ................................................................................................................. 33
Line Timing Detail – Progressive Scan ............................................................................................................................................. 33
Line Timing Binning by 2 Detail – Progressive Scan ..................................................................................................................... 34
Line Timing Edge Alignment .............................................................................................................................................................. 34
Pixel Timing ................................................................................................................................................................................................ 35
Pixel Timing Detail ............................................................................................................................................................................... 35
Fast Line Dump Timing ............................................................................................................................................................................ 36
Electronic Shutter ..................................................................................................................................................................................... 37
Electronic Shutter Line Timing .......................................................................................................................................................... 37
Electronic Shutter – Integration Time Definition ......................................................................................................................... 37
Electronic Shutter – DC and AC Bias Definition ............................................................................................................................ 37
Electronic Shutter Description .......................................................................................................................................................... 38
Large Signal Output ................................................................................................................................................................................. 39
Storage and Handling .......................................................................................................................................................................................... 40
Storage Conditions................................................................................................................................................................................... 40
ESD ............................................................................................................................................................................................................... 40
Cover Glass Care and Cleanliness ......................................................................................................................................................... 40
Environmental Exposure ........................................................................................................................................................................ 40
Soldering Recommendations ................................................................................................................................................................ 40
Mechanical Drawings ........................................................................................................................................................................................... 41
Completed Assembly ............................................................................................................................................................................... 41
Die to Package Alignment ...................................................................................................................................................................... 42
Glass ............................................................................................................................................................................................................. 43
Glass Transmission ................................................................................................................................................................................... 44
Quality Assurance and Reliability .................................................................................................................................................................. 45
Quality and Reliability ............................................................................................................................................................................. 45
Replacement .............................................................................................................................................................................................. 45
Liability of the Supplier ........................................................................................................................................................................... 45
Liability of the Customer ........................................................................................................................................................................ 45
Test Data Retention ................................................................................................................................................................................. 45
Mechanical .................................................................................................................................................................................................. 45
Life Support Applications Policy .................................................................................................................................................................... 45
Revision Changes................................................................................................................................................................................................... 46
MTD/PS-0609 ............................................................................................................................................................................................. 46
PS-0018 ....................................................................................................................................................................................................... 46
KAI-2001 Image Sensor
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TABLE OF FIGURES
Figure 1: Sensor Architecture ...................................................................................................................................................................... 7
Figure 2: Pixel Architecture .......................................................................................................................................................................... 8
Figure 3: Vertical to Horizontal Transfer Architecture ......................................................................................................................... 9
Figure 4: Horizontal Register to Floating Diffusion Architecture .................................................................................................... 10
Figure 5: Horizontal Register ..................................................................................................................................................................... 11
Figure 6: Output Architecture ................................................................................................................................................................... 12
Figure 7: Package Pin Designations – Top View .................................................................................................................................... 13
Figure 8: Monochrome with Microlens Quantum Efficiency.............................................................................................................. 16
Figure 9: Monochrome without Microlens Quantum Efficiency ....................................................................................................... 16
Figure 10: Color Quantum Efficiency ....................................................................................................................................................... 17
Figure 11: Angular Quantum Efficiency .................................................................................................................................................. 18
Figure 12: Dark Current versus Temperature ........................................................................................................................................ 18
Figure 13: Power ........................................................................................................................................................................................... 19
Figure 14: Frame Rates ................................................................................................................................................................................ 19
Figure 15: Overclock Regions of Interest ............................................................................................................................................... 21
Figure 16: Test Sub Regions of Interest .................................................................................................................................................. 24
Figure 17: Clock Line Capacitances .......................................................................................................................................................... 27
Figure 18: Progressive Scan Operation ................................................................................................................................................... 29
Figure 19: Progressive Scan Flow Chart .................................................................................................................................................. 29
Figure 20: Framing Timing without Binning ........................................................................................................................................... 30
Figure 21: Frame Timing for Vertical Binning by 2 ............................................................................................................................... 30
Figure 22: Frame Timing Edge Alignment .............................................................................................................................................. 31
Figure 23: Line Timing Single Output ...................................................................................................................................................... 32
Figure 24: Line Timing Dual Output ......................................................................................................................................................... 32
Figure 25: Line Timing Vertical Binning by 2 .......................................................................................................................................... 33
Figure 26: Line Timing Detail ..................................................................................................................................................................... 33
Figure 27: Line Timing by 2 Detail ............................................................................................................................................................ 34
Figure 28: Line Timing Edge Alignment .................................................................................................................................................. 34
Figure 29: Pixel Timing ................................................................................................................................................................................ 35
Figure 30: Pixel Timing Detail .................................................................................................................................................................... 35
Figure 31: Fast Line Dump Timing ............................................................................................................................................................ 36
Figure 32: Electronic Shutter Line Timing .............................................................................................................................................. 37
Figure 33: Integration Time Definition .................................................................................................................................................... 37
Figure 34: Completed Assembly ............................................................................................................................................................... 41
Figure 35: Die to Package Alignment ...................................................................................................................................................... 42
Figure 36: Glass Drawing ............................................................................................................................................................................. 43
Figure 37: Glass Transmission .................................................................................................................................................................... 44
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 5
Summary Specification
KAI-2001 Image Sensor
DESCRIPTION
The KAI-2001 Image Sensor is a high-performance 2-
million pixel sensor designed for a wide range of medical,
scientific and machine vision applications. The 7.4 μm
square pixels with microlenses provide high sensitivity
and the large full well capacity results in high dynamic
range. The split horizontal register offers a choice of
single or dual output allowing either 15 or 30 frame per
second (fps) video rate for the progressively scanned
images. Also included is a fast line dump for sub-sampling
at higher frame rates. The vertical overflow drain
structure provides antiblooming protection and enables
electronic shuttering for precise exposure control. Other
features include low dark current, negligible lag and low
smear.
FEATURES
High resolution
High sensitivity
High dynamic range
Low noise architecture
High frame rate
Binning capability for higher frame rate
Electronic shutter
APPLICATIONS
Machine Vision
Scientific
Parameter
Value
Architecture
Interline CCD; Progressive Scan
Total Number of Pixels
1640 (H) x 1214 (V)
Number of Effective Pixels
1608 (H) x 1208 (V)
Number of Active Pixels
1600 (H) x 1200 (V)
Pixel Size
7.4 μm (H) x 7.4 μm (V)
Imager Size
14.803mm (diagonal)
Chip Size
13.38mm (H) x 9.52mm (V)
Aspect Ratio
4:3
Number of Outputs
1 or 2
Saturation Signal
40,000 e-
Output Sensitivity
16 μV/e
Quantum Efficiency
-ABA
-CBA (BGR)
55%
45%, 42%, 35%
Total System Noise
40MHZ
20MHz
40 e-
23 e-
Dark Current
< 0.5 nA/cm2
Dark Current Doubling
Temperature
7 °C
Dynamic Range
60 dB
Charge Transfer Efficiency
> 0.99999
Blooming Suppression
300X
Smear
80 dB
Image Lag
<10 e-
Maximum Data Rate
40 MHz
All parameters above are specified at T = 40 °C
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 6
Ordering Information
Catalog
Number
Product Name
Description
Marking Code
4H0309
KAI-2001-AAA-CR-BA
Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear
Cover Glass with AR coating (2 sides), Standard Grade
KAI-2001
S/N
4H0310
KAI-2001-AAA-CR-AE
Monochrome, No Microlens, CERDIP Package (sidebrazed), Taped Clear
Cover Glass with AR coating (2 sides), Engineering Sample
4H0318
KAI-2001-AAA-CF-BA
Monochrome, No Microlens, CERDIP Package (sidebrazed), Quartz
Cover Glass (no coatings), Standard Grade
4H0319
KAI- 2001-AAA-CF-AE
Monochrome, No Microlens, CERDIP Package (sidebrazed), Quartz
Cover Glass (no coatings), Engineering Sample
4H0312
KAI-2001-CBA-CD-BA
Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed),
Clear Cover Glass with AR coating (both sides), Standard Grade
KAI-2001CM
S/N
4H0313
KAI-2001-CBA-CD-AE
Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed),
Clear Cover Glass with AR coating (both sides), Engineering Sample
4H0315
KAI-2001-ABA-CD-BA
Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed),
Clear Cover Glass with AR coating (both sides), Standard Grade
KAI-2001M
S/N
4H0316
KAI-2001-ABA-CD-AE
Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed),
Clear Cover Glass with AR coating (both sides), Engineering Sample
4H0354
KAI-2001-ABA-CP-BA
Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed),
Taped Clear Cover Glass, no coatings, Standard Grade
4H0355
KAI-2001-ABA-CP-AE
Monochrome, Telecentric Microlens, CERDIP Package (sidebrazed),
Taped Clear Cover Glass, no coatings, Engineering Sample
4H0691
KEK-4H0691-KAI-2001/2020-12-20
Evaluation Board, 12 Bit, 20 MHz (Complete Kit)
N/A
4H0692
KEK-4H0692-KAI-2001/2020-10-40
Evaluation Board, 10 Bit, 40 MHz (Complete Kit)
See Application Note Product Naming Convention for a full description of the naming convention used for Truesense
Imaging image sensors. For reference documentation, including information on evaluation kits, please visit our web
site at www.truesenseimaging.com.
Please address all inquiries and purchase orders to:
Truesense Imaging, Inc.
1964 Lake Avenue
Rochester, New York 14615
Phone: (585) 784-5500
E-mail: info@truesenseimaging.com
Truesense Imaging reserves the right to change any information contained herein without notice. All information
furnished by Truesense Imaging is believed to be accurate.
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 7
Device Description
ARCHITECTURE
Figure 1: Sensor Architecture
There are 2 light shielded rows followed 1208 photoactive rows and finally 4 more light shielded rows. The first 4 and
the last 4 photoactive rows are buffer rows giving a total of 1200 lines of image data.
In the single output mode all pixels are clocked out of the Video L output in the lower left corner of the sensor. The
first 4 empty pixels of each line do not receive charge from the vertical shift register. The next 16 pixels receive charge
from the left light shielded edge followed by 1608 photosensitive pixels and finally 16 more light shielded pixels from
the right edge of the sensor. The first and last 4 photosensitive pixels are buffer pixels giving a total of 1600 pixels of
image data.
In the dual output mode the clocking of the right half of the horizontal CCD is reversed. The left half of the image is
clocked out Video L and the right half of the image is clocked out Video R. Each row consists of 4 empty pixels followed
by 16 light shielded pixels followed by 800 photosensitive pixels. When reconstructing the image, data from Video R
will have to be reversed in a line buffer and appended to the Video L data.
There are 4 dark reference rows at the top and 2 dark rows at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference level. Use the 16 dark columns on the left or right side of
the image sensor as a dark reference.
Of the 16 dark columns, the first and last dark columns should not be used for determining the zero signal level. Some
light does leak into the first and last dark columns. Only use the center 14 columns of the 16 column dark reference.
4Buffer Rows
1600 (H) x 1200 (H)
Active Pixels
4 Buffer Rows
2 Dark Rows
4 Buffer Rows
4 Buffer Columns
16 Dark Columns
16 Dark Columns
4 Dummy Pixels
4 Dummy Pixels
4 Buffer Columns
Dual
Output
or
Video L Video R
416 41600 416 4
Single
416 4800 800 416 4
4 Dark Rows
GG
R
B
Pixel
1,1
KAI-2001 Image Sensor
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PIXEL
Figure 2: Pixel Architecture
An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-
hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of
potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel
is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. When the
photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming.
Top View
Direction
of
Charge
Transfer
True Two Phase Burried Channel VCCD
Lightshield over VCCD not shown
7.4
m
V1
Photodiode
7.4
m
V2
Transfer
Gate
Direction of
Charge
Transfer
V1 V2 V1
n- n
n- n-
p Well (GND)
Cross Section Down Through VCCD
n Substrate
p
V1
np+
Light Shield
p
p
n
n
Substrate
p
Cross Section Through
Photodiode and VCCD Phase 1
Photo
diode
pp
V2
np+
Light Shield
p
p
n
n
Substrate
p
Cross Section Through Photodiode
and VCCD Phase 2 at Transfer Gate
Transfer
Gate
Cross Section Showing Lenslet Drawings not scale
Lenslet
VCCD VCCD
Light Shield Light Shield
Photodiode
Red Color Filter
KAI-2001 Image Sensor
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VERTICAL TO HORIZONTAL TRANSFER
Figure 3: Vertical to Horizontal Transfer Architecture
When the V1 and V2 timing inputs are pulsed, charge in every pixel of the VCCD is shifted one row towards the HCCD.
The last row next to the HCCD is shifted into the HCCD. When the VCCD is shifted, the timing signals to the HCCD must
be stopped. H1 must be stopped in the high state and H2 must be stopped in the low state. The HCCD clocking may
begin THD µs after the falling edge of the V1 and V2 pulse.
Charge is transferred from the last vertical CCD phase into the H1S horizontal CCD phase. Refer to Figure 26 for an
example of timing that accomplishes the vertical to horizontal transfer of charge.
If the fast line dump is held at the high level (FDH) during a vertical to horizontal transfer, then the entire line is
removed and not transferred into the horizontal register.
Top View
Direction of
Vertical
Charge
Transfer
V1
V2
V1
Photo
diode
V2
Transfer
Gate
Fast
Line
Dump
H1S
H2
S
H
1
B
H
2
B
Direction of
Horizontal
Charge Transfer
Lightshield
not shown
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 10
HORIZONTAL REGISTER TO FLOATING DIFFUSION
Figure 4: Horizontal Register to Floating Diffusion Architecture
The HCCD has a total of 1648 pixels. The 1640 vertical shift registers (columns) are shifted into the center 1640 pixels
of the HCCD. There are 4 pixels at both ends of the HCCD, which receive no charge from a vertical shift register. The
first 4 clock cycles of the HCCD will be empty pixels (containing no electrons). The next 16 clock cycles will contain only
electrons generated by dark current in the VCCD and photodiodes. The next 1608 clock cycles will contain photo-
electrons (image data). Finally, the last 16 clock cycles will contain only electrons generated by dark current in the
VCCD and photodiodes. Of the 16 dark columns, the first and last dark columns should not be used for determining the
zero signal level. Some light does leak into the first and last dark columns. Only use the center 14 columns of the 16
column dark reference.
When the HCCD is shifting valid image data, the timing inputs to the electronic shutter (SUB), VCCD (V1, V2), and fast
line dump (FD) should be not be pulsed. This prevents unwanted noise from being introduced. The HCCD is a type of
charge coupled device known as a pseudo-two phase CCD. This type of CCD has the ability to shift charge in two
directions. This allows the entire image to be shifted out to the video L output, or to the video R output (left/right
image reversal). The HCCD is split into two equal halves of 824 pixels each. When operating the sensor in single output
mode the two halves of the HCCD are shifted in the same direction. When operating the sensor in dual output mode
the two halves of the HCCD are shifted in opposite directions. The direction of charge transfer in each half is controlled
by the H1BL, H2BL, H1BR, and H2BR timing inputs.
n+
ROG H2B H1B H2S H2B H1S H1B
n- n- n-
RD
Floating
Diffusion
n (burried channel)
n
n+
p (GND)
n (SUB)
H1S
n-
KAI-2001 Image Sensor
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HORIZONTAL REGISTER SPLIT
Figure 5: Horizontal Register
Single Output Operation
When operating the sensor in single output mode all pixels of the image sensor will be shifted out the Video L output
(pin 31). To conserve power and lower heat generation the output amplifier for Video R may be turned off by
connecting VDDR (pin 24) and VOUTR (pin 24) to GND (zero volts).
The H1 timing from the timing diagrams should be applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing should be
applied to H2SL, H2BL, H2SR, and H1BR. In other words, the clock driver generating the H1 timing should be
connected to pins 4, 3, 13, and 15. The clock driver generating the H2 timing should be connected to pins 5, 2, 12, and
14. The horizontal CCD should be clocked for 4 empty pixels plus 16 light shielded pixels plus 1608 photoactive pixels
plus 16 light shielded pixels for a total of 1644 pixels.
Dual Output Operation
In dual output mode the connections to the H1BR and H2BR pins are swapped from the single output mode to change
the direction of charge transfer of the right side horizontal shift register. In dual output mode both VDDL and VDDR
(pins 25, 24) should be connected to 15 V. The H1 timing from the timing diagrams should be applied to H1SL, H1BL,
H1SR, H1BR, and the H2 timing should be applied to H2SL, H2BL, H2SR, and H2BR. The clock driver generating the H1
timing should be connected to pins 4, 3, 13, and 14. The clock driver generating the H2 timing should be connected to
pins 5, 2, 12, and 15. The horizontal CCD should be clocked for 4 empty pixels plus 16 light shielded pixels plus 804
photoactive pixels for a total of 824 pixels. If the camera is to have the option of dual or single output mode, the clock
driver signals sent to H1BR and H2BR may be swapped by using a relay. Another alternative is to have two extra clock
drivers for H1BR and H2BR and invert the signals in the timing logic generator. If two extra clock drivers are used, care
must be taken to ensure the rising and falling edges of the H1BR and H2BR clocks occur at the same time (within 3 ns)
as the other HCCD clocks.
Single Output
H2SL
H1SL H1BL H2SRH1SR H2BRH1BR
Pixel
824 Pixel
825
H2SL H2BLH1BL
H1 H1 H1 H1 H1H2 H2 H2 H2 H2
H2SL
H1SL H1BL H2SRH1SR H2BRH1BR
Pixel
824 Pixel
825
H2SL H2BLH1BL
H1 H1 H1 H1 H2H2 H2 H2 H1 H2
Dual Output
KAI-2001 Image Sensor
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OUTPUT
Figure 6: Output Architecture
Charge packets contained in the horizontal register are dumped pixel by pixel onto the floating diffusion (fd) output
node whose potential varies linearly with the quantity of charge in each packet. The amount of potential charge is
determined by the expression Vfd=Q/Cfd. A three-stage source-follower amplifier is used to buffer this signal
voltage off chip with slightly less than unity gain. The translation from the charge domain to the voltage domain is
quantified by the output sensitivity or charge to voltage conversion in terms of microvolts per electron (μV/e-). After
the signal has been sampled off chip, the reset clock (R) removes the charge from the floating diffusion and resets its
potential to the reset drain voltage (RD).
When the image sensor is operated in the binned or summed interlaced modes there will be more than 40,000
electrons in the output signal. The image sensor is designed with a 16 µV/e charge to voltage conversion on the
output. This means a full signal of 40,000 electrons will produce a 640 mV change on the output amplifier. The output
amplifier was designed to handle an output swing of 640 mV at a pixel rate of 40 MHz. If 80,000 electron charge
packets are generated in the binned or summed interlaced modes then the output amplifier output will have to swing
1280 mV. The output amplifier does not have enough bandwidth (slew rate) to handle 1280 mV at 40 MHz. Hence, the
pixel rate will have to be reduced to 20 MHz if the full dynamic range of 80,000 electrons is desired.
The charge handling capacity of the output amplifier is also set by the reset clock voltage levels. The reset clock driver
circuit is very simple if an amplitude of 5 V is used. But the 5 V amplitude restricts the output amplifier charge capacity
to 40,000 electrons. If the full dynamic range of 80,000 electrons is desired then the reset clock amplitude will have to
be increased to 7 V.
If you only want a maximum signal of 40,000 electrons in binned or summed interlaced modes, then a 40 MHz pixel rate
with a 5 V reset clock may be used. The output of the amplifier will be unpredictable above 40,000 electrons so be
sure to set the maximum input signal level of your analog to digital converter to the equivalent of 40,000 electrons
(640 mV).
Floating
Diffusion
HCCD
Charge
Transfer
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
RD
R
OG
H2B
H1B
H2S
H2B
H1S
VDD
VOUT
H1S
VDD
VSS
KAI-2001 Image Sensor
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PIN DESCRIPTION AND PHYSICAL ORIENTATION
Figure 7: Package Pin Designations – Top View
Pin
Name
Description
Pin
Name
Description
1
φRL
Reset Gate, Left
32
VSS
Output Amplifier Return
2
φH2BL
H2 Barrier, Left
31
VOUTL
Video Output, Left
3
φH1BL
H1 Barrier, Left
30
ESD
ESD
4
φH1SL
H1 Storage, Left
29
φV2
Vertical Clock, Phase 2
5
φH2SL
H2 Storage, Left
28
φV1
Vertical Clock, Phase 1
6
GND
Ground
27
VSUB
Substrate
7
OGL
Output Gate, Left
26
GND
Ground
8
RDL
Reset Drain, Left
25
VDDL
Vdd, Left
9
RDR
Reset Drain, Right
24
VDDR
Vdd, Right
10
OGR
Output Gate, Right
23
GND
Ground
11
FD
Fast Line Dump Gate
22
VSUB
Substrate
12
φH2SR
H2 Storage, Right
21
φV1
Vertical Clock, Phase 1
13
φH1SR
H1 Storage, Right
20
φV2
Vertical Clock, Phase 2
14
φH1BR
H1 Barrier, Right
19
GND
Ground
15
φH2BR
H2 Barrier, Right
18
VOUTR
Video Output, Right
16
φRR
Reset Gate, Right
17
VSS
Output Amplifier Return
The pins are on a 0.070” spacing
VSS
VOUTL
ESD
V2
V1
VSUB
GND
VDDL
VDDR
GND
VSUB
V1
V2
GND
VOUTR
VSSRR
RL
H2BL
H1BL
H1SL
H2SL
OGL
OGR
RDR
RDL
H2SR
H1SR
H1BR
H2BR
GND
FD
Pixel 1,1
1732
116
31 30 29 28 27 26 25 24 23 22 21 20 19 18
2 3 4 5 6 7 8 9 151413121110
KAI-2001 Image Sensor
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Imaging Performance
TYPICAL OPERATIONAL CONDITIONS
Unless otherwise noted, Imaging Performance Specifications are measured using the following conditions.
Description
Condition
Notes
Frame Time
237 msec
1
Horizontal Clock Frequency
10 MHz
Light Source
Continuous red, green and blue illumination centered at 450, 530 and 650
nm
2,3
Operation
Nominal operating voltages and timing
Notes:
1. Electronic shutter is not used. Integration time equals frame time.
2. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP-8115.
3. For monochrome sensor, only green LED used.
SPECIFICATIONS
All Configurations
Description
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Temperature
Tested At
(°C)
Notes
Dark Center Uniformity
n/a
n/a
20
e-rms
Die
27, 40
Dark Global Uniformity
n/a
n/a
5.0
mVpp
Die
27, 40
Global Uniformity
n/a
2.5
5.0
%rms
Die
27, 40
1
Global Peak to Peak Uniformity
PRNU
n/a
10
20
%pp
Die
27, 40
1
Center Uniformity
n/a
1.0
2.0
%rms
Die
27, 40
1
Maximum Photoresponse Nonlinearity
NL
n/a
2
%
Design
2,3
Maximum Gain Difference Between Outputs
ΔG
n/a
10
%
Design
2,3
Max. Signal Error due to Nonlinearity Dif.
ΔNL
n/a
1
%
Design
2,3
Horizontal CCD Charge Capacity
Hne
n/a
100
n/a
ke-
Design
Vertical CCD Charge Capacity
VNe
n/a
50
n/a
ke-
Die
Photodiode Charge Capacity
PNe
38
40
n/a
ke-
Die
Horizontal CCD Charge Transfer Efficiency
HCTE
0.99999
n/a
n/a
Design
Vertical CCD Charge Transfer Efficiency
VCTE
0.99999
n/a
n/a
Design
Photodiode Dark Current
Ipd
n/a
40
350
e/p/s
Die
Photodiode Dark Current
Ipd
n/a
0.01
0.1
nA/cm2
Die
Vertical CCD Dark Current
Ivd
n/a
400
1711
e/p/s
Die
Vertical CCD Dark Current
Ivd
n/a
0.12
0.5
nA/cm2
Die
Image Lag
Lag
n/a
<10
50
e-
Design
Antiblooming Factor
Xab
100
300
n/a
Design
Vertical Smear
Smr
n/a
80
75
dB
Design
Total Noise
ne-T
23
e-rms
Design
5
Total Noise
ne-T
40
e-rms
Design
6
Dynamic Range
DR
60
dB
Design
6,7
Output Amplifier DC Offset
Vodc
4
8.5
14
V
Die
Output Amplifier Bandwidth
F-3db
140
MHz
Design
Output Amplifier Impedance
ROUT
100
130
200
Ohms
Die
Output Amplifier Sensitivity
ΔV/ΔN
16
μV/e-
Design
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 15
KAI-2001-ABA Configuration
Description
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Temperature
Tested At
(°C)
Notes
Peak Quantum Efficiency
QEmax
45
55
n/a
%
Design
Peak Quantum Efficiency
Wavelength
λQE
n/a
500
n/a
nm
Design
KAI-2001-CBA Configuration
Description
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Temperature
Tested At
(°C)
Notes
Peak Blue
Quantum Green
Efficiency Red
QEmax
45
42
35
n/a
%
Design
Peak Blue
Quantum Green
Efficiency Red
Wavelength
λQE
n/a
470
540
620
n/a
nm
Design
n/a: not applicable
Notes:
1. Per color.
2. Value is over the range of 10% to 90% of photodiode saturation.
3. Value is for the sensor operated without binning
4. Includes system electronics noise, dark pattern noise and dark current shot noise at 20 MHz.
5. Includes system electronics noise, dark pattern noise and dark current shot noise at 40 MHz.
6. Uses 20LOG(PNe/ne-T)
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 16
Typical Performance Curves
QUANTUM EFFICIENCY
Monochrome with Microlens
Figure 8: Monochrome with Microlens Quantum Efficiency
Monochrome without Microlens
Figure 9: Monochrome without Microlens Quantum Efficiency
0.0
0.1
0.2
0.3
0.4
0.5
0.6
400 500 600 700 800 900 1000
Wavelength (nm)
Absolute
Quantum
Efficiency
Measured with
glass
0.00
0.02
0.04
0.06
0.08
0.10
0.12
240 340 440 540 640 740 840 940
Wavelength (nm)
Absolute Quantum Efficiency
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 17
Color (Bayer RGB) with Microlens
Figure 10: Color Quantum Efficiency
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
400 500 600 700 800 900 1000
Wavelength (nm)
Absolute Quantum Efficiency
Red Green Blue
Measured with
glass
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 18
ANGULAR QUANTUM EFFICIENCY
For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Monochrome with Microlens
Figure 11: Angular Quantum Efficiency
DARK CURRENT VERSUS TEMPERATURE
Figure 12: Dark Current versus Temperature
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30
Angle (degrees)
Relative
Quantum
Efficiency
(%)
Horizontal
Vertical
1
10
100
1000
10000
100000
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4
1000/T(K)
Electrons/second
T (C)
97
84
72
60
50
40
30
21
VCCD
Photodiodes
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 19
POWER - ESTIMATED
Figure 13: Power
FRAME RATES
Figure 14: Frame Rates
0
50
100
150
200
250
300
350
400
450
500
0 5 10 15 20 25 30 35 40
Horizontal Clock Frequency (MHz)
Power (mW)
Output Power One Output(mW) Horizontal Power (mW)
Vertical Power One Output(mW) Total Power One Output (mW)
Right Output Disabled
0
10
20
30
40
50
60
70
10 15 20 25 30 35 40
Pixel Clock (MHz)
Frame Rate (fps)
Single output
Dual output or
Single 2x2 binning
Dual 2x2 binning
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 20
Defect Definitions
Description
Definition
Maximum
Temperature(s) tested
at (°C)
Notes
Major dark field
defective pixel
Defect ≥ 179 mV
20
27, 40
1
Major bright field
defective pixel
Defect ≥ 15 %
1
Minor dark field
defective pixel
Defect ≥ 57 mV
200
27, 40
Cluster defect
A group of 2 to 10 contiguous major defective
pixels, but no more than 2 adjacent defects
horizontally
8
27, 40
1
Column defect
A group of more than 10 contiguous major
defective pixels along a single column
0
27, 40
1
Notes:
1. There will be at least two non-defective pixels separating any two major defective pixels.
DEFECT MAP
The defect map supplied with each sensor is based upon testing at an ambient (27 °C) temperature. Minor point
defects are not included in the defect map. All defective pixels are reference to pixel 1, 1 in the defect maps.
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 21
Test Definitions
TEST REGIONS OF INTEREST
Active Area ROI: Pixel (1, 1) to Pixel (1600, 1200)
Center 100 by 100 ROI: Pixel (750, 550) to Pixel (849, 649)
Only the active pixels are used for performance and defect tests.
OVERCLOCKING
The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions.
See Figure 15 for a pictorial representation of the regions.
Figure 15: Overclock Regions of Interest
Pixel 1,1
Vertical Overclock
Horizontal Overclock
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 22
TESTS
Dark Field Center Non-Uniformity
This test is performed under dark field conditions. Only the center 100 by 100 pixels of the sensor are used for this test
- pixel (750, 550) to pixel (849, 649).
Units: mV rms. DPS integration time: Device Performance Specification Integration Time = 33 msec.
Dark Field Global Non-Uniformity
This test is performed under dark field conditions. The sensor is partitioned into 192 sub regions of interest, each of
which is 100 by 100 pixels in size. See Figure 16. The average signal level of each of the 192 sub regions of interest is
calculated. The signal level of each of the sub regions of interest is calculated using the following formula:
Signal of ROI[i] = (ROI Average in ADU – Horizontal overclock average in ADU) * mV per count
Where i = 1 to 192. During this calculation on the 192 sub regions of interest, the maximum and minimum signal levels
are found. The dark field global uniformity is then calculated as the maximum signal found minus the minimum signal
level found.
Units: mVpp (millivolts peak to peak)
Global Non-Uniformity
This test is performed with the imager illuminated to a level such that the output is at 80% of saturation
(approximately 32,000 electrons). Prior to this test being performed the substrate voltage has been set such that the
charge capacity of the sensor is 40,000 electrons. Global uniformity is defined as
Signal Area Active Deviation Standard Area Active
* 100 y UniformitGlobal
Units: %rms. Active Area Signal = Active Area Average – Horizontal Overclock Average.
Global Peak to Peak Non-Uniformity
This test is performed with the imager illuminated to a level such that the output is at 80% of saturation
(approximately 32,000 electrons). Prior to this test being performed the substrate voltage has been set such that the
charge capacity of the sensor is 40,000 electrons. The sensor is partitioned into 192 sub regions of interest, each of
which is 100 by 100 pixels in size. See Figure 16. The average signal level of each of the 192 sub regions of interest
(ROI) is calculated. The signal level of each of the sub regions of interest is calculated using the following formula:
Signal of ROI[i] = (ROI Average in ADU – Horizontal overclock average in ADU) * mV per count
Where i = 1 to 192. During this calculation on the 192 sub regions of interest, the maximum and minimum signal levels
are found. The global peak to peak uniformity is then calculated as:
Signal AreaActive Signal Minimum - Signal Maximum
Uniformity Global
Units: %pp
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 23
Center Non-Uniformity
This test is performed with the imager illuminated to a level such that the output is at 80% of saturation
(approximately 32,000 electrons). Prior to this test being performed the substrate voltage has been set such that the
charge capacity of the sensor is 40,000 electrons. Defects are excluded for the calculation of this test. This test is
performed on the center 100 by 100 pixels of the sensor (see Figure 16). Center uniformity is defined as:
Signal ROI Center Deviation Standard ROI Center
* 100 Uniformity ROI Center
Units: %rms. Center ROI Signal = Center ROI Average – Horizontal Overclock Average.
Dark Field Defect Test
This test is performed under dark field conditions. The sensor is partitioned into 192 sub regions of interest, each of
which is 100 by 100 pixels in size (see Figure 16). In each region of interest, the median value of all pixels is found. For
each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of
interest plus the defect threshold specified in “Defect Definitions” section.
Bright Field Defect Test
This test is performed with the imager illuminated to a level such that the output is at 80% of saturation
(approximately 32,000 electrons). Prior to this test being performed the substrate voltage has been set such that the
charge capacity of the sensor is 40,000 electrons. The average signal level of all active pixels is found. The bright and
dark thresholds are set as:
Dark defect threshold = Active Area Signal * threshold
Bright defect threshold = Active Area Signal * threshold
The sensor is then partitioned into 192 sub regions of interest, each of which is 100 by 100 pixels in size (see Figure 16).
In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked
defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified
or if it is less than or equal to the median value of that region of interest minus the dark threshold specified.
Example for major bright field defective pixels:
Average value of all active pixels is found to be 416 mV (32,000 electrons).
Dark defect threshold: 416mV * 15% = 62.4 mV
Bright defect threshold: 416mV * 15% = 62.4 mV
Region of interest #1 selected. This region of interest is pixels 1, 1 to pixels 100, 100.
o Median of this region of interest is found to be 416 mV.
o Any pixel in this region of interest that is ≥ (416+62.4 mV) 478.4 mV in intensity will be marked
defective.
o Any pixel in this region of interest that is ≥ (416-62.4 mV) 353.6 mV in intensity will be marked
defective.
All remaining 191 sub regions of interest are analyzed for defective pixels in the same manner.
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 24
Test Sub Regions of Interest
Figure 16: Test Sub Regions of Interest
Pixel
(1,1)
Pixel
(1600,1200)
1 2 3 4 5 6 7 8 9 10
17 18 19 20 21 22 23 24 25 26
33 34 35 36 37 38 39 40 41 42
49 50 51 52 53 54 55 56 57 58
65 66 67 68 69 70 71 72 73 74
81 82 83 84 85 86 87 88 89 90
97 98 99 100 101 102 103 104 105 106
113 114 115 116 117 118 119 120 121 122
129 130 131 132 133 134 135 136 137 138
11 12 13 14 15 16
27 28 29 30 31 32
43 44 45 46 47 48
59 60 61 62 63 64
75 76 77 78 79 80
91 92 93 94 95 96
107 108 109 110 111 112
123 124 125 126 127 128
139 140 141 142 143 144
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 25
Operation
MAXIMUM RATINGS
Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the
description. If the level or the condition is exceeded, the device will be degraded and may be damaged.
Description
Symbol
Minimum
Maximum
Units
Notes
Operating Temperature
TOP
-50
70
°C
1
Humidity
RH
5
90
%
2
Output Bias Current
Iout
0.0
10
mA
3
Off-chip Load
CL
10
pF
4
Notes:
1. Noise performance will degrade at higher temperatures.
2. T=25 °C. Excessive humidity will degrade MTTF.
3. Total for both outputs. Current is 5 mA for each output. Note that the current bias affects the amplifier bandwidth.
4. With total output load capacitance of CL = 10 pF between the outputs and AC ground.
MAXIMUM VOLTAGE RATINGS BETWEEN PINS
Description
Minimum
Maximum
Units
Notes
RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGR, OGL to
ESD
0
17
V
Pin to Pin with ESD Protection
-17
17
V
1
VDDL, VDDR to GND
0
25
V
Notes:
1. Pins with ESD protection are: RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGL, and OGR.
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 26
DC BIAS OPERATING CONDITIONS
Description
Symbol
Minimum
Nominal
Maximum
Units
Maximum DC
Current (mA)
Notes
Output Gate
OG
-3.0
-2.5
-2.0
V
1 μA
Reset Drain
RD
11.5
12.0
12.5
V
1 μA
Output Amplifier Supply
VDD
14.5
15.0
15.5
V
1 mA
1
Ground
GND
0.0
0.0
0.0
V
Substrate
SUB
8.0
Vab
17.0
V
2, 4
ESD Protection
ESD
-8.0
-7.0
-6.0
V
3
Output Amplifier Return
VSS
0.0
0.7
1.0
V
Notes:
1. The operating value of the substrate voltage, Vab, will be marked on the shipping container for each device. The value Vab
is set such that the photodiode charge capacity is 40,000 electrons.
2. VESD must be at least 1 Volt more negative than H1L, H2L and RL during sensors operation AND during camera power turn
on.
3. One output, unloaded
4. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 27
AC OPERATING CONDITIONS
Clock Levels
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
Vertical CCD Clock High
V2H
7.5
8.0
8.5
V
Vertical CCD Clocks Midlevel
V1M, V2M
-0.2
0.0
0.2
V
Vertical CCD Clocks Low
V1L, V2L
-9.5
-9.0
-8.5
V
Horizontal CCD Clocks Amplitude
H1H, H2H
4.5
5.0
5.5
V
Horizontal CCD Clocks Low
H1L, H2L
-5.0
-4.0
-3.8
V
Reset Clock Amplitude
RH
5.0
V
1
Reset Clock Low
RL
-4.0
-3.5
-3.0
V
2
Electronic Shutter Voltage
Vshutter
44
48
52
V
3
Fast Dump High
FDH
4.8
5.0
5.2
V
Fast Dump Low
FDL
-9.5
-9
-8
V
Notes:
1. Reset amplitude must be set to 7.0 V for 80,000 electrons output in summed interlaced or binning modes.
2. Reset low level must be set to –5.0 V for 80,000 electrons output in summed interlaced or binning modes.
3. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Clock Line Capacitances
Figure 17: Clock Line Capacitances
V1
V2
GND
25nF
25nF
H1SL+H1BL
66pF
H2SL+H2BL
58pF
H1SR+H1BR
66pF
H2SR+H2BR
58pF
20pF
20pF
GND
GND
Reset
10pF
GND
SUB
2nF
GND
FD
21pF
5nF
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 28
TIMING REQUIREMENTS
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
HCCD Delay
THD
1.3
1.5
10.0
μs
VCCD Transfer time
TVCCD
1.3
1.5
20.0
μs
Photodiode Transfer time
TV3rd
8.0
12.0
15.0
μs
VCCD Pedestal time
T3P
20.0
25.0
50.0
μs
VCCD Delay
T3D
15.0
20.0
100.0
μs
Reset Pulse time
TR
5.0
10.0
ns
Shutter Pulse time
TS
3.0
5.0
10.0
μs
Shutter Pulse delay
TSD
1.0
1.6
10.0
μs
HCCD Clock Period
TH
25.0
50.0
200.0
ns
VCCD rise/fall time
TVR
0.0
0.1
1.0
μs
Fast Dump Gate delay
TFD
0.0
0.0
0.5
μs
Vertical Clock Edge Alignment
TVE
0.0
100.0
ns
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 29
TIMING MODES
Progressive Scan
Figure 18: Progressive Scan Operation
In progressive scan read out every pixel in the image sensor is read out simultaneously. Each charge packet is
transferred from the photodiode to the neighboring vertical CCD shift register simultaneously. The maximum useful
signal output is limited by the photodiode charge capacity to 40,000 electrons.
Figure 19: Progressive Scan Flow Chart
photodiode CCD shift register
0
1
2
3
5
4
7
6
output
HCCD
Vertical Frame
Timing
Line Timing
Repeat for
1214 Lines
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 30
FRAME TIMING
Frame Timing without Binning – Progressive Scan
Figure 20: Framing Timing without Binning
Frame Timing for Vertical Binning by 2 – Progressive Scan
Figure 21: Frame Timing for Vertical Binning by 2
V1
V2
H1
H2
TLTV3rd
T3P T3D
TL
Line 1214 Line 1
Line 1213
V1
V2
H1
H2
TLTV3rd
T3P T3D
TL
Line 607 Line 1Line 606
3 x TVCCD
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 31
Frame Timing Edge Alignment
Figure 22: Frame Timing Edge Alignment
V1
V2
T
VE
V1M
V1L
V2H
V2M
V2L
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 32
LINE TIMING
Line Timing Single Output – Progressive Scan
Figure 23: Line Timing Single Output
Line Timing Dual Output – Progressive Scan
Figure 24: Line Timing Dual Output
V1
V2 TVCCD
TL
THD
H1
H2
R
2
1
pixel count
19
4
5
6
7
20
21
22
23
1625
1626
1627
1629
1630
1643
1644
24
1628
1642
3
V1
V2 TVCCD
TL
THD
H1
H2
R
2
1
pixel count
19
4
5
6
7
20
21
22
23
816
817
818
820
821
824
825
24
819
823
822
3
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 33
Line Timing Vertical Binning by 2 – Progressive Scan
Figure 25: Line Timing Vertical Binning by 2
Line Timing Detail – Progressive Scan
Figure 26: Line Timing Detail
V1
V2 3 x TVCCD
TL
THD
H1
H2
R
2
1
pixel count
19
4
5
6
7
20
21
22
23
1625
1626
1627
1629
1630
1643
1644
24
1628
1642
3
V1
V2 T
VCCD
H2
T
HD
1/2 T
H
R
H1
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 34
Line Timing Binning by 2 Detail – Progressive Scan
Figure 27: Line Timing by 2 Detail
Line Timing Edge Alignment
Applies to all modes.
Figure 28: Line Timing Edge Alignment
V1
V2
T
VCCD
H2
T
HD
1/2 T
H
R
H1
T
VCCD
T
VCCD
V1
V2
T
VE
T
VE
T
VCCD
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 35
PIXEL TIMING
Figure 29: Pixel Timing
Pixel Timing Detail
Figure 30: Pixel Timing Detail
H2
R
Vout
V1
V2
Pixel
Count
Dummy Pixels Light Shielded Pixels Photosensitive Pixels
H1
1 5 19 20 21
4
32
R
H2
VOUT
TRRH
RL
H1H
H1L
H2H
H2L
H1
KAI-2001 Image Sensor
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FAST LINE DUMP TIMING
Figure 31: Fast Line Dump Timing
TVCCD
V1
V2
TFD
FD
TFD
TVCCD
H1
H2
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 37
ELECTRONIC SHUTTER
Electronic Shutter Line Timing
Figure 32: Electronic Shutter Line Timing
Electronic Shutter – Integration Time Definition
Figure 33: Integration Time Definition
Electronic Shutter – DC and AC Bias Definition
The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock
are referenced to ground.
V1
V2 TVCCD
TS
THD
H1
H2
R
TSD
VShutter
VSUB
V2
Integration Time
VShutter
VSUB
VSUB
VShutter
GND GND
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 38
Electronic Shutter Description
The voltage on the substrate (SUB) determines the charge capacity of the photodiodes. When SUB is 8 volts the
photodiodes will be at their maximum charge capacity. Increasing VSUB above 8 volts decreases the charge capacity of
the photodiodes until 48 volts when the photodiodes have a charge capacity of zero electrons. Therefore, a short pulse
on SUB, with a peak amplitude greater than 48 volts, empties all photodiodes and provides the electronic shuttering
action.
It may appear the optimal substrate voltage setting is 8 volts to obtain the maximum charge capacity and dynamic
range. While setting VSUB to 8 volts will provide the maximum dynamic range, it will also provide the minimum
antiblooming protection.
The KAI-2001 VCCD has a charge capacity of 55,000 electrons (55 ke-). If the SUB voltage is set such that the
photodiode holds more than 55 ke-, then when the charge is transferred from a full photodiode to VCCD, the VCCD will
overflow. This overflow condition manifests itself in the image by making bright spots appear elongated in the vertical
direction. The size increase of a bright spot is called blooming when the spot doubles in size. The blooming can be
eliminated by increasing the voltage on SUB to lower the charge capacity of the photodiode. This ensures the VCCD
charge capacity is greater than the photodiode capacity. There are cases where an extremely bright spot will still cause
blooming in the VCCD. Normally, when the photodiode is full, any additional electrons generated by photons will spill
out of the photodiode. The excess electrons are drained harmlessly out to the substrate. There is a maximum rate at
which the electrons can be drained to the substrate. If that maximum rate is exceeded, (for example, by a very bright
light source) then it is possible for the total amount of charge in the photodiode to exceed the VCCD capacity. This
results in blooming. The amount of antiblooming protection also decreases when the integration time is decreased.
There is a compromise between photodiode dynamic range (controlled by VSUB) and the amount of antiblooming
protection. A low VSUB voltage provides the maximum dynamic range and minimum (or no) antiblooming protection. A
high VSUB voltage provides lower dynamic range and maximum antiblooming protection. The optimal setting of VSUB
is written on the container in which each KAI-2001 is shipped. The given VSUB voltage for each sensor is selected to
provide antiblooming protection for bright spots at least 100 times saturation, while maintaining at least 40 ke- of
dynamic range.
The electronic shutter provides a method of precisely controlling the image exposure time without any mechanical
components. If an integration time of TINT is desired, then the substrate voltage of the sensor is pulsed to at least 40
volts TINT seconds before the photodiode to VCCD transfer pulse on V2. Use of the electronic shutter does not have to
wait until the previously acquired image has been completely read out of the VCCD.
KAI-2001 Image Sensor
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LARGE SIGNAL OUTPUT
When the image sensor is operated in the binned or summed interlaced modes there will be more than 40,000
electrons in the output signal. The image sensor is designed with a 16µV/e charge to voltage conversion on the
output. This means a full signal of 40,000 electrons will produce a 640 mV change on the output amplifier. The output
amplifier was designed to handle an output swing of 640 mV at a pixel rate of 40 MHz. If 80,000 electron charge
packets are generated in the binned or summed interlaced modes then the output amplifier output will have to swing
1280 mV. The output amplifier does not have enough bandwidth (slew rate) to handle 1280 mV at 40 MHz. Hence, the
pixel rate will have to be reduced to 20 MHz if the full dynamic range of 80,000 electrons is desired.
The charge handling capacity of the output amplifier is also set by the reset clock voltage levels. The reset clock driver
circuit is very simple if an amplitude of 5 V is used. But the 5 V amplitude restricts the output amplifier charge capacity
to 40,000 electrons. If the full dynamic range of 80,000 electrons is desired then the reset clock amplitude will have to
be increased to 7 V.
If you only want a maximum signal of 40,000 electrons in binned or summed interlaced modes, then a 40 MHz pixel rate
with a 5 V reset clock may be used. The output of the amplifier will be unpredictable above 40,000 electrons so be
sure to set the maximum input signal level of your analog to digital converter to the equivalent of 40,000 electrons
(640 mV).
KAI-2001 Image Sensor
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Storage and Handling
STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Units
Notes
Storage
Temperature
TST
-55
80
°C
1
Humidity
RH
5
90
%
2
Notes:
1. Long-term exposure toward the maximum
temperature will accelerate color filter degradation.
2. T=25 °C. Excessive humidity will degrade MTTF
ESD
1. This device contains limited protection against
Electrostatic Discharge (ESD). ESD events may
cause irreparable damage to a CCD image sensor
either immediately or well after the ESD event
occurred. Failure to protect the sensor from
electrostatic discharge may affect device
performance and reliability.
2. Devices should be handled in accordance with
strict ESD procedures for Class 0 (<250V per
JESD22 Human Body Model test), or Class A
(<200V JESD22 Machine Model test) devices.
Devices are shipped in static-safe containers and
should only be handled at static-safe
workstations.
3. See Application Note Image Sensor Handling Best
Practices for proper handling and grounding
procedures. This application note also contains
workplace recommendations to minimize
electrostatic discharge.
4. Store devices in containers made of electro-
conductive materials.
COVER GLASS CARE AND CLEANLINESS
1. The cover glass is highly susceptible to particles
and other contamination. Perform all assembly
operations in a clean environment.
2. Touching the cover glass must be avoided.
3. Improper cleaning of the cover glass may
damage these devices. Refer to Application Note
Image Sensor Handling Best Practices.
ENVIRONMENTAL EXPOSURE
1. Extremely bright light can potentially harm CCD
image sensors. Do not expose to strong sunlight
for long periods of time, as the color filters
and/or microlenses may become discolored. In
addition, long time exposures to a static high
contrast scene should be avoided. Localized
changes in response may occur from color
filter/microlens aging. For Interline devices, refer
to Application Note Using Interline CCD Image
Sensors in High Intensity Visible lighting
Conditions.
2. Exposure to temperatures exceeding maximum
specified levels should be avoided for storage
and operation, as device performance and
reliability may be affected.
3. Avoid sudden temperature changes.
4. Exposure to excessive humidity may affect
device characteristics and may alter device
performance and reliability, and therefore should
be avoided.
5. Avoid storage of the product in the presence of
dust or corrosive agents or gases, as
deterioration of lead solderability may occur. It is
advised that the solderability of the device leads
be assessed after an extended period of storage,
over one year.
SOLDERING RECOMMENDATIONS
1. The soldering iron tip temperature is not to
exceed 370 °C. Higher temperatures may alter
device performance and reliability.
2. Flow soldering method is not recommended.
Solder dipping can cause damage to the glass
and harm the imaging capability of the device.
Recommended method is by partial heating using
a grounded 30 W soldering iron. Heat each pin
for less than 2 seconds duration.
KAI-2001 Image Sensor
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Mechanical Drawings
COMPLETED ASSEMBLY
Figure 34: Completed Assembly
Configuration
Marking Code
Monochrome
KAI-2001
SN
Monochrome with Lenslets
KAI-2001M
SN
Color with Lenslets
KAI-2001CM
SN
Notes:
1. See table for marking code
2. Cover glass is manually placed and visually aligned
over die - Location accuracy is not guaranteed
DIMENSIONS UNITS: INCH [MM]
TOLERANCE: UNLESS OTHERWISE SPECIFIED
CERAMIC +/- 1% NO LESS THAN 0.005"
L/F +/- 1% NO MORE THAN 0.005"
MARKING
CODE
KAI-2001 Image Sensor
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DIE TO PACKAGE ALIGNMENT
Figure 35: Die to Package Alignment
Notes:
1. Center of image is offset from center of package by
(0.00, 0.00) mm nominal.
2. Die is aligned within +/- 2 degree of any package
cavity edge.
DIMENSIONS UNITS: IN [MM]
TOLERANCES: UNLESS OTHERWISE SPECIFIED
CERAMIC +/- 1% NO LESS THAN 0.005"
L/F +/- 1% NO MORE THAN 0.005"
KAI-2001 Image Sensor
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GLASS
Figure 36: Glass Drawing
EPOXY: NCO-150HB
THK.0.002-0.005
4X C 0.020
TYP
[C 0.51]
8X C 0.002-0.008 TYP
[C 0.05-0.20]
NOTES:
1. MATERIALS: SUBSTRATE = SCHOTT D263T eco or equivalent
EPOXY = NCO-150HB
THK = 0.002 - 0.005
2. DUST/SCRATCH COUNT = 10 MICRON MAX
3. DOUBLE SIDED AR COATING REFLECTANCE:
420 -435 nm < 2.0%
435 -630 nm < 0.8%
630 -680 nm < 2.0%
UNITS: IN [MM]
TOLERANCE: UNLESS OTHERWISE SPECIFIED
+/- 1% NO LESS THAN 0.005"
KAI-2001 Image Sensor
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GLASS TRANSMISSION
Figure 37: Glass Transmission
0
10
20
30
40
50
60
70
80
90
100
200 300 400 500 600 700 800 900
Wavelength (nm)
Transmission (%)
KAI-2001 Image Sensor
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Quality Assurance and Reliability
QUALITY AND RELIABILITY
All image sensors conform to the specifications stated in this document. This is accomplished through a combination
of statistical process control and visual inspection and electrical testing at key points of the manufacturing process,
using industry standard methods. Information concerning the quality assurance and reliability testing procedures and
results are available from Truesense Imaging upon request. For further information refer to Application Note Quality
and Reliability.
REPLACEMENT
All devices are warranted against failure in accordance with the Terms of Sale. Devices that fail due to mechanical and
electrical damage caused by the customer will not be replaced.
LIABILITY OF THE SUPPLIER
A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the
customer. Product liability is limited to the cost of the defective item, as defined in the Terms of Sale.
LIABILITY OF THE CUSTOMER
Damage from mishandling (scratches or breakage), electrostatic discharge (ESD), or other electrical misuse of the
device beyond the stated operating or storage limits, which occurred after receipt of the sensor by the customer, shall
be the responsibility of the customer.
TEST DATA RETENTION
Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for a period of 2
years after date of delivery.
MECHANICAL
The device assembly drawing is provided as a reference.
Truesense Imaging reserves the right to change any information contained herein without notice. All information
furnished by Truesense Imaging is believed to be accurate.
Life Support Applications Policy
Truesense Imaging image sensors are not authorized for and should not be used within Life Support Systems without
the specific written consent of Truesense Imaging, Inc.
KAI-2001 Image Sensor
www.truesenseimaging.com Revision 1.0 PS-0018 Pg 46
©Truesense Imaging Inc., 2012. TRUESENSE is a registered trademark of Truesense Imaging, Inc.
Revision Changes
MTD/PS-0609
Revision Number
Description of Changes
1.0
Initial formal release
1.1
Removed caution for cover glass protective tape. The use of the protective tape has been discontinued.
2.0
Updated format
Updated Ordering Information
3.0
Reformatted Ordering Information, Storage and Handling, and Quality Assurance and Reliability pages
4.0
Added the note “Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions”
to the following sections
o DC Bias Operating Conditions
o AC Operating Conditions
o Storage and Handling
Changed cover glass material to D263T eco or equivalent
PS-0018
Revision Number
Description of Changes
1.0
Initial release with new document number, updated branding and document template
Updated Storage and Handling and Quality Assurance and Reliability sections
Reorganized structure for consistency with other Interline Transfer CCD documents
