OKI Semiconductor MS81V04166A FEDS81V04166A-01 This version: Nov.,21, 2002 Dual FIFO (262,214 Words x 8 Bits) x 2 GENERAL DESCRIPTION The MS81V04166A is a single-chip 4Mb FIFO functionally composed of two Oki's 2Mb FIFO (First-In First-Out) memories which were designed for 256k x 8-bit high-speed asynchronous read/write operation. The read clock of each of the 2Mb FIFO memories is connected in common, and the clocks are provided independently of each of the FIFO memories. The MS81V04166A functionally compatible with Oki's 2Mb FIFO memory (MSM51V8222A), can be used as a x16 configuration FIFO. The MS81V04166A is a field memory for wide or low end use in general commodity TVs and VTRs exclusively and is not designed for high end use in professional graphics systems, which require long term picture storage, data storage, medical use and other storage systems. The MS81V04166A provides independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams. The MS81V04166A provides high speed FIFO (First-in First-out) operation without external refreshing: MS81V04166A refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MS81V04166A's function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. The delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 71 x 16-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. The MS81V04166A, which is provided with two sets of the serial write clocks, allows the split-screen processing to be implemented easily. Additionally, the MS81V04166A has a write mask function or input enable function (IE), and read-data skipping function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to the MS81V04166A. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a "picture in picture" on a TV screen. 1/19 FEDS81V04166A-01 1Semiconductor MS81V04166A FEATURES * * * * * * * * * 262,214 words x 8 bits x 2 Fast FIFO (First-In First-Out) Operation: 25 ns cycle time Self refresh (No refresh control is required) High speed asynchronous serial access Read/Write Cycle Time 20 ns/25 ns Access Time 18 ns/23 ns Variable length delay bit (150 to 262214) Write mask function (Output enable control) Cascading capability by mode setting Single power supply: 3.3 V 0.3V Package: 100-Pin plastic TQFP (TQFP 100-P-1414-0.50-k) (Product: MS81V04166A-xxTB) xx indicates speed rank. Parameter Access Time Symbol tAC MS81V04166A-xxTB -20 -25 18 ns 23 ns 20 ns 25 ns Read/Write tSWC Cycle Time tSRC Operation current ICC1 80 mA 80 mA Standby current ICC2 3 mA 3 mA 2/19 FEDS81V04166A-01 1Semiconductor MS81V04166A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC DI22 DI21 DI20 RSTW2 IE2 WE2 VSS VCC VSS NC VCC NC VSS NC MODE1 NC VCC RSTR2 RE2 OE2 NC VSS VSS NC PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 PIN TQFP TOP VIEW VCC DO20 DO21 VSS DO22 DO23 DO24 DO25 VSS DO26 DO27 VCC SRCK VCC DO17 DO16 VSS DO15 DO14 DO13 DO12 VSS DO11 DO10 VCC NC DI12 DI11 DI10 RSTW1 IE1 WE1 VSS VCC VSS NC VCC NC VSS NC SWCK1 NC VCC RSTR1 RE1 OE1 NC VSS VSS NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DI23 VSS DI24 DI25 DI26 DI27 NC VSS VSS VCC VCC SWCK2 VCC VCC VSS VSS NC DI17 DI16 DI15 DI14 VSS DI13 NC Pin Name Function Pin Name Function SWCK1 Port1 Serial Write clock SRCK Serial Read Clock SWCK2 Port2 Serial Write clock WE2 Port2 Write Enable WE1 Port1 Write Enable RE2 Port2 Read Enable RE1 Port1 Read Enable IE2 Port2 Input Enable IE1 Port1 Input Enable OE1 Port1 Output Enable RSTW2 OE2 Port2 Reset Write Port2 Output Enable RSTW1 Port1 Reset Write RSTR2 Port2 Reset Read RSTR1 Port1 Reset Read DI20 to 27 Port2 Data Input DI10 to 17 Port1 Data Input DO20 to 27 Port2 Data Output DO10 to 17 Port1 Data Output NC No Connection Mode Input VSS Ground (0 V) MODE1 VCC Note: Power Supply (3.3 V) The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 3/19 DI (x8) Data-In Buffer (x8) 71 Word Sub-Register (x8) 71 Word Sub-Register (x8) Data-Out Buffer (x8) DO (x8) x8 Memory Array 256k (x8) x8 WE1 x Decoder SWCK Controller RSTW1 Write Serial Read Register (x8) Serial IE1 SRCK Controller RSTR1 Read RE1 Serial Read Register (x8) Serial OE1 Read/Write and Refresh Controller VBB Generator MODE1,2 Clock Oscillator Read/Write and Refresh Controller OE2 Controller RE2 x8 x8 Memory Array 256k (x8) Serial RSTW2 Write WE2 IE2 Controller Serial Write Register (x8) SWCK Decoder x Read RSTR2 Serial Read Register (x8) Serial SRCK DI (x8) Data-In Buffer (x8) 71 Word Sub-Register (x8) 71 Word Sub-Register (x8) Data-Out Buffer (x8) DO (x8) FEDS81V04166A-01 1Semiconductor MS81V04166A BLOCK DIAGRAM 4/19 FEDS81V04166A-01 1Semiconductor MS81V04166A PIN DESCRIPTION Data Inputs: (DIN10 to 17) These pins are used for serial data inputs. Write Reset: RSTW1 The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW1 setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW1, the states of WE1 and IE1 are ignored in the write reset cycle. Before RSTW1 may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Write Enable: WE1 WE1 is used for data write enable/disable control. WE1 high level enables the input, and WE1 low level disables the input and holds the internal write address pointer. There are no WE1 disable time (low) and WE1 enable time (high) restrictions, because the MS81V01466A is in fully static operation as long as the power is on. Note that WE1 setup and hold times are referenced to the rising edge of SWCK. Input Enable: IE1 IE1 is used to enable/disable writing into memory. IE1 high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE1 level. Note that IE1 setup and hold times are referenced to the rising edge of SWCK. Data Out: (DOUT0 to 11) These pins are used for serial data outputs. Read Reset: RSTR1 The first positive transition of SRCK after RSTR1 becomes high resets the read address pointers to zero. RSTR1 setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR, the states of RE1 and OE1 are ignored in the read reset cycle. Before RSTR may be brought high again for a further reset operation, it must be low for at least *two SRCK cycles. Read Enable: RE1 The function of RE1 is to gate of the SRCK clock for incrementing the read pointer. When RE1 is high before the rising edge of SRCK, the read pointer is incremented. When RE1 is low, the read pointer is not incremented. RE1 setup times (tRENS and tRDSS) and RE1 hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock. Output Enable: OE1 OE1 is used to enable/disable the outputs. OE1 high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE1 level. Note that OE1 setup and hold times are referenced to the rising edge of SRCK. Serial Write: Clock SWCK1 The SWCK1 latches the input data on chip when WE1 and IE1 are high, and also increments the internal write address pointer when WE1 is high. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK1. Serial Write Clock: SWCK2 The SWCK2 latches the input data on chip when WE2 and IE2 are high, and also increments the internal write address pointer when WE2 is high, Data-in setup time tDS and hold time tDH are referenced to the rising edge of SWCK2. 5/19 FEDS81V04166A-01 1Semiconductor MS81V04166A Serial Read Clock: SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE1, 2 is high during a read operation. The SRCK input increments the internal read address pointer when RE1, 2 is high. The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of SRCK. Data Input: (DIN20 to 27) These pins are used for serial data inputs. Write Reset: RSTW2 The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW2 setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW2, the states of WE2 and IE2 are ignored in the write reset cycle. Before RSTW2 may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Write Enable: WE2 WE is used for data write enable/disable control. WE2 high level enables the input, and WE2 low level disables the input and holds the internal write address pointer. There are no WE2 disable time (low) and WE2 enable time (high) restrictions, because the MS81V04166A is in fully static operation as long as the power is on. Note that WE2 setup and hold times are referenced to the rising edge of SWCK. Input Enable: IE2 IE2 is used to enable/disable writing into memory. IE2 high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE2 level. Note that IE2 setup and hold times are referenced to the rising edge of SWCK. Data Out: (DOUT20 to 27) These pins are used for serial data outputs. Read Reset: RSTR2 The first positive transition of SRCK after RSTR2 becomes high resets the read address pointers to zero. RSTR2 setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR2, the states of RE2 and OE2 are ignored in the read reset cycle. Before RSTR2 may be brought high again for a further reset operation, it must be low for at least *two SRCK cycles. Output Enable: OE2 OE2 is used to enable/disable the outputs. OE2 high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE2 level. Note that OE2 setup and hold times are referenced to the rising edge of SRCK. Mode Setting: MODE1 The Cascade/Non cascade select pin. Setting the MODE1 pin to the VCC level configures this memory device as cascade type and setting the pin to the VSS level configures this memory device as non cascade. During memory operation, the pin must be permanently connected to VCC or VSS. If a MODE1 level is changed during memory operation, memory data is not guaranteed. Note: Cascade/Non cascade When MODE1 is set to the VSS level, memory accessing starts in the cycle in which the control signals are input (Non cascade type). When MODE1 is set to the VCC level, memory accessing starts in the cycle subsequent to the cycle in which the control signals are input (Cascade type). This type is used for consecutive memory accessing. 6/19 FEDS81V04166A-01 1Semiconductor MS81V04166A ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Condition Rating Input Output Voltage VT at Ta = 25C, VSS -1.0 to +5.5 V Output Current IOS Ta = 25C 50 mA Power Dissipation Unit PD Ta = 25C 1 W Operating Temperature TOPR -- 0 to 70 C Storage Temperature TSTG -- -55 to +150 C Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage VCC 3.0 3.3 3.6 V Power Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.4 VCC 5.5 V Input Low Voltage VIL -0.3 0 +0.8 V DC Characteristics Parameter Symbol Condition Min. Max. Unit Input Leakage Current ILI 0<VI<VCC, Other input pins at V = 0 V -10 +10 A Output Leakage Current ILO 0<VO<VCC -10 +10 A Output "H" Level Voltage VOH IOH = -1 mA 2.4 -- V Output "L" Level Voltage VOL IOL = 2 mA -- 0.4 V Operating Current ICC1 Minimum Cycle Time, Output Open -- 80 mA Standby Current ICC2 Input Pin = VIH/VIL -- 3 mA Capacitance (Ta = 25C, f = 1 MHz) Symbol Max. Unit Input Capacitance (DI, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE) Parameter CI 7 pF Output Capacitance (DO) CO 7 pF 7/19 FEDS81V04166A-01 1Semiconductor MS81V04166A AC Characteristics (VCC = 3.3 V 0.3 V, Ta = 0 to 70C) Parameter Access Time from SRCK DOUT Hold Time from SRCK DOUT Enable Time from SRCK SWCK "H" Pulse Width SWCK "L" Pulse Width Input Data Setup Time Input Data Hold Time WE Enable Setup Time WE Enable Hold Time WE Disable Setup Time WE Disable Hold Time IE Enable Setup Time IE Enable Hold Time IE Disable Setup Time IE Disable Hold Time WE "H" Pulse Width WE "L" Pulse Width IE "H" Pulse Width IE "L" Pulse Width RSTW Setup Time RSTW Hold Time SRCK "H" Pulse Width SRCK "L" Pulse Width RE Enable Setup Time RE Enable Hold Time RE Disable Setup Time RE Disable Hold Time OE Enable Setup Time OE Enable Hold Time OE Disable Setup Time OE Disable Hold Time RE "H" Pulse Width RE "L" Pulse Width OE "H" Pulse Width OE "L" Pulse Width RSTR Setup Time RSTR Hold Time SWCK Cycle Time SRCK Cycle Time Transition Time (Rise and Fall) Symbol tAC tDDCK tDECK tWSWH tWSWL tDS tDH tWENS tWENH tWDSS tWDSH tIENS tIENH tIDSS tIDSH tWWEH tWWEL tWIEH tWIEL tRSTWS tRSTWH tWSRH tWSRL tRENS tRENH tRDSS tRDSH tOENS tOENH tODSS tODSH tWREH tWREL tWOEH tWOEL tRSTRS tRSTRH tSWC tSRC tT MS81V04166A-20 Min. Max. -- 18 6 -- 6 20 9 -- 9 -- 3 -- 4 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 3 -- 5 -- 9 -- 9 -- 3 -- 5 -- 3 -- 5 -- 3 -- 5 -- 3 -- 5 -- 3 -- 5 -- 5 -- 5 -- 3 -- 5 -- 20 -- 20 -- 3 30 MS81V04166A-25 Min. Max. -- 23 6 -- 6 23 12 -- 12 -- 3 -- 4 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- 3 -- 10 -- 12 -- 12 -- 3 -- 5 -- 3 -- 5 -- 3 -- 5 -- 3 -- 5 -- 3 -- 5 -- 5 -- 5 -- 3 -- 10 -- 25 -- 25 -- 3 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8/19 FEDS81V04166A-01 1Semiconductor MS81V04166A AC Characteristics Measuring Conditions Output Compare Level Output Load Input Signal Level 1.5 V / 1.5 V 1 TTL + 30 pF 3.0 V / 0.0 V Input Signal Rise/Fall Time 3 ns Input Signal Measuring Reference Level 1.5 V 1. Input voltage levels for the AC characteristic measurement are VIH = 3.0 V and VIL= 0 V. The transition time tT is defined to be a transition time that signal transfers between VIH = 3.0 V and VIL = 0 V. 2. AC measurements assume tT = 3 ns. 3. Read address must have more than a 150 address delay than write address in every cycle when asynchronous read/write is performed. 4. Read must have more than a 150 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called "new data read". When read has less than a 20 address delay than write, the read data are the data written in a previous series of write cycles which had been written before at last write reset cycle: this is called "old data read". 5. When the read address delay is between more than 21 and less than 149 or more than 262,214, read data will be undetermined. However, normal write is achieved in this address condition. 9/19 FEDS81V04166A-01 1Semiconductor MS81V04166A OPERATION MODE Write Operation Cycle The write operation is controlled by seven control signals, SWCK1, SWCK2, RSTW1, RSTW2, WE1, WE2 and IE1, IE2. Port1 write operation is accomplished by cycling SWCK1, and holding WE1 and IE1 high after the write address pointer reset operation or RSTW1. RSTW1 must be preformed for internal circuit initialization before Write operation. Each write operation, which begins after RSTW1, must contain at least 140 active write cycles, i.e. SWCK1 cycles while WE1 and IE1 are high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW1 operation is required after the last SWCK1 cycle. Note that every write timing of MS81V04166A is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Setting MODE1 to the VSS level starts write data accessing in the cycle in which RSTW1, WE1, and IE1 control signals are input. Setting MODE1 to the VCC level starts write data accessing in the cycle subsequent to the cycle in which RSTW1, WE1, and IE1 control signals are input. These operation are the same for Port1 and Port2. Settings of WE1, 2 and IE1, 2 to the operation mode of Write address pointer and Data input. WE1, 2 IE1, 2 H H H L L X Internal Write address pointer Incremented Halted Data input Input Not input X indicates "don't care" Read Operation Cycle The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1, RE2, and OE1, OE2. Port1 read operation is accomplished by cycling SRCK, and holding RE1 and OE1 high after the read address pointer reset operation or RSTR1. Each read operation, which begins after RSTR1, must contain at least 140 active read cycles, i.e. SRCK cycles while RE1 and OE1 are high. These operations are the same for Port1 and Port2. Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data output. WE1, 2 IE1, 2 H H H L L X L L Internal Write address pointer Incremented Halted Data output Output High impedance Output High impedance 10/19 FEDS81V04166A-01 1Semiconductor MS81V04166A Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 100 s after VCC has stabilized to a value within the range of recommended operating conditions. After this 100 s stabilization interval, the following initialization sequence must be performed. Because the read and write address pointers are undefined after power-up, a minimum of 80 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW1, 2 operation and an RSTR1, 2 operation, to properly initialize the write and the read address pointer. Dummy write cycles/RSTW1, 2 and dummy read cycles/RSTR1, 2 may occur simultaneously. If these dummy read and write operations start while VCC and/or the substrate voltage has not stabilized, it is necessary to perform an RSTR1, 2 operation plus a minimum of 80 SRCK cycles plus another RSTR1, 2 operation, and an RSTW1, 2 operation plus a minimum of 80 SWCK cycles plus another RSTW1, 2 operation to properly initialize read and write address pointers. Old/New Data Access There must be a minimum delay of 150 SWCK cycles between writing into memory and reading out from memory. If reading from the first field starts with an RSTR1, 2 operation, before the start of writing the second field (before the next RSTW1, 2 operation), then the data just written will be read out. The start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 20 SWCK cycles. If the RSTR1, 2 operation for the first field read-out occurs less than 20 SWCK cycles after the RSTW1, 2 operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. The first field of data that is read out while the second field of data is written is called "old data". In order to read out "new data", i.e., the second field written in, the delay between an RSTW1, 2 operation and an RSTR1, 2 operation must be at least 150 SRCK cycles. If the delay between RSTW1, 2 and RSTR1, 2 operations is more than 21 but less than 149 cycles, then the data read out will be undetermined. It may be "old data" or "new data", or a combination of old and new data. Such a timing should be avoided. 11/19 FEDS81V04166A-01 1Semiconductor MS81V04166A TIMING WAVEFORM Write Cycle Timing (Write Reset): MODE1 = VCC 0 cycle n cycle 1 cycle 2 cycle VIH SWCK1, 2 VIL tRSTWS tRSTWH tWSWH tWSWL tSWC RSTW1, 2 tDS VIH VIL tDH VIH DI 10-17/20-27 n-1 n 0 1 2 VIL VIH IE1, 2 VIL VIH WE1, 2 VIL Write Cycle Timing (Write Enable): MODE1 = VCC n cycle Disable cycle Disable cycle n + 1 cycle VIH SWCK1, 2 tWENH tWDSH tWDSS VIL tWENS VIH tWWEL WE1, 2 VIL tWWEH VIH DI 10-17/20-27 n-1 n n+1 VIL VIH IE1, 2 VIL VIH RSTW1, 2 VIL 12/19 FEDS81V04166A-01 1Semiconductor MS81V04166A Write Cycle Timing (Input Enable): MODE1 = VCC n cycle n + 1 cycle n + 3 cycle n + 2 cycle VIH SWCK1, 2 tIENH tIDSH tIDSS VIL tIENS VIH tWIEL IE1, 2 VIL tWIEH VIH DI 10-17/20-27 n-1 n+3 n VIL VIH WE1, 2 VIL VIH RSTW1, 2 VIL Write Cycle Timing (Write Reset): MODE1 = VSS n cycle 1 cycle 0 cycle 2 cycle VIH SWCK1, 2 tRSTWS tRSTWH VIL tWSWH tWSWL VIH tSWC RSTW1, 2 VIL tDS tDH VIH DI 10-17/20-27 n 0 1 2 3 VIL VIH WE1, 2 VIL VIH IE1, 2 VIL 13/19 FEDS81V04166A-01 1Semiconductor MS81V04166A Write Cycle Timing (Write Enable): MODE1 = VSS n cycle Disable cycle n + 1 cycle Disable cycle VIH SWCK1, 2 tWENH tWDSH tWDSS VIL tWENS VIH tWWEL WE1, 2 VIL tWWEH VIH DI 10-17/20-27 n n+1 n VIL VIH IE1, 2 VIL VIH RSTW1, 2 VIL Write Cycle Timing (Input Enable): MODE1 = VSS n cycle n + 1 cycle n + 2 cycle n + 3 cycle VIH SWCK1, 2 tIDSH tIENH tIDSS VIL tIENS tWIEL VIH IE1, 2 VIL tWIEH VIH DI 10-17/20-27 n n n+3 n+4 VIL VIH WE1, 2 VIL VIH RSTW1, 2 VIL 14/19 FEDS81V04166A-01 1Semiconductor MS81V04166A Read Cycle Timing (Read Reset): MODE1 = VCC/VSS n cycle 0 cycle 2 cycle 1 cycle VIH SRCK VIL tRSTRS tRSTRH tWSRH tWSRL VIH tSRC RSTR1, 2 DO 10-17/20-27 VIL tDDCK tAC VIH n-1 n 0 1 2 VIL VIH RE1, 2 VIL VIH OE1, 2 VIL Read Cycle Timing (Read Enable): MODE1 = Vcc/Vss n cycle Disable cycle Disable cycle n + 1 cycle VIH SRCK tRDSH tRENH tRDSS VIL tRENS VIH tWREL RE1, 2 VIL tWREH DO 10-17/20-27 VIH n-1 n n+1 VIL VIH OE1, 2 VIL VIH RSTR1, 2 VIL 15/19 FEDS81V04166A-01 1Semiconductor MS81V04166A Read Cycle Timing (Output Enable): MODE1 = VCC/VSS n cycle n + 1 cycle n + 2 cycle n + 3 cycle VIH SRCK tOENH tODSH tODSS VIL tOENS VIH tWOEL OE1, 2 tDECK VIL tWOEH DO 10-17/20-27 VIH n-1 n Hi-Z n+3 VIL VIH RE1, 2 VIL VIH RSTR1, 2 VIL 16/19 FEDS81V04166A-01 1Semiconductor MS81V04166A PACKAGE DIMENSIONS (Unit: mm) TQFP100-P-1414-0.50-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (5m) 0.55 TYP. 4/Oct. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/19 FEDS81V04166A-01 1Semiconductor MS81V04166A REVISION HISTORY Document No. Date FEDS81V04160A-01 Nov. 21, 2002 Page Previous Current Edition Edition - - Description Final edition 1 18/19 FEDS81V04166A-01 1Semiconductor MS81V04166A NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 19/19