19-2123; Rev 4; 5/08 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface The MAX5741 quad, 10-bit, low-power, buffered voltage-output, digital-to-analog converter (DAC) is packaged in a space-saving 10-pin MAX(R) package (5mm 3mm). The wide supply voltage range of +2.7V to +5.5V and 229A supply current accommodates lowpower and low-voltage applications. DAC outputs employ on-chip precision output amplifiers that swing rail-to-rail. The MAX5741's reference input accepts a voltage range from 0 to VDD. In power-down the reference input is high impedance, further reducing the system's total power consumption. The 20MHz, 3-wire SPITM, QSPITM, MICROWIRETM and DSP-compatible serial interface saves board space and reduces the complexity of opto- and transformer-isolated applications. The MAX5741 on-chip power-on reset (POR) circuit resets the DAC outputs to zero and loads the output with a 100k resistor to ground. This provides additional safety for applications that drive valves or other transducers that need to be off on power-up. The MAX5741's software controlled power-down reduces supply current to less than 1A and provides softwareselectable output loads (1k, 100k, or high impedance) while in power-down. The MAX5741 is specified over the -40C to +125C extended temperature range and available in a 10-pin MAX package Features Ultra-Low Power Consumption 229A at VDD = +3.6V 271A at VDD = +5.5V Wide +2.7V to +5.5V Single-Supply Range 10-Pin MAX Package 0.3A Power-Down Current Guaranteed 10-Bit Monotonicity (1LSB DNL) Safe Power-Up Reset to Zero Volts at DAC Output Three Software-Selectable Power-Down Impedances (100k, 1k, Hi-Z) Fast 20MHz, 3-Wire SPI, QSPI, and MICROWIRECompatible Serial Interface Rail-to-Rail Output Buffer Amplifiers Schmitt-Triggered Logic Inputs for Direct Interfacing to Optocouplers Wide -40C to +125C Operating Temperature Range Ordering Information Applications Automatic Tuning PART TEMP RANGE PIN-PACKAGE Gain and Offset Adjustment MAX5741EUB -40C to +85C 10 MAX Power Amplifier Control MAX5741AUB -40C to +125C 10 MAX Process Control I/O Boards Battery-Powered Instruments VCO Control Pin Configuration TOP VIEW CS 1 Functional Diagram appears at end of data sheet. MAX is a registered trademark of Maxim Integrated Products, Inc. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp. SCLK 2 VDD 3 GND DIN 10 OUTD 9 OUTC 8 OUTB 4 7 OUTA 5 6 REF MAX5741 MAX ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5741 General Description MAX5741 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V OUT_, SCLK, DIN, CS, REF to GND...............-0.3 to (VDD+0.3V) Maximum Continuous Current Into Any Pin......................50mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 6.9 mW/C above +70C) ..........555mW Operating Temperature Range .........................-40C to +125C Junction Temperature........................................-65C to +150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +5V, TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (Note 1) Resolution N 10 Integral Nonlinearity Error INL (Note 2) Differential Nonlinearity Error DNL Guaranteed monotonic (Note 2) Zero-Code Error OE Code = 000 GE Code = 3FF hex 0.5 0.4 Zero-Code Error Tempco Gain Error 4 LSB 1 LSB 1.5 % of FS 2.3 PSRR ppm/C 3 Gain-Error Tempco Power-Supply Rejection Ratio Bits Code = 3FF hex, VDD = 10% % of FS 0.26 ppm/C 58.8 dB REFERENCE INPUT Reference Input Voltage Range VREF Reference Input Impedance RREF Power-Down Reference Current 0 In operation 32 VDD 45 In power-down mode 2 In power-down mode (Note 3) 1 63 V k M 10 A DAC OUTPUT Output Voltage Range No load (Note 4) DC Output Impedance Code = 200 hex 0.8 Short-Circuit Current Wake-Up Time Output Leakage Current 2 0 VDD VDD = +3V 15 VDD = +5V 48 VDD = +3V 8 VDD = +5V 8 Power-down mode = output high impedance 18 _______________________________________________________________________________________ V mA s nA 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +5V, TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS) Input High Voltage VIH VDD = +3V, +5V Input Low Voltage VIL VDD = +3V, +5V Input Leakage Current IIN Digital inputs = 0 or VDD Input Capacitance CIN 0.7 VDD V 0.1 0.3 VDD V 1 A 5 pF DYNAMIC PERFORMANCE Voltage Output Slew Rate SR 0.5 Voltage Output Settling Time 100 hex to 300 hex (Note 3) Digital Feedthrough Any digital inputs from 0 to VDD Digital-Analog Glitch Impulse Major carry transition (Code 1FF hex to Code 200 hex) 4 DAC-to-DAC Crosstalk V/s 10 s 0.15 nV-s 12 nV-s 2.4 nV-s POWER REQUIREMENTS Supply Voltage Range VDD Supply Current with No Load IDD Power-Down Supply Current IDDPD 2.7 5.5 V All digital inputs at 0 or VDD = 3.6V 230 395 All digital inputs at 0 or VDD = 5.5V 270 420 All digital inputs at 0 or VDD = 5.5V 0.29 1 A TYP MAX UNITS 20 MHz A TIMING CHARACTERISTICS (VDD = 2.7V to 5.5V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN SCLK Clock Frequency f SCLK 0 SCLK Pulse Width High tCH 25 ns SCLK Pulse Width Low tCL 25 ns CS Fall to SCLK Rise Setup Time tCSS 10 ns SCLK Fall to CS Rise Setup Time tCSH 10 ns tDS 15 ns tDH 0 ns tCSW 80 ns DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time CS Pulse Width High Note 1: Note 2: Note 3: Note 4: Note 5: DC specifications are tested without output loads. Linearity guaranteed from code 29 to code 995. Limited with test conditions. Offset and gain error limit the FSR. Guaranteed by design. _______________________________________________________________________________________ 3 MAX5741 ELECTRICAL CHARACTERISTICS (continued) __________________________________________Typical Operating Characteristics (VREF = VDD, TA = +25C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. CODE, TA = +25C 0.15 2 0.10 VDD = +3V DNL (LSB) 0 -1 VDD = +5V -0.05 -0.15 -3 -4 -9 -14 VDD = +3V AND +5V -19 -0.20 -24 -0.25 -4 256 512 768 1024 0 256 512 768 0 1024 256 512 768 CODE CODE CODE INTEGRAL NONLINEARITY vs. CODE, TA = +40C DIFFERENTIAL NONLINEARITY vs. CODE, TA = -40C TOTAL UNADJUSTED ERROR vs. CODE, TA = -40C 0.15 2 0.10 VDD = +5V DNL (LSB) 1 0 -1 VDD = +3V 0.05 0 -0.05 -0.10 -2 -0.15 -3 1 1024 MAX5741 toc06 3 0.20 TOTAL UNADJUSTED ERROR (%) 0.25 MAX5741 toc04 4 MAX5741 toc05 0 -4 VDD = +3V AND +5V -9 -14 -19 -0.20 -0.25 -4 256 512 768 -24 0 1024 256 512 768 0 1024 256 512 768 CODE CODE CODE INTEGRAL NONLINEARITY vs. CODE, TA = +125C DIFFERENTIAL NONLINEARITY vs. CODE, TA = +125C TOTAL UNADJUSTED ERROR vs. CODE, TA = +125C 0.25 MAX5741 toc07 4 3 0.20 0.15 2 0.10 VDD = +3V DNL (LSB) 1 0 -1 VDD = +5V 0.05 0 -0.05 -0.10 -2 -0.15 -3 1 1024 MAX5741 toc09 0 TOTAL UNADJUSTED ERROR (%) INL (LSB) 0 -0.10 -2 -4 VDD = +3V AND +5V -9 -14 -19 -0.20 -4 -0.25 0 256 512 CODE 4 0.05 MAX5741 toc08 INL (LSB) 1 1 MAX5741 toc03 0.20 TOTAL UNADJUSTED ERROR (%) 0.25 MAX5741 toc02 3 TOTAL UNADJUSTED ERROR vs. CODE, TA = +25C DIFFERENTIAL NONLINEARITY vs. CODE, TA = +25C MAX5741 toc01 4 INL (LSB) MAX5741 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface 768 1024 -24 0 256 512 CODE 768 1024 0 256 512 CODE _______________________________________________________________________________________ 768 1024 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface SOURCE-AND-SINK CURRENT CAPABILITY (VDD = +3V) 3 CODE = 3FF HEX, SOURCING CURRENT FROM OUT_ 2.5 0 -1 MINIMUM DNL 1.5 CODE = 100 HEX, SINKING CURRENT INTO OUT_ 1.0 MINIMUM INL -2 -4 0 20 40 60 80 100 120 1.5 CODE = 000 HEX, SINKING CURRENT INTO OUT_ CODE = 100 HEX, SINKING CURRENT INTO OUT_ CODE = 000 HEX, SINKING CURRENT INTO OUT_ 0.5 0 0 2 TEMPERATURE (C) 4 6 8 10 12 14 16 0 2 4 ISOURCE/SINK (mA) 8 10 12 14 16 POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 250 CODE = 3FF HEX 210 190 170 150 MAX5741 toc14 270 300 POWER-DOWN SUPPLY CURRENT (nA) MAX5741 toc13 290 230 6 ISOURCE/SINK (mA) SUPPLY CURRENT vs. SUPPLY VOLTAGE 250 200 150 100 50 0 2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. CS INPUT VOLTAGE SUPPLY CURRENT vs. TEMPERATURE 290 MAX5741 toc15 900 800 600 VDD = +5V 500 400 300 VDD = +3V 200 280 SUPPLY CURRENT (A) 700 5.2 MAX5721 toc16 SUPPLY CURRENT (A) CODE = 300 HEX, SOURCING CURRENT FROM OUT_ 2.5 2.0 0 -40 -20 VDD = 5V 3.0 1.0 0.5 -3 4.0 3.5 CODE = 300 HEX, SOURCING CURRENT FROM OUT_ 2.0 MAXIMUM INL CODE = 3FF HEX, SOURCING CURRENT FROM OUT_ 4.5 VOUT (V) MAXIMUM DNL VOUT (V) 1 SUPPLY CURRENT (A) INL AND DNL (LSB) 2 5.0 MAX5741 toc11 3.0 MAX5741 toc10 4 SOURCE-AND-SINK CURRENT CAPABILITY (VDD = +5V) MAX5742 toc12 WORST-CASE INL AND DNL vs. TEMPERATURE 270 VDD = +5.5V 260 250 240 230 220 VDD = +3.6V 210 100 200 0 0 1 2 3 4 CS INPUT VOLTAGE (V) 5 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) _______________________________________________________________________________________ 5 MAX5741 Typical Operating Characteristics (continued) (VREF = VDD, TA = +25C, unless otherwise noted.) MAX5741 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface Typical Operating Characteristics (continued) (VREF = VDD, TA = +25C, unless otherwise noted.) FULL-SCALE SETTLING TIME (VDD = +5V) FULL-SCALE SETTLING TIME (VDD = +5V) MAX5741 toc17 MAX5741 toc18 VSCLK 5V/div VSCLK 5V/div VOUT_ 1V/div VOUT_ 1V/div CODE 000 TO 3FF HEX RL = 5k CL = 200pF CODE 3FF HEX TO 000 RL = 5k CL = 200pF 1s/div 1s/div HALF-SCALE SETTLING TIME (VDD = +3V) HALF-SCALE SETTLING TIME (VDD = +3V) MAX5741 toc19 MAX5721 toc20 VSCLK 5V/div VSCLK 5V/div VOUT_ 1V/div VOUT_ 1V/div CODE 100 HEX TO 300 HEX RL = 5k CL = 200pF CODE 300 HEX TO 100 HEX RL = 5k CL = 200pF 1s/div 1s/div EXITING POWER-DOWN (VDD = +5V) DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +5V) MAX5741 toc22 MAX5741 toc21 VSCLK 5V/div CODE 200 HEX 5s/div 6 SCLK, fSCLK = 500kHz 2V/div VOUT_ 1V/div CODE 1FF HEX TO 200 HEX VOUT_ AC-COUPLED, 20mV/div 1s/div _______________________________________________________________________________________ 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +5V) DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +3V) MAX5741 toc24 MAX5741 toc23 CODE 1FF HEX TO 200 HEX SCLK, fSCLK = 500kHz, 2V/div SCLK, fSCLK = 500kHz, 2V/div VOUT_ AC-COUPLED, 50mV/div VOUT_ AC-COUPLED, 50mV/div CODE 200 HEX TO 1FF HEX 1s/div 1s/div POWER-ON RESET, FAST RISE TIME (VDD = +5V) DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +3V) MAX5741 toc26 MAX5741 toc25 SCLK, fSCLK = 500kHz, 1V/div CODE 200 HEX TO 1FF HEX VDD 2V/div VOUT_ AC-COUPLED, 20mV/div VDD RISE TIME = 20s 20s/div 1s/div POWER-ON RESET, FAST RISE TIME (VDD = +3V) POWER-ON RESET, SLOW RISE TIME (VDD = +5V) MAX5741 toc28 MAX5741 toc27 VDD RISE TIME = 76s VDD 2V/div VDD 2V/div VDD RISE TIME = 20s VOUT_ AC-COUPLED, 10mV/div VOUT_ AC-COUPLED, 2mV/div 40s/div VOUT_ AC-COUPLED, 10mV/div 20s/div _______________________________________________________________________________________ 7 MAX5741 Typical Operating Characteristics (continued) (VREF = VDD, TA = +25C, unless otherwise noted.) MAX5741 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface Typical Operating Characteristics (continued) (VDD = +3V, VREF = VDD, TA = +25C, unless otherwise noted.) POWER-ON RESET, SLOW RISE-TIME (VDD = +3V) CLOCK FEEDTHROUGH (VDD = +5V) MAX5741 toc29 MAX5741 toc30 VDD 2V/div SCLK, 2V/div VDD RISE TIME = 72s VOUT_, AC-COUPLED 1mV/div VOUT_ AC-COUPLED 2mV/div 2s/div CODE 200 HEX, fSCLK = 50kHz 40s/div LINE TRANSIENT RESPONSE (VDD = +5V) CLOCK FEEDTHROUGH (VDD = +3V) MAX5741 toc31 MAX5741 toc32 SCLK, 2V/div VDD, AC-COUPLED, 100mV/div VOUT_, AC-COUPLED 1mV/div VOUT_ AC-COUPLED, 10mV/div 2s/div CODE 200 HEX, fSCLK = 50kHz 20s/div LINE TRANSIENT RESPONSE (VDD = +3V) CROSSTALK (VDD = +5V) MAX5741 toc34 MAX5741 toc33 VDD, AC-COUPLED, 100mV/div VOUTA, 2V/div CODE 3FF HEX TO 008 HEX VOUTB, AC-COUPLED 1mV/div VOUT_ AC-COUPLED, 10mV/div 20s/div 8 2s/div _______________________________________________________________________________________ 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface PIN NAME FUNCTION 1 CS Chip-Select Input 2 SCLK Serial Clock Input 3 VDD Power-Supply Input 4 GND Ground 5 DIN Serial Data Input 6 REF External Reference Voltage Input 7, 8, 9, 10 OUTA-OUTD DAC Voltage Outputs. Power-on reset sets DAC registers to zero, and internally connects OUT to GND with 100k resistor. Detailed Description The MAX5741 contains four 10-bit, voltage-output, lowpower digital-to-analog converters (DACs). Each DAC employs a resistor word string architecture that converts a 10-bit digital input word to an equivalent analog output voltage proportional to the applied reference voltage. The MAX5741 shares one reference input (REF) between all four DACs. The MAX5741 includes rail-to-rail output buffer amplifiers for each DAC, and input logic for simple microprocessor (P), and CMOS interfaces. The power-supply range is from +2.7V to +5.5V (Functional Diagram). The MAX5741's reference input accepts a voltage range from 0 to VDD. In powerdown mode the reference input is high impedance. The MAX5741 is compatible with the 3-wire SPI, QSPI, MICROWIRE, and DSP serial interface with Schmitt-triggered logic inputs. Reference Input and DAC Output Range The reference input accepts positive DC and AC signals. The voltage at REF sets the full-scale output voltage of the four DACs. The reference input voltage range is 0 to VDD. The impedance at REF is 45k. The voltage at REF can vary from GND to VDD. The output voltages (VOUT_) are represented by a digitally programmable voltage source as: VOUT_ = (VREF D) / 210 where D is the decimal equivalent of binary DAC input code ranging from 0 to 1023. VREF is the voltage at REF. Output Buffer Amplifiers All DACs are internally buffered at the output. The buffer amplifiers have both rail-to-rail common mode and (GND to VREF) output voltage range. The buffers are unity-gain stable with CL = 200pF and RL = 5k. Buffer amplifiers are disabled during power-up and individual DAC outputs are shorted to GND through a 100k resistor. Buffer amplifiers can individually or altogether be powered-down by programming the input register control bits. During power down, contents of the input and DAC registers remain the same. On wake-up all DAC outputs are restored to their prepower down voltage values. Power-Down Mode In power-down mode, the DAC outputs are programmed to one of three output states, 1k, 100k, or floating (Table 1). The REF input is high impedance (2M typ) to conserve current drain from the system reference; therefore, the system reference does not have to be powered-down. The DAC outputs return to the values contained in the registers when brought out of power-down. The recovery time, from total powerdown to power-up, is 8s. This extra time is needed to allow the internal bias to wake-up. Power-down mode reduces current consumption to 0.3A. 3-Wire Serial Interface The MAX5741 digital interface is a standard 3-wire connection compatible with SPI/QSPI/MICROWIRE/DSP interfaces. The chip-select input (CS) frames the serial data loading at DIN. Immediately following CS high-tolow transition, the data is shifted synchronously and latched into the input register on the falling edge of the serial clock input (SCLK). After 16 bits have been loaded into the serial input register, it transfers its con- _______________________________________________________________________________________ 9 MAX5741 Pin Description MAX5741 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface Table 1. Power-Down Mode Control EXTENDED CONTROL DATA BITS DESCRIPTION FUNCTION C3 C2 C1 C0 D9-D3 D2 D1 D0 S1 S0 1 1 1 1 X 0 0 0 0 0 DAC A DAC O/P, wake-up 1 1 1 1 X 0 0 0 0 1 DAC A Floating output 1 1 1 1 X 0 0 0 1 0 DAC A Output is terminated with 1k 1 1 1 1 X 0 0 0 1 1 DAC A Output is terminated with 100k 1 1 1 1 X 0 0 1 0 0 DAC B DAC O/P, wake-up 1 1 1 1 X 0 0 1 0 1 DAC B Floating output 1 1 1 1 X 0 0 1 1 0 DAC B Output is terminated with 1k 1 1 1 1 X 0 0 1 1 1 DAC B Output is terminated with 100k 1 1 1 1 X 0 1 0 0 0 DAC C DAC O/P, wake-up 1 1 1 1 X 0 1 0 0 1 DAC C Floating output 1 1 1 1 X 0 1 0 1 0 DAC C Output is terminated with 1k 1 1 1 1 X 0 1 0 1 1 DAC C Output is terminated with 100k 1 1 1 1 X 0 1 1 0 0 DAC D DAC O/P, wake-up 1 1 1 1 X 0 1 1 0 1 DAC D Floating output 1 1 1 1 X 0 1 1 1 0 DAC D Output is terminated with 1k 1 1 1 1 X 0 1 1 1 1 DAC D Output is terminated with 100k 1 1 1 1 X 1 0 0 0 0 DAC A-D DAC O/P, wake-up 1 1 1 1 X 1 0 0 0 1 DAC A-D Floating output 1 1 1 1 X 1 0 0 1 0 DAC A-D Output is terminated with 1k 1 1 1 1 X 1 0 0 1 1 DAC A-D Output is terminated with 100k X = Don't Care tents to the DAC latch. CS may then either be held low or brought high. CS must be brought high for a minimum of 80ns before the next write sequence, since a write sequence is initiated on a falling edge of CS. Not keeping CS low during the first 15 SCLK cycles discards input data. The serial clock (SCLK) can idle either high or low between transitions. The MAX5741 has two internal registers per DAC, the input register and the DAC register. The input register holds the data that is waiting to be shifted to the DAC register. All four input registers can be loaded without updating the output. This function is useful when all outputs need to be updated at the same time. The input register can be made transparent. When the input register is transparent, the data written into DIN loads directly to the DAC register and the output is updated. 10 The DAC output is not updated until data is written to the DAC register. See Table 2 for a list of serial-interface programming commands. Power-On Reset (POR) The MAX5741 has an internal POR circuit. At power-up all DACs are powered-down and OUT_ is terminated to GND through 100k resistors. Contents of input and DAC registers are cleared to all zero. 8s recovery time after issuing a wake-up command is needed before writing to the DAC registers. Power-down mode control commands can be applied immediately with no recovery time. C3-C0 are control bits. The data bits D9 to D0 are in straight binary format. Set bits S1 and S0 to zero. All zeros correspond to zero scale and all ones correspond to full scale. ______________________________________________________________________________________ 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface D9 (MSB) C3 C2 C1 C0 D9 D8 D0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 Figure 1. 16-Bit Input Word tCH SCLK tCL tCSW tCSS tDH tCSH tDS CS DIN C3 SO Figure 2. Timing Diagram Digital Inputs The digital inputs are compatible with CMOS logic. In order to save power and reduce input to output coupling, SCLK and DIN input buffers are powered down immediately after completion of shifting 16 bits into the input shift register. A high to low transition at CS powers up SCLK and DIN input buffers. Applications Information Unipolar Output The typical application circuit (Figure 3) shows the MAX5741 configured for a unipolar output, where the output voltages and the reference inputs have the same polarity. Table 3 lists the unipolar output codes. Bipolar Output The MAX5741 can be configured for bipolar operation using a dual supply op amp (Figure 4). The transfer function for bipolar operation is: 2D VOUT = VREF - 1 1024 ______________________________________________________________________________________ 11 MAX5741 CONTENTS OF INPUT SHIFT MAX5741 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface Table 2. Serial-Interface Programming Commands CONTROL DATA BITS DAC FUNCTION X A Input register transparent, data shifted directly to DAC register, OUTA updated X B Input register transparent, data shifted directly to DAC register, OUTB updated X X C Input register transparent, data shifted directly to DAC register, OUTC updated X X D Input register transparent, data shifted directly to DAC register, OUTD updated 0 X X A Data shifted to input register, OUTA unchanged 0 1 X X B Data shifted to input register, OUTB unchanged 1 0 X X C Data shifted to input register, OUTC unchanged 1 1 1 X X D Data shifted to input register, OUTD unchanged 1 0 0 0 X X A Shift data from input register to DAC register, OUTA updated 1 0 0 1 X X B Shift data from input register to DAC register, OUTB updated 1 0 1 0 X X C Shift data from input register to DAC register, OUTC updated 1 0 1 1 X X D Shift data from input register to DAC register, OUTD updated 1 1 0 0 X X A-D Input registers transparent, data shifted directly to DAC registers, OUTA-OUTD updated 1 1 0 1 X X A-D Data shifted to input registers, OUTA-OUTD unchanged 1 1 1 0 X X A-D Shift data from input registers to DAC registers, OUTA-OUTD updated C3 C2 C1 C0 D9-D0 S1-S0 0 0 0 0 X 0 0 0 1 X 0 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 X = Don't Care R1 +2.7V TO +5.5V R2 +2.7V TO +5.5V REF VDD REF OUT IN OUT_ DAC_ VDD VOUT DAC_ MAX6050 OUT_ V- GND GND MAX5741 Figure 3. Typical Operating Circuit, Unipolar Output 12 V+ MAX5741 Figure 4. Bipolar Output Circuit ______________________________________________________________________________________ R1 = R2 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface Table 4. Bipolar Code Table DAC CONTENTS ANALOG OUTPUT DAC CONTENTS ANALOG OUTPUT 1111 1111 1100 1023 VREF 1024 1111 1111 1100 511 + VREF 512 1000 0000 0100 513 VREF 1024 1000 0000 0100 1 + VREF 512 1000 0000 0000 0 1000 0000 0000 VREF 2 511 VREF 1024 0111 1111 1100 0000 0000 0100 1 VREF 1024 0000 0000 0000 0 1 512 0111 1111 1100 - VREF 0000 0000 0100 - VREF 511 512 - VREF 0000 0000 0000 Chip Information TRANSISTOR COUNT: 14458 PROCESS: BiCMOS MAX5741 Table 3. Unipolar Code Table Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10 MAX U10CN-1 21-0061 ______________________________________________________________________________________ 13 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface MAX5741 Functional Diagram VDD REF INPUT REGISTER A DAC REGISTER A 10-BIT DAC OUTPUT BUFFER OUTA RESISTOR NETWORK INPUT REGISTER B DAC REGISTER B 10-BIT DAC OUTPUT BUFFER OUTB RESISTOR NETWORK INPUT REGISTER C DAC REGISTER C 10-BIT DAC OUTPUT BUFFER OUTC RESISTOR NETWORK INPUT REGISTER D DAC REGISTER D 10-BIT DAC OUTPUT BUFFER OUTD RESISTOR NETWORK INPUT CONTROL LOGIC AND SHIFT REGISTER POWER-DOWN CONTROL LOGIC MAX5741 CS 14 SCLK DIN GND ______________________________________________________________________________________ 10-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface REVISION NUMBER REVISION DATE 4 5/08 DESCRIPTION Corrected labeling in two TOCs PAGES CHANGED 5 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX5741 Revision History