General Description
The MAX1426 10-bit, monolithic analog-to-digital con-
verter (ADC) is capable of a 10Msps sampling rate. This
device features an internal track-and-hold (T/H) amplifier
for excellent dynamic performance; at the same time, it
minimizes the number of external components. Low
input capacitance of only 8pF minimizes input drive
requirements. A wide input bandwidth (up to 150MHz)
makes this device suitable for digital RF/IF downconvert-
er applications employing undersampling techniques.
The MAX1426 employs a differential pipelined architec-
ture with a wideband T/H amplifier to maximize through-
put while limiting power consumption to only 156mW.
The MAX1426 generates an internal +2.5V reference
that supplies three additional reference voltages
(+3.25V, +2.25V, and +1.25V). These reference volt-
ages provide a differential input range of +2V to -2V.
The analog inputs are biased internally to correct the
DC level, eliminating the need for external biasing on
AC-coupled applications.
A separate +3V digital logic supply input allows for
separation of digital and analog circuitry. The output
data is in two’s complement format. The MAX1426 is
available in the space-saving 28-pin SSOP package.
For a pin-compatible version at a higher data rate, refer
to the MAX1424 or MAX1425
Applications
Medical Ultrasound Imaging
CCD Pixel Processing
IR Focal Plane Array
Radar
IF and Baseband Digitization
Set-Top Boxes
Features
oDifferential Inputs for High Common-Mode
Noise Rejection
o61dB Signal-to-Noise Ratio (at fIN = 2MHz)
oInternal +2.5V Reference
o150MHz Input Bandwidth
oWide ±2V Input Range
oLow Power Consumption: 156mW
oSeparate Digital Supply Input for 3V Logic
Compatibility
oSingle +5V Operation Possible
MAX1426
10-Bit, 10Msps ADC
________________________________________________________________
Maxim Integrated Products
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D0
D1
D2
D3
D4
DGND
D9
DVDD
DGND
DVDD
D5
D6
D7
D8
OE/PD
CLK
CMLN
CMLP
INN
INP
AVDD
AGND
CML
REFN
REFIN
REFP
AVDD
AGND
SSOP
TOP VIEW
MAX1426
+
CLK
INP
INTERFACE
PIPELINE ADC
REF SYSTEM +
BIAS
OUTPUT
DRIVERS
REF
REFIN REFP CML REFN OE/PD
AVDD
AGND
DVDD
DGND
D9–D0
INN
T/H
MAX1426
Functional Diagram
19-1598 Rev 1; 7/11
PART
MAX1426CAI+
MAX1426EAI+ -40°C to +85°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
28 SSOP
28 SSOP
Pin Configuration
Ordering Information
+
Denotes a lead(Pb)-free/RoHS-compliant package.
Devices are also available in a tape-and-reel package.
Specify tape and reel by adding “T” to the number when order-
ing.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1426
10-Bit, 10Msps ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0V, internal reference, digital output loading 35pF, fCLK =
10MHz (50% duty cycle), TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND ........................................................ -0.3V to +6V
DVDD to DGND ....................................................... -0.3V to +6V
AVDD to DGND........................................................ -0.3V to +6V
DGND to AGND ................................................................. ±0.3V
REFP, REFIN, REFN, CMLN, CMLP,
CML, INP, INN .....................(VAGND - 0.3V) to (V
AVDD + 0.3V)
CLK, OE/PD, D0–D9 ...............(VDGND - 0.3V) to (VDVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
28-Pin SSOP (derated 9.5mW/°C above +70°C) .........762mW
Operating Temperature Ranges
MAX1426CAI ..................................................... 0°C to +70°C
MAX1426EAI................................................... -40°C to +85°C
Maximum Junction Temperature .................................... +150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
58 60
f = 2MHz
-70 -67
f = 2MHz
%FSR
%FSR
f = 2MHz
(Note 4)
External reference (REFP, CML, REFN)
(Note 3)
External reference (REFIN) (Note 2)
Guaranteed monotonic
(Note 1)
Internal reference (Note 1)
f = 2MHz
CONDITIONS
SINADSignal-to-Noise and Distortion
dBTHD
Total Harmonic Distortion
(first five harmonics)
dB
69 72
SFDRSpurious-Free Dynamic Range
dB
60 61
SNRSignal-to-Noise Ratio
LSB
-1 1
DNLDifferential Nonlinearity
Bits
10
RESResolution
mV/V
-5 ±2 +5
PSRRPower-Supply Rejection Ratio
-5 ±3 5
-5 ±2 5
LSB
-1.5 ±0.3 1.5
INLIntegral Nonlinearity
No Missing Codes
-3 ±1.0 3
MSOMidscale Offset
-10 ±5 10
GEGain Error
UNITSMIN TYP MAXSYMBOLPARAMETER
dB
ACCURACY
DYNAMIC PERFORMANCE (AIN = -1.0dBFS)
MAX1426
10-Bit, 10Msps ADC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0V, internal reference, digital output loading 35pF, fCLK =
10MHz (50% duty cycle), TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
f = 2MHz
CONDITIONS
Bits
9.3 9.7
ENOBEffective Number of Bits
UNITSMIN TYP MAXSYMBOL PARAMETER
f1 = 1.98MHz, f2 = 2.00MHz
(-7dB FS, each tone) (Note 5) dBc
-70
IMDIntermodulation Distortion
(Note 7)
(Note 7)
VINP - VINN
CML (Note 6)
Either input to ground
Either input to ground
MHz150LSBWLarge-Signal Bandwidth
MHz400SSBWSmall-Signal Bandwidth
V±2DRDifferential Input Range
V
2.25
±10%
VCMVR
Input Common-Mode Voltage
Range
pF
8
CIN
Input Capacitance
kΩ
3.5
RIN
Input Resistance
REFP, CML, REFN
REFP, CML, REFN
VREFP - VREFN
REFIN
REFIN (Note 8)
V
1.25
±10%
REFN Input Range
V
2.25
±10%
CML Input Range
V
3.25
±10%
REFP Input Range
pF
15
CIN
Input Capacitance
µA
-325 +325
IIN
Input Current
V
2.0
Differential Reference
pF
10
CIN
Input Capacitance
kΩ
6.5
RIN
Input Resistance
VREFP - VREFN, TA = +25°C V
1.9 2.0 2.1
Differential Reference
V
1.25
VREFN
Negative Reference Input
Voltage
V
2.25
VCML
Common-Mode Reference
Voltage
V
3.25
VREFP
Positive Reference Voltage
ppm/°C±50
Differential Reference
Temperature Coefficient
REFERENCE OUTPUTS (REFP, CML, REFN; external +2.5V reference)
REFERENCE (VREFIN = 0; REFP, REFN, CML applied externally)
ANALOG INPUT (INP, INN, CML)
MAX1426
10-Bit, 10Msps ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0V, internal reference, digital output loading 35pF, fCLK =
10MHz (50% duty cycle), TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1) V
3.25
VREFP
Positive Reference
(Note 1) V
2.25
VCML
Common-Mode Reference
Voltage
OE/PD = DVDD
VDVDD = 5.25V, OE/PD = DVDD
IOL = 200µA, VDVDD = 2.7V
IOH = -200µA, VDVDD = 2.7V
VREFP - VREFN, TA = +25°C
VDVDD < 4.75V
VDVDD > 4.75V
OE/PD = DVDD
VDVDD = 5.0V
REFIN = AGND
OE/PD = DVDD
VDVDD < 4.75V
VDVDD = 3.3V
VDVDD > 4.75V
CONDITIONS
pFThree-State Capacitance
µAThree-State Leakage
VVOL
Output Logic Low
VVOH
Output Logic High
pFInput Capacitance
0.3 ×
VDVDD
V
0.8
VIL
Input Logic Low
0.7 ×
VDVDD
V
2.4
VIH
Input Logic High
ppm/°C
±150
Differential Reference
Temperature Coefficient
V
1.8 2 2.2
Differential Reference
mW
156 210
PDPower Dissipation
µA
40 150
Digital Shutdown Current
5.3 8
mA
25 35
Analog Supply Current with
Internal Reference in Shutdown
mA
0.6 1
Analog Shutdown Current
mA
3.3 6
IDVDD
Digital Supply Current
UNITSMIN TYP MAXSYMBOL PARAMETER
V
2.7 3.3 5.5
VDVDD
Digital Supply Voltage
V
4.75 5.00 5.25
VAVDD
Analog Supply Voltage
mA
29 38
IAVDD
Analog Supply Current
(Note 1) V
1.25
VREFN
Negative Reference
VDVDD = 5.25V µA-20 20
µA-10 10
Input Current Leakage
10
VDVDD VDVDD
- 0.5
0.5
-10 10
10
ICLK
IOE/PD
REFERENCE OUTPUT (REFP, CML, REFN; internal +2.5V reference)
POWER SUPPLY
DIGITAL INPUTS (CLK, OE/PD)
DIGITAL OUTPUTS (D0–D9)
MAX1426
10-Bit, 10Msps ADC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0V, internal reference, digital output loading 35pF, fCLK =
10MHz (50% duty cycle), TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1: Internal reference, REFIN bypassed to AGND with a 0.1µF capacitor.
Note 2: External +2.5V reference applied to REFIN.
Note 3: Internal reference disabled. VREFIN = 0, VREFP = 3.25V, VCML = 2.25V, and VREFN = 1.25V.
Note 4: Measured as the ratio of the change in midscale offset voltage for a ±5% change in VAVDD using the internal reference.
Note 5: IMD is measured with respect to either of the fundamental tones.
Note 6: Specifies the common-mode range of the differential input signal supplied to the MAX1426.
Note 7: Defined as the input frequency at which the fundamental component of the output spectrum is attenuated by 3dB.
Note 8: VREFIN is internally biased to +2.5V through a 5kΩresistor.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
10 20 ns
ns10 20
Bus Enable
Bus Disable
Data Output Delay ns52025tOD
Aperture Jitter ps7tAJ
Aperture Delay ns5tAD
Pipeline Delay (Latency) cycles5.5
Clock Low ns40 50 60Figure 4tCL
Clock High ns40 50 60Figure 4tCH
Clock Frequency MHz10fCLK
Conversion Rate MHz0.1 10CONV
TIMING CHARACTERISTICS
MAX1426
10-Bit, 10Msps ADC
6 _______________________________________________________________________________________
Typical Operating Characteristics
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0V, internal reference, digital output load = 35pF, fCLK = 10MHz (50%
duty cycle), for dynamic performance 0dB is full scale, TA= +25°C, unless otherwise noted.)
-1.2
-0.6
-0.8
-1.0
-0.4
-0.2
0
0.2
0.4
0.6
0.8
0400200 600 800 1000
INTEGRAL NONLINEARITY vs. CODE
MAX1426-01
CODE
INL (LSB)
fINP = 2MHz
-0.6
-0.2
-0.4
0
0.2
0.4
0.6
0400200 600 800 1000
DIFFERENTIAL NONLINEARITY vs. CODE
MAX1426-02
CODE
DNL (LSB)
fINP = 2MHz
-8.0
-6.0
-7.0
-5.0
-4.0
-3.0
-2.0
-1.0
0
0.01 10.1 10 100 1000 10,000
ANALOG INPUT BANDWIDTH
(FULL POWER)
MAX1426-03
BANDWIDTH (MHz)
AMPLITUDE (dB)
-140
-100
-120
-60
-80
-20
-40
0
0 2.01.0 3.0 4.00.5 2.51.5 3.5 4.5 5.0
INTERMODULATION DISTORTION
MAX1426-04
FREQUENCY (MHz)
MAGNITUDE (dB)
fCLK = 10MHz
f1 = 1.98MHz
f2 = 2.00MHz
0
20
10
30
50
40
60
70
SIGNAL-TO-NOISE RATIO
vs. POWER (fIN = 1.997MHz)
MAX1426-07
INPUT (dB)
SNR (dB)
-60 -30-45 -15 0
0
20
40
60
80
SIGNAL-TO-NOISE PLUS DISTORTION
vs. POWER (fIN = 1.997MHz)
MAX1426-05
INPUT (dB)
SINAD (dB)
-60 -30-45 -15 0
0
20
40
60
80
SIGNAL-TO-NOISE RATIO PLUS DISTORTION
vs. POWER (fIN = 4.942MHz)
MAX1426-06
INPUT (dB)
SINAD (dB)
-60 -30-45 -15 0
0
20
10
30
50
40
60
70
SIGNAL-TO-NOISE RATIO
vs. POWER (fIN = 4.942MHz)
MAX1426-08
INPUT (dB)
SNR (dB)
-60 -30-45 -15 0
0
20
10
30
60
50
40
70
80
SPURIOUS-FREE DYNAMIC RANGE
vs. POWER (fIN = 1.997MHz)
MAX1426-09
INPUT (dB)
SFDR (dB)
-60 -30-45 -15 0
MAX1426
10-Bit, 10Msps ADC
_______________________________________________________________________________________
7
0
20
40
60
80
SPURIOUS-FREE DYNAMIC RANGE
vs. POWER (fIN = 9.942MHz)
MAX1426-10
INPUT (dB)
SFDR (dB)
-60 -30-45 -15 0
-80
-60
-40
-20
0
TOTAL HARMONIC DISTORTION
vs. POWER (fIN = 1.997MHz)
MAX1426-11
INPUT (dB)
THD (dB)
-60 -30-45 -15 0
-80
-60
-40
-20
0
TOTAL HARMONIC DISTORTION
vs. POWER (fIN = 4.942MHz)
MAX1426-12
INPUT (dB)
THD
(dB)
-60 -30-45 -15 0
0
2
4
6
8
10
EFFECTIVE NUMBER OF BITS
vs. POWER (fIN = 1.997MHz)
MAX1426-13
INPUT (dB)
ENOB (bits)
-60 -30-45 15 0
57
58
59
60
SIGNAL-TO-NOISE RATIO
vs. INPUT FREQUENCY
MAX1426-16
INPUT FREQUENCY (MHz)
SNR (dB)
23 4 5
0
2
4
6
8
10
EFFECTIVE NUMBER OF BITS
vs. POWER (fIN = 4.942MHz)
MAX1426-14
INPUT (dB)
ENOB (bits)
-60 -30-45 15 0 8.0
8.4
8.8
9.2
9.6
10.0
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
MAX1426-15
INPUT FREQUENCY (MHz)
ENOB (bits)
23 4 5
-75
-74
-73
-72
-71
-70
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCY
MAX1426-17
INPUT FREQUENCY (MHz)
THD
(dB)
23 4 5
57
58
59
60
61
SIGNAL-TO-NOISE PLUS DISTORTION
vs. INPUT FREQUENCY
MAX1426-18
INPUT FREQUENCY (MHz)
SINAD (dB)
23 4 5
Typical Operating Characteristics (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0V, internal reference, digital output load = 35pF, fCLK = 10MHz (50%
duty cycle), for dynamic performance 0dB is full scale, TA= +25°C, unless otherwise noted.)
MAX1426
10-Bit, 10Msps ADC
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0V, internal reference, digital output load = 35pF, fCLK = 10MHz (50%
duty cycle), for dynamic performance 0dB is full scale, TA= +25°C, unless otherwise noted.)
-140
-100
-120
-60
-80
-20
-40
0
0 2.01.0 3.0 4.00.5 2.51.5 3.5 4.5 5.0
FFT PLOT (fIN = 2MHz)
MAX1426-19
FREQUENCY (MHz)
MAGNITUDE (dB)
24
28
36
32
40
44
0.60
0.65
0.75
0.70
0.80
0.85
-40 -15 10 35 60 85
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
MAX1426-21
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
SHUTDOWN CURRENT (mA)
OE/PD = L
SHUTDOWN
REFIN = AGND
REFIN = GND
-140
-100
-120
-60
-80
-20
-40
0
042681537910
FFT PLOT (fIN = 5MHz)
MAX1426-20
FREQUENCY (MHz)
MAGNITUDE (dB)
2.08
2.10
2.14
2.12
2.16
2.18
-40 -15 10 35 60 85
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1426-22
TEMPERATURE (°C)
INTERNAL REFERENCE (V)
MAX1426
10-Bit, 10Msps ADC
_______________________________________________________________________________________ 9
Pin Description
Common-Mode Level Positive Input. For AC applications, connect to AVDD to internally set the input
DC bias level. For DC-coupled applications, connect to AGND.
CMLP11
Common-Mode Level Negative Input. Connect to AGND to internally set the input DC bias level for
both AC- and DC-coupled applications.
CMLN12
Clock Input. Clock frequency range from 0.1MHz to 10MHz.CLK13
Active-Low Output Enable and Power-Down Input. Digital outputs become high impedance and
device enters low-power mode when pin is high.
OE/PD
14
Digital Data Output (MSB)D915
Negative Reference Output. Bypass to AGND with 0.1µF capacitor. REFN can accept an external
voltage when the internal reference is disabled (REFN = AGND).
REFN5
Common-Mode Level Input. Bypass to AGND with a 0.1µF capacitor. CML can accept an external
voltage when the internal reference is disabled (REFN = AGND).
CML6
Positive Analog Signal InputINP9
Negative Analog Signal InputINN10
External Reference Input. Bypass to AGND with a 0.1µF capacitor. REFIN can be biased externally
to adjust the reference level and calibrate full-scale errors. To disable the internal reference, connect
REFIN to AGND.
REFIN4
Positive Reference Output. Bypass to AGND with a 0.1µF capacitor. If the internal reference is
disabled, REFP can accept an external voltage.
REFP3
PIN
Analog Supply Voltage Input. Bypass with a parallel combination of 2.2µF, 0.1µF, and 100pF capacitors
to AGND. Bypass each supply input to the closest AGND (e.g., capacitors between pins 1 and 2).
AVDD
2, 8
Analog Ground. Connect all return paths for analog signals to these pins.AGND1, 7
FUNCTIONNAME
Digital Data Outputs 4–1D4–D124–27
Digital Data Output (LSB)D028
Digital Supply Voltage Input. Bypass with 2.2µF and 0.1µF capacitors in parallel. Digital supply can
operate with voltages as low as +2.7V.
DVDD
20, 22
Digital GroundDGND21, 23
Digital Data Outputs 8–5D8–D516–19
MAX1426
10-Bit, 10Msps ADC
10
Detailed Description
The MAX1426 uses a 10-stage, fully differential, pipelined
architecture (Figure 1) that allows for high-speed conver-
sion while minimizing power consumption. Each sample
moves through a pipeline stage every half clock cycle.
Counting the delay through the output latch, there is a 5.5
clock-cycle latency.
A 2-bit flash ADC converts the input voltage to digital
code. A DAC converts the ADC result back into an ana-
log voltage, which is subtracted from the held input sig-
nal. The resulting error signal is then multiplied by two,
and this product is passed along to the next pipeline
stage where the process is repeated. Digital error correc-
tion compensates for offsets and mismatches in each
pipeline stage and ensures no missing codes.
Internal Track-and-Hold Circuit
Figure 2 shows a simplified functional diagram of the
internal track-and-hold (T/H) circuit in both track mode
and hold mode. The fully differential circuit samples the
input signal onto the four capacitors C1a, C1b, C2a,
and C2b. Switches S2a and S2b set the common mode
for the amplifier input, and open before S1. When S1
opens, the input is sampled. Switches S3a and S3b
then connect capacitors C1a and C1b to the output of
the amplifier. Capacitors C2a and C2b are connected
either to REFN, REFP, or each other, depending on the
results of the flash ADC. The amplifier then multiplies
the residue by two and the next stage in the pipeline
performs a similar operation.
System Timing Requirements
Figure 3 shows the relationship between the clock
input, analog input, and data output. The MAX1426
samples the falling edge of the input clock. Output data
is valid on the rising edge of the input clock. The output
data has an internal latency of 5.5 clock cycles, as
shown. Figure 4 shows an output timing diagram that
specifies the relationship between the input clock para-
meters and the valid output data.
Analog Input and Internal Reference
The MAX1426 has an internal +2.5V reference used to
generate three reference levels: +3.25V, +2.25V, and
+1.25V corresponding to VREFP, VCML, and VREFN.
These reference voltages enable a ±2V input range.
Bypass all reference voltages with a 0.1µF capacitor.
The MAX1426 allows for three modes of reference
operation: an internal reference (default) mode, an
externally adjusted reference mode, or a full external
reference mode. The internal reference mode occurs
when no voltages are applied to REFIN, REFP, CML,
T/H VOUT
x2
Σ
FLASH
ADC DAC
2 BITS
MDAC
10
VIN
VIN
STAGE 1 STAGE 2
D [9:0]
DIGITAL CORRECTION LOGIC
STAGE 10
S3a
INP
REFP
REFN
REFP
REFN
INN
S4a
S4c
C1a
CML
S2a
S1
S2b
CML
C2a
C2b
C1b
S4b
S3a
INP
a) TRACK MODE
b) HOLD MODE
REFP
REFN
REFP
REFN
INN
S4a
S3b
S4c
C1a
CML
S2a
S1
S2b
CML
C2a
C2b
C1b
S4b
Figure 1. Pipelined A/D Architecture (Block) Figure 2. Internal Track-and-Hold Circuit
MAX1426
10-Bit, 10Msps ADC
______________________________________________________________________________________ 11
and REFN. In this mode, the voltages at these pins
are set to their nominal values (see
Electrical
Characteristics
). The reference voltage levels can be
adjusted externally by applying a voltage at REFIN.
This allows other input levels to be used as well. The
full external reference mode is entered when REFIN =
AGND. External voltages can be applied to REFP,
CML, and REFIN. In this mode, the internal voltage
shuts down, resulting in less overall power consump-
tion.
Clock Input (CLK)
CLK is TTL/CMOS compatible. Since the interstage
conversion of the device depends on the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). Low clock jitter
improves SNR performance. The MAX1426 operates
with a 50% duty cycle. If the clock has a duty cycle
other than 50%, the clock must meet the specifications
for high and low periods as stated in the
Electrical
Characteristics
.
Output Enable/Power-Down Function
(
OE
//PD) and Output Data
All data outputs, D0 through D9, are TTL/CMOS-logic
compatible. There is a 5.5 clock-cycle latency between
the start convert signal and the valid output data. The
output coding for the MAX1426 is in binary two’s com-
plement format, which has the MSB inverted (Table 1).
The digital output goes into a high-impedance state
and the device into a low-power mode when OE/PD
goes high. For normal operation, drive OE low. The out-
puts are not designed to drive high capacitances or
n - 6
n
n - 5
n + 1
n - 4
n + 2
n - 3
n + 3
n - 2
n + 4
n - 1
n + 5
n
n + 6
n + 1
n + 7
5.5 CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
Figure 3. System Timing Diagram
Figure 4. Output Timing Diagram
DATA 0
INPUT
CLK
OUTPUT
DATA
tOD
tCLK
tCH tCI
DATA 1 DATA 2
1 1 1 1 1 1 1 1 1 1 -1 LSB
1 1 1 0 0 0 0 0 0 0-1/4 Full Scale
1 1 0 0 0 0 0 0 0 0-1/2 Full Scale
0 1 0 0 0 0 0 0 0 0+1/2 Full Scale
0 0 1 0 0 0 0 0 0 0+1/4 Full Scale
0 0 0 0 0 0 0 0 0 1+1 LSB
0 0 0 0 0 0 0 0 0 0Bipolar Zero
0 1 1 0 0 0 0 0 0 0+3/4 Full Scale
0 1 1 1 1 1 1 1 0 1+Full Scale 2LSB
0 1 1 1 1 1 1 1 1 0 +Full Scale 1LSB
0 1 1 1 1 1 1 1 1 1 +Full Scale
OUTPUT CODE
(TWO’S COMPLEMENT)
DIFFERENTIAL INPUT
Table 1. MAX1426 Output Code
1 0 1 0 0 0 0 0 0 0-3/4 Full Scale
1 0 0 0 0 0 0 0 0 1-Full Scale + 1LSB
1 0 0 0 0 0 0 0 0 0-Full Scale
MAX1426
10-Bit, 10Msps ADC
12 ______________________________________________________________________________________
Figure 5. Typical Application Circuit Using the Internal Reference
INPUT
50Ω
25Ω
-5V
+5V
0.1µF
0.1µF
0.1µF
BAS16 22pF
+5V
-5V
300Ω
600Ω
300Ω
300Ω
INP
CML
INN
600Ω
2.5k
+5V
-5V
0.1µF
600Ω
300Ω
300Ω
600Ω
300Ω
50Ω
50Ω
2.5k
+5V
22pF
50Ω
BAS16
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
25Ω
MAX4108
MAX473A
MAX1426
MAX4108
MAX4108
heavy loads, as they are specified to deliver only 200µA
for TTL compatibility. If an application needs output
buffering, use 74LS74s or 74ALS541s as required.
Applications Information
Figure 5 shows a typical application circuit containing a
single-ended to differential converter. The internal ref-
erence provides a +2.25V output for level shifting. The
input is buffered and then split to a voltage follower and
inverter. The op amps are followed by a lowpass filter
to remove some of the wideband noise associated with
high-speed op amps. In this application, the amplifier
outputs are directly coupled to the inputs. This configura-
tion can also be modified for AC-coupled applications.
The MAX1426 includes a DC level-shifting circuit internal
to the part, allowing for AC-coupled applications. The
level-shifting circuit is shown in Figure 6.
The circuit in Figure 6 can accept a 1Vp-p maximum
input voltage. With a maximum clock frequency of
10MHz, use 50Ωtermination to minimize reflections.
Buffer the digital outputs with a low-cost, high-speed,
MAX1426
10-Bit, 10Msps ADC
______________________________________________________________________________________ 13
octal D-latched flip-flop (74ALS374), or use octal
buffers such as the 74ALS541.
Typical Application Using an
External Reference
Figure 7 shows an application circuit that shuts down
the internal reference, allowing an external reference to
be used for selecting a different common-mode volt-
age. This added flexibility also allows for ratiometric
conversions, as well as for calibration.
Using Transformer Coupling
A small transformer (Figure 8) provides isolation and
AC-coupling to the ADC’s input. Connecting the trans-
former's center tap to CML provides a +2.25VDC level
shift to the input. Transformer coupling reduces the
need for high-speed op amps, thereby reducing cost.
Although a 1:1 transformer is shown, a step-up trans-
former may be selected to reduce the drive require-
ments.
Single-Ended DC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended applica-
tion. The MAX4106 quad op amp provides high speed,
high bandwidth, low noise, and low distortion to main-
tain the integrity of the input signal.
4.5k
CMLP
INP
INN
CMLN
4.5k
TO T/H INPUT
5.5k 5.5k
Figure 6. Analog Input DC Bias Circuit
Figure 7. Using an External Reference for REFP, REFN, and CML (internal reference shut down)
MAX1426
REFIN
REFN
R
50Ω
R
R
R
R
+1V
R
50Ω
50Ω
R
R
VDD
VDD
2
CML
0.1µF
0.1µF
0.1µF
AGND
VDD
2
VDD
2
VDD
4
VDD
4
MAX4284
MAX4284
( )
VDD
2- 1V
( )
REFP VDD
2+ 1V
( )
MAX4284
MAX1426
10-Bit, 10Msps ADC
14 ______________________________________________________________________________________
Bypassing and Board Layout
The MAX1426 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, using surface-mount devices
for minimum inductance. Bypass all analog voltages
(AVDD, REFIN, REFP, REFN, and CML) to AGND.
Bypass the digital supply (DVDD) to DGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Route high-
speed digital signal traces away from sensitive analog
traces. Matching impedance, especially for the input
clock generator, may reduce reflections, thus providing
less jitter in the system. For optimum results, use low-
distortion complementary components such as the
MAX4108.
Figure 8. Using a Transformer for AC-Coupling
Figure 9. Single-Ended AC-Coupled Input Signal
MAX1426
T1
N.C.
IN1 61
52
43
C3
22pF
C9
22pF
0.1µF
R2
100Ω
R3
100ΩR5
25Ω
R4
25Ω
MINICIRCUITS
KKB1 INP
CML
INN
MAX1426
0.1µF
100Ω
50Ω
±2V
100Ω
22pF
INP
INN
0.1µF50Ω
VIN
±V
MAX4108
MAX1426
10-Bit, 10Msps ADC
______________________________________________________________________________________ 15
________________________________________________________Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
28 SSOP A28+1 21-0056 90-0095
MAX1426
10-Bit, 10Msps ADC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/00 Initial release —
1 7/11 Updated Ordering Information, Absolute Maximum Ratings, Electrical Characteristics,
and Package Information 1, 2, 15
