Preliminary GS8161E18/36AT-300/275/250/225/200 1M x 18, 512K x 36 18Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features * FT pin for user-configurable flow through or pipeline operation * Single Cycle Deselect (SCD) operation * IEEE 1149.1 JTAG-compatible Boundary Scan * Dual Cycle Deselect (DCD) operation * 1.8 V or 2.5 V +10%/-10% core power supply * 1.8 V or 2.5 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to Interleaved Pipeline mode * Byte Write (BW) and/or Global Write (GW) operation * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC-standard 100-lead TQFP 100-pin TQFP package Pipeline 3-1-1-1 2.5 V 1.8 V Flow Through 2-1-1-1 2.5 V 1.8 V tKQ tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36) -300 -275 -250 -225 -200 Unit 2.2 2.4 2.5 2.7 3.0 ns 3.3 3.6 4.0 4.4 5.0 ns 320 375 320 370 300 345 300 340 275 320 275 315 250 295 250 285 230 265 225 260 mA mA mA mA tKQ tCycle 5.0 5.0 5.25 5.25 5.5 5.5 6.0 6.0 6.5 6.5 ns ns Curr (x18) Curr (x36) Curr (x18) Curr (x36) 220 265 220 265 215 260 215 260 210 245 210 245 200 235 200 235 190 225 190 225 mA mA mA mA 300 MHz-200 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. DCD Pipelined Reads The GS8161E18/36AT is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Functional Description Applications The GS8161E18/36AT is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Core and Interface Voltages The GS8161E18/36AT operates on a 1.8 V or 2.5 V power supply. All input are 2.5 V and 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 2.5 V and 1.8 V compatible. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positiveedge-triggered clock input (CK). Output enable (G) and power Rev: 1.01 3/2002 1/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 A6 A7 E1 A18 NC NC BB BA A17 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9 GS8161E18A 100-Pin TQFP Pinout LBO A5 A4 VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC Rev: 1.01 3/2002 A19 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC A1 A0 TMS TDI VSS VDD TDO TCK A10 A11 A12 A13 A14 A15 A16 VDDQ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M X 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A3 A2 NC NC NC 2/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 A6 A7 E1 A18 BD BC BB BA A17 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9 GS8161E36A 100-Pin TQFP Pinout Rev: 1.01 3/2002 DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9 TDO TCK A10 A11 A12 A13 A14 A15 A16 LBO A5 A4 VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A3 A2 A1 A0 TMS TDI VSS VDD DQC9 DQC8 DQC7 VDDQ 3/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 TQFP Pin Description Pin Location Symbol Type Description 37, 36 A0, A1 I Address field LSBs and Address Counter preset Inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, A2-A18 I Address Inputs 80 A19 I Address Inputs (x18 versions) 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29 DQA1-DQA8 DQB1-DQB8 DQC1-DQC8 DQD1-DQD8 I/O Data Input and Output pins (x36 Version) 51, 80, 1, 30 DQA9, DQB9, DQC9, DQD9 I/O Data Input and Output pins (x36 Version) 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 DQA1-DQA9 DQB1-DQB9 I/O Data Input and Output pins (x18 Version) 51, 52, 53, 56, 57 75, 78, 79, 95, 96 1, 2, 3, 6, 7, 25, 28, 29, 30 NC -- No Connect (x18 Version) 16, 66 NC -- No Connect 87 BW I Byte Write--Writes all enabled bytes; active low 93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low 95, 96 BC, BD I Byte Write Enable for DQC, DQD Data I/'s; active low (x36 Version) 89 CK I Clock Input Signal; active high 88 GW I Global Write Enable--Writes all bytes; active low 98 E1 I Chip Enable; active low 86 G I Output Enable; active low 83 ADV I Burst address counter advance enable; active low 84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low 64 ZZ I Sleep Mode control; active high 31 LBO I Linear Burst Order mode; active low 15, 41, 65, 91 VDD I Core power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS I I/O and Core Ground 4, 11, 20, 27, 54, 61, 70, 77 VDDQ I Output driver power supply Rev: 1.01 3/2002 4/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 GS Block Diagram Register A0-An D Q A0 A0 D0 Q0 A1 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q 36 36 Register D Q BB 4 4 Register D Q Q Register D D Q D Q Register Register D Q Register BC BD Register D 36 Q 36 36 Register E1 D Q 4 32 36 Parity Encode Register D Q 4 Parity Compare FT G ZZ 36 DQx1-DQx9 Power Down NC NC Control Note: Only x36 version shown for simplicity. Rev: 1.01 3/2002 5/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There is a are pull-up devices on the ZQ, SCD FT pin and a pull-down devices on the PE and ZZ pins, so thosethis input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Enable / Disable Parity I/O Pins This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16, x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits. Burst Counter Sequences Interleaved Burst Sequence Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.01 3/2002 6/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Note: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes "C" and "D" are only available on the x36 version. Rev: 1.01 3/2002 7/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Synchronous Truth Table Operation Address Used State Diagram Key5 E1 ADSP ADSC ADV W3 DQ4 Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CW H X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend Burst Current H X H H T D Notes: 1. X = Don't Care, H = High, L = Low 2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.01 3/2002 8/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR CR W X R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.01 3/2002 9/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.01 3/2002 10/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins -0.5 to 3.6 V VDDQ Voltage in VDDQ Pins -0.5 to 3.6 V VCK Voltage on Clock Input Pin -0.5 to 3.6 V VI/O Voltage on I/O Pins -0.5 to VDDQ +0.5 ( 3.6 V max.) V VIN Voltage on Other Input Pins -0.5 to VDD +0.5 ( 3.6 V max.) V IIN Input Current on Any Pin +/-20 mA IOUT Output Current on Any I/O Pin +/-20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature -55 to 125 o C TBIAS Temperature Under Bias -55 to 125 o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 1.01 3/2002 11/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V 1.8 V Supply Voltage VDD1 1.6 1.8 2.0 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V 1.8 V VDDQ I/O Supply Voltage VDDQ1 1.6 1.8 2.0 V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. VDDQ2 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD -- VDD + 0.3 V 1 VDD Input Low Voltage VIL -0.3 -- 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD -- VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ -0.3 -- 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ1 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD -- VDD + 0.3 V 1 VDD Input Low Voltage VIL -0.3 -- 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD -- VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ -0.3 -- 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Rev: 1.01 3/2002 12/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Recommended Operating Temperatures Parameter Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 C 2 Ambient Temperature (Industrial Range Versions) TA -40 25 85 C 2 Note: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS - 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. Package Thermal Characteristics Rating Layer Board Symbol Max Unit Notes Junction to Ambient (at 200 lfm) single RJA 40 C/W 1,2 Junction to Ambient (at 200 lfm) four RJA 24 C/W 1,2 Junction to Case (TOP) -- RJC 9 C/W 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1.01 3/2002 13/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 AC Test Conditions Parameter Conditions Input high level VDD - 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 30pF* 50 VDDQ/2 * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD -1 uA 1 uA ZZ Input Current IIN1 VDD VIN VIH 0 V VIN VIH -1 uA -1 uA 1 uA 100 uA FTInput Current IIN2 VDD VIN VIL 0 V VIN VIL -100 uA -1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD -1 uA 1 uA Output High Voltage VOH2 IOH = -8 mA, VDDQ = 2.3 V VDDQ - 0.4 V -- Output High Voltage VOH1 IOH = -4 mA, VDDQ = 1.6 V VDDQ - 0.4 V -- Output Low Voltage VOL2 IOL = 8 mA, VDD = 2.3 V -- 0.4 V Output Low Voltage VOL1 IOL = 4 mA, VDD = 1.6 V -- 0.4 V Rev: 1.01 3/2002 14/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Rev: 1.01 3/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 15/35 -- Device Deselected; All other inputs VIH or VIL Deselect Current IDD 70 95 IDD Pipeline Flow Through 35 35 ISB Pipeline ISB 175 10 IDD IDDQ Flow Through Flow Through 305 15 IDD IDDQ Pipeline 345 25 175 10 305 15 195 30 345 30 0 to 70C 195 30 IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD Symbol IDDQ Flow Through Pipeline Flow Through Pipeline Flow Through Pipeline Mode 75 100 45 45 185 10 315 15 205 30 355 25 185 10 315 15 205 30 355 30 -40 to 85C -300 Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. -- ZZ VDD - 0.2 V (x18) (x36) (x18) (x36) Standby Current 1.8 V Operating Current Device Selected; All other inputs VIH or VIL Output open Device Selected; All other inputs VIH or VIL Output open Operating Current 2.5 V Test Conditions Parameter Operating Currents 70 90 35 35 170 10 285 15 190 30 315 25 170 10 285 15 190 30 315 30 0 to 70C 75 95 45 45 180 10 295 15 200 30 325 25 180 10 295 15 200 30 325 30 -40 to 85C -275 60 85 35 35 165 10 260 15 185 30 290 25 165 10 260 15 185 30 290 30 0 to 70C 65 90 45 45 175 10 270 15 195 30 300 25 175 10 270 15 195 30 600 60 -40 to 85C -250 60 80 35 35 155 10 235 15 175 30 265 20 155 10 235 15 175 30 265 30 0 to 70C 65 85 45 45 165 10 245 15 185 30 275 20 165 10 245 15 185 30 275 30 -40 to 85C -225 50 75 35 35 150 10 215 10 165 25 240 20 150 10 215 15 165 25 240 25 0 to 70C 55 80 45 45 160 10 225 10 175 25 250 20 160 10 225 15 175 25 250 25 -40 to 85C -200 mA mA mA mA mA mA mA mA mA mA mA mA Unit Preliminary GS8161E18/36AT-300/275/250/225/200 (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 AC Electrical Characteristics Pipeline Flow Through Parameter Symbol Clock Cycle Time -300 -275 -250 -225 -200 Unit Min Max Min Max Min Max Min Max Min Max tKC 3.3 -- 3.7 -- 4.0 -- 4.4 -- 5.0 -- ns Clock to Output Valid tKQ -- 2.2 -- 2.4 -- 2.5 -- 2.7 -- 3.0 ns Clock to Output Invalid tKQX 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns 1 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns Clock to Output in Low-Z tLZ Setup time tS 1.1 -- 1.1 -- 1.2 -- 1.3 -- 1.4 -- ns Hold time tH 0.1 -- 0.1 -- 0.2 -- 0.3 -- 0.4 -- ns Clock Cycle Time tKC 5.0 -- 5.25 -- 5.5 -- 6.0 -- 6.5 -- ns Clock to Output Valid tKQ -- 5.0 -- 5.25 -- 5.5 -- 6.0 -- 6.5 ns Clock to Output Invalid tKQX 3.0 -- 3.0 -- 3.0 -- 3.0 -- 3.0 -- ns Clock to Output in Low-Z tLZ1 3.0 -- 3.0 -- 3.0 -- 3.0 -- 3.0 -- ns Setup time tS 1.4 -- 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Hold time tH 0.4 -- 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns Clock HIGH Time tKH 1.3 -- 1.3 -- 1.3 -- 1.3 -- 1.3 -- ns Clock LOW Time tKL 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns Clock to Output in High-Z tHZ1 1.5 2.3 1.5 2.3 1.5 2.3 1.5 2.5 1.5 3.0 ns G to Output Valid tOE -- 2.3 -- 2.3 -- 2.3 -- 2.5 -- 3.0 ns G to output in Low-Z tOLZ1 0 -- 0 -- 0 -- 0 -- 0 -- ns G to output in High-Z tOHZ1 -- 2.3 -- 2.3 -- 2.3 -- 2.5 -- 3.0 ns ZZ setup time tZZS2 5 -- 5 -- 5 -- 5 -- 5 -- ns ZZ hold time tZZH2 1 -- 1 -- 1 -- 1 -- 1 -- ns ZZ recovery tZZR 20 -- 20 -- 20 -- 20 -- 20 -- ns Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.01 3/2002 16/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Write Cycle Timing Write Cycle Timing Single Write Burst Write Deselected Write CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH A0-An ADV must be inactive for ADSP Write WR2 WR1 WR3 tS tH GW tS tH BW tS tH BA-BD WR2 WR1 WR1 tS tH WR3 WR3 E1 masks ADSP E1 E1 only sampled with ADSP or ADSC G tS tH DQA-DQD Rev: 1.01 3/2002 Hi-Z Write specified byte for 2A and all bytes for 2B, 2C& 2D D1A D2A D2B D2C D2D 17/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D3A (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Flow Through Read Cycle Timing Single Read Burst Read tKL CK tKH tS tH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0-An RD1 RD2 RD3 tS tH tS tH GW BW BA-BD tS tH E1 masks ADSP E1 tOE tOHZ G tKQX tOLZ DQA-DQD Q1A Hi-Z Q2A tKQX Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 1.01 3/2002 18/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Flow Through Read-Write Cycle Timing Single Write Single Read Burst Read CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0-An WR1 RD1 tS RD2 tH GW tH tS BW tS tH BA-BD WR1 tS tH E1 masks ADSP E1 tOE tOHZ G tS tKQ DQA-DQD Hi-Z Q1A tH D1A Q2A Q2B Q2c Q2D Q2A Burst wrap around to it's initial state Rev: 1.01 3/2002 19/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Pipelined DCD Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst ADV tS tH A0-An RD1 RD3 RD2 tS tH tS tH GW BW BA-BD tS tH E1 masks ADSP E1 tOE G tOHZ Hi-Z tOLZ Q1A DQA-DQD tKQX Q2A tKQX Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 1.01 3/2002 20/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Pipelined DCD Read-Write Cycle Timing Single Write Burst Read Single Read tKL CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0-An RD1 WR1 RD2 tS tH GW tS tH BW tS tH BA-BD WR1 tS tH E1 masks ADSP E1 tOE tOHZ G DQA-DQD Rev: 1.01 3/2002 Hi-Z tS tH tKQ Q1A D1A Q2A 21/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q2B Q2c Q2D (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. tKC tKH tKL ADSP ADSC tZZS ZZ ~ ~ ~ ~ tS tH ~ ~ CK tZZH ~ ~~ ~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ ~ ~ Sleep Mode Timing Diagram tZZR Snooze Application Tips Single and Dual Cycle Deselect SCD devices force the use of "dummy read cycles" (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Rev: 1.01 3/2002 22/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.01 3/2002 23/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 JTAG TAP Block Diagram 0 Bypass Register 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 * * * * 2 1 0 Boundary Scan Register n * * * * * * * * * 2 1 0 TMS Test Access Port (TAP) Controller TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Die Revision Code GSI Technology JEDEC Vendor ID Code I/O Configuration Not Used Presence Register ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.01 3/2002 24/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 0 Pause IR 1 Exit2 IR 0 1 Update DR Update IR 1 1 0 0 0 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to ShiftDR state then places the boundary scan register between the TDI and TDO pins. EXTEST Rev: 1.01 3/2002 25/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.01 3/2002 26/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min. Max. Unit Notes 3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V 1 3.3 V Test Port Input Low Voltage VILJ3 -0.3 0.8 V 1 2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1 2.5 V Test Port Input Low Voltage VILJ2 -0.3 0.3 * VDD2 V 1 TMS, TCK and TDI Input Leakage Current IINHJ -300 1 uA 2 TMS, TCK and TDI Input Leakage Current IINLJ -1 100 uA 3 TDO Output Leakage Current IOLJ -1 1 uA 4 Test Port Output High Voltage VOHJ 1.7 -- V 5, 6 Test Port Output Low Voltage VOLJ -- 0.4 V 5, 7 Test Port Output CMOS High VOHJC VDDQ - 100 mV -- V 5, 8 Test Port Output CMOS Low VOLJC -- 100 mV V 5, 9 Notes: 1. Input Under/overshoot voltage must be -2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = -4 mA 7. IOLJ = + 4 mA 8. IOHJC = -100 uA 9. IOHJC = +100 uA JTAG Port AC Test Conditions Parameter Conditions Input high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level 1.25 V 50 30pF* VT = 1.25 V * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. Rev: 1.01 3/2002 JTAG Port AC Test Load DQ 27/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 JTAG Port Timing Diagram tTKH tTKL tTKC TCK tTS tTH TMS TDI TDO tTKQ JTAG Port AC Electrical Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tTKC 50 -- ns TCK Low to TDO Valid tTKQ -- 20 ns TCK High Pulse Width tTKH 20 -- ns TCK Low Pulse Width tTKL 20 -- ns TDI & TMS Set Up Time tTS 10 -- ns TDI & TMS Hold Time tTH 10 -- ns Rev: 1.01 3/2002 28/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 GS8161E18/36A Boundary Scan Chain Order (Cont.) GS8161E18/36A Boundary Scan Chain Order Order x36 x18 Order Pin x36 x18 1 PH = 0 n/a 2 X n/a 3 X n/a 4 A10 44 5 A11 45 6 A12 46 7 A13 47 8 A14 48 9 A15 49 10 A16 50 11 QA9 NC = 1 51 n/a 12 DA9 PH = 0 51 n/a 13 NC = 1 n/a 14 PH = 0 n/a 15 QA8 NC = 1 52 n/a 16 DA8 PH = 0 52 n/a 17 PH = 0 NC = 1 n/a PH = 0 18 n/a 19 QA7 NC = 1 53 n/a 20 DA7 PH = 0 53 n/a 21 NC = 1 n/a 22 PH = 0 n/a 23 QA6 NC = 1 56 n/a 24 DA6 PH = 0 56 n/a 25 NC = 1 n/a 26 PH = 0 n/a 27 QA5 NC = 1 57 n/a 28 DA5 PH = 0 57 n/a x18 Pin x36 x18 29 NC = 1 n/a 30 PH = 0 n/a 31 QA4 QA1 58 32 DA4 DA1 58 33 NC = 1 n/a 34 PH = 0 n/a 35 QA3 QA2 59 36 DA3 DA2 59 37 NC = 1 n/a 38 PH = 0 n/a 39 QA2 QA3 62 40 DA2 DA3 62 41 NC = 1 n/a 42 PH = 0 n/a 43 QA1 QA4 63 44 DA1 DA4 63 45 NC = 1 n/a 46 PH = 0 n/a 47 ZZ 64 48 PH = 0 n/a 49 NC = 1 66 50 QB1 QA5 68 51 DB1 DA5 68 52 NC = 1 n/a 53 PH = 0 n/a 54 QB2 QA6 69 55 DB2 DA6 69 56 NC = 1 n/a 57 PH = 0 n/a 58 Rev: 1.01 3/2002 x36 QB3 29/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. QA7 72 (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 GS8161E18/36A Boundary Scan Chain Order (Cont.) Order x36 x18 59 DB3 DA7 Pin x36 x18 GS8161E18/36A Boundary Scan Chain Order (Cont.) Order x36 x18 Pin x36 x18 72 89 ADV 83 60 NC = 1 n/a 90 ADSP 84 61 PH = 0 n/a 91 ADSC 85 62 QB4 QA8 73 92 G 86 63 DB4 DA8 73 93 BW 87 64 NC = 1 n/a 94 GW 88 65 PH = 0 n/a 95 NC = 1 n/a 66 QB5 QA9 74 96 NC = 1 n/a 67 DB5 DA9 74 97 NC = 1 n/a 68 NC = 1 n/a 98 NC = 1 n/a 69 PH = 0 n/a 99 CK 89 70 QB6 NC = 1 75 n/a 100 PH = 0 n/a 71 DB6 PH = 0 75 n/a 101 PH = 0 n/a 72 NC = 1 n/a 102 A17 92 73 PH = 0 n/a 103 BA 93 74 QB7 NC = 1 78 n/a 104 BB NC = 1 75 DB7 PH = 0 78 n/a 105 BC BB BD NC = 1 94 n/a 95 76 NC = 1 n/a 106 77 PH = 0 n/a 107 A18 97 96 n/a 78 QB8 NC = 1 79 n/a 108 E1 98 79 DB8 PH = 0 79 n/a 109 A7 99 A6 100 80 NC = 1 n/a 110 81 PH = 0 n/a 111 QC9 NC = 1 1 n/a DC9 PH = 0 1 n/a 82 QB9 NC = 1 80 n/a 112 83 DB9 PH = 0 80 n/a 113 NC = 1 n/a PH = 0 n/a 84 NC = 1 n/a 114 85 PH = 0 n/a 115 QC8 NC = 1 2 n/a 116 DC8 PH = 0 2 n/a 86 NC = 1 A19 n/a 80 87 A9 81 117 NC = 1 n/a 88 A8 82 118 PH = 0 n/a Rev: 1.01 3/2002 30/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 GS8161E18/36A Boundary Scan Chain Order (Cont.) Order x36 x18 119 QC7 120 DC7 Pin GS8161E18/36A Boundary Scan Chain Order (Cont.) Order x36 x18 Pin x36 x18 x36 x18 NC = 1 3 n/a 149 PH = 0 3 n/a 150 QD8 QB5 18 DD8 DB5 18 NC = 1 n/a 121 NC = 1 n/a 151 122 PH = 0 n/a 152 NC = 1 n/a PH = 0 n/a 123 QC6 NC = 1 6 n/a 153 124 DC6 PH = 0 6 n/a 154 QD7 QB6 19 DD7 DB6 19 125 NC = 1 n/a 155 126 PH = 0 n/a 156 NC = 1 n/a PH = 0 n/a 127 QC5 NC = 1 7 n/a 157 128 DC5 PH = 0 7 n/a 158 QD6 QB7 22 DD6 DB7 22 129 NC = 1 n/a 159 130 PH = 0 n/a 160 NC = 1 n/a PH = 0 n/a 131 QC4 QB1 8 161 132 DC4 DB1 8 162 QD5 QB8 23 DD5 DB8 23 133 NC = 1 n/a 163 134 PH = 0 n/a 164 NC = 1 n/a PH = 0 n/a 135 QC3 QB2 9 165 136 DC3 DB2 9 166 QD4 QB9 24 DD4 DB9 24 137 NC = 1 n/a 167 138 PH = 0 n/a 168 NC = 1 n/a PH = 0 n/a 139 QC2 QB3 12 169 140 DC2 DB3 12 170 QD3 NC = 1 25 n/a DD3 PH = 0 25 n/a 141 NC = 1 n/a 171 142 PH = 0 n/a 172 NC = 1 n/a PH = 0 n/a 143 QC1 QB4 13 173 144 DC1 DB4 13 174 QD2 NC = 1 28 n/a DD2 PH = 0 28 n/a 145 NC = 1 n/a 175 146 PH = 0 n/a 176 NC = 1 n/a 147 FT 14 177 PH = 0 n/a 148 NC = 1 16 178 Rev: 1.01 3/2002 QD1 31/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. NC = 1 29 n/a (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 GS8161E18/36A Boundary Scan Chain Order (Cont.) Order x36 x18 179 DD1 PH = 0 Pin x36 x18 29 n/a 180 NC = 1 n/a 181 PH = 0 n/a 182 QD9 NC = 1 30 n/a 183 DD9 PH = 0 30 n/a 184 NC = 1 n/a 185 PH = 0 n/a 186 LBO 31 187 A5 32 188 A4 33 189 A3 34 190 A2 35 191 A1 36 192 A0 37 193 PH = 0 n/a 194 G 86 Notes: 1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1, PE = 0, SD = 0, ZZ = 0, FT = 1, and SCD = 1. 2. Every DQ pad consists of two scan registers--D is for input capture, and Q is for output capture. 3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control is effective after JTAG EXTEST instruction is executed. 4. 1 = no connect, internally set to logic value 1 5. 0 = no connect, internally set to logic value 0 6. X = no connect, value is undefined Rev: 1.01 3/2002 32/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 TQFP Package Drawing L Description Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch L Foot Length L1 Lead Length Y Coplanarity Lead Angle L1 c Pin 1 Symbol 0.20 D D1 e b 0.65 0.45 0.60 0.75 1.00 A1 A2 0.10 Y 0 7 E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.01 3/2002 33/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TA3 1M x 18 GS8161E18AT-300 Pipeline/Flow Through TQFP 300/5 C 1M x 18 GS8161E18AT-275 Pipeline/Flow Through TQFP 275/5.25 C 1M x 18 GS8161E18AT-250 Pipeline/Flow Through TQFP 250/5.5 C 1M x 18 GS8161E18AT-225 Pipeline/Flow Through TQFP 225/6 C 1M x 18 GS8161E18AT-200 Pipeline/Flow Through TQFP 200/6.5 C 512K x 36 GS8161E36AT-300 Pipeline/Flow Through TQFP 300/5 C 512K x 36 GS8161E36AT-275 Pipeline/Flow Through TQFP 275/5.25 C 512K x 36 GS8161E36AT-250 Pipeline/Flow Through TQFP 250/5.5 C 512K x 36 GS8161E36AT-225 Pipeline/Flow Through TQFP 225/6 C 512K x 36 GS8161E3T-200 Pipeline/Flow Through TQFP 200/6.5 C 1M x 18 GS8161E18AT-300I Pipeline/Flow Through TQFP 300/5 I 1M x 18 GS8161E18AT-275I Pipeline/Flow Through TQFP 275/5.25 I 1M x 18 GS8161E18AT-250I Pipeline/Flow Through TQFP 250/5.5 I 1M x 18 GS8161E18AT-225I Pipeline/Flow Through TQFP 225/6 I 1M x 18 GS8161E18AT-200I Pipeline/Flow Through TQFP 200/6.5 I 512K x 36 GS8161E36AT-300I Pipeline/Flow Through TQFP 300/5 I 512K x 36 GS8161E36AT-275I Pipeline/Flow Through TQFP 275/5.25 I 512K x 36 GS8161E36AT-250I Pipeline/Flow Through TQFP 250/5.5 I 512K x 36 GS8161E36AT-225I Pipeline/Flow Through TQFP 225/6 I 512K x 36 GS8161E36AT-200I Pipeline/Flow Through TQFP 200/6.5 I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS-. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.01 3/2002 34/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161E18/36AT-300/275/250/225/200 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New Types of Changes Format or Content * Creation of new datasheet 8161E18A_r1 8161E18A_r1; 8161E18A_r1_01 Rev: 1.01 3/2002 Page;Revisions;Reason Content * Updated FT power numbers * Updated AC Characteristics table * Updated ZZ recovery time diagram * Updated AC Test Conditions table and removed Output Load 2 diagram 35/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc.