Rev: 1.01 3/2002 1/35 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161E18/36AT-300/275/250/225/200
1M x 18, 512K x 36
18Mb Sync Burst SRAMs
300 MHz–200 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• Dual Cycle Deselect (DCD) operation
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP 100-pin TQFP package
Functional Description
Applications
The GS8161E18/36AT is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8161E18/36AT is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8161E18/36AT operates on a 1.8 V or 2.5 V power
supply. All input are 2.5 V and 1.8 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 2.5 V and 1.8 V compatible.
-300 -275 -250 -225 -200 Unit
Pipeline
3-1-1-1 tKQ
tCycle 2.2
3.3 2.4
3.6 2.5
4.0 2.7
4.4 3.0
5.0 ns
ns
2.5 V Curr (x18)
Curr (x36)
320
375 300
345 275
320 250
295 230
265 mA
mA
1.8 V Curr (x18)
Curr (x36)
320
370 300
340 275
315 250
285 225
260 mA
mA
Flow
Through
2-1-1-1
tKQ
tCycle 5.0
5.0 5.25
5.25 5.5
5.5 6.0
6.0 6.5
6.5 ns
ns
2.5 V Curr (x18)
Curr (x36)
220
265 215
260 210
245 200
235 190
225 mA
mA
1.8 V Curr (x18)
Curr (x36)
220
265 215
260 210
245 200
235 190
225 mA
mA