ON Semiconductor MC34080 thru MC34085 High Slew Rate, Wide Bandwidth, JFET Input Operational Amplifiers These devices are a new generation of high speed JFET input monolithic operational amplifiers. Innovative design concepts along with JFET technology provide wide gain bandwidth product and high slew rate. Well-matched JFET input devices and advanced trim techniques ensure low input offset errors and bias currents. The all NPN output stage features large output voltage swing, no deadband crossover distortion, high capacitive drive capability, excellent phase and gain margins, low open loop output impedance, and symmetrical source/sink AC frequency response. This series of devices is available in fully compensated or decompensated (AVCL2) and is specified over a commercial temperature range. They are pin compatible with existing Industry standard operational amplifiers, and allow the designer to easily upgrade the performance of existing designs. * Wide Gain Bandwidth: 8.0 MHz for Fully Compensated Devices Wide Gain Bandwidth: 16 MHz for Decompensated Devices * High Slew Rate: 25 V/s for Fully Compensated Devices High Slew Rate: 50 V/s for Decompensated Devices * High Input Impedance: 1012 * * * * * HIGH PERFORMANCE JFET INPUT OPERATIONAL AMPLIFIERS 8 8 1 1 P SUFFIX PLASTIC PACKAGE CASE 626 PIN CONNECTIONS Input Offset Voltage: 0.5 mV Maximum (Single Amplifier) Large Output Voltage Swing: -14.7 V to +14 V for Large Output Voltage Swing: VCC/VEE = 15 V Low Open Loop Output Impedance: 30 @ 1.0 MHz Offset Null 1 Inv. Input 2 Noninv. Input 3 Output 1 Inputs 1 Single Dual Quad 7 VCC + 6 Output 5 Offset Null 1 8 VCC 2 7 Output 2 - 3 + VEE ORDERING INFORMATION - + 4 6 5 Inputs 2 (Dual, Top View) Operating Temperature Range Package TA = 0 to +70C AVCL2 Compensated NC - (Single, Top View) Excellent Phase/Gain Margins: 55/7.6 dB for Fully Compensated Devices Fully Compensated 8 VEE 4 Low THD Distortion: 0.01% Op Amp Function D SUFFIX PLASTIC PACKAGE CASE 751 (SO-8) MC34081BD MC34080BD SO-8 MC34081BP MC34080BP Plastic DIP MC34082P MC34083BP MC34084DW MC34085BDW MC34084P MC34085BP Plastic DIP SO-16L TA = 0 to +70C Plastic DIP 16 14 1 1 P SUFFIX PLASTIC PACKAGE CASE 646 DW SUFFIX PLASTIC PACKAGE CASE 751G (SO-16L) PIN CONNECTIONS Output 1 Inputs 1 VCC Inputs 2 1 16 2 15 3 + 1 4 + 14 4 13 5 12 6 + - 2 3 + - 11 Output 4 Inputs 4 VEE VCC Inputs 3 7 10 Output 3 NC 8 9 NC March, 2002 - Rev. 1 Inputs 1 1 14 2 + 13 4 11 5 + - 10 3 Output 2 Semiconductor Components Industries, LLC, 2002 Output 1 Inputs 2 Output 2 6 + + - 1 2 4 3 7 12 9 8 Output 4 Inputs 4 VEE Inputs 3 Output 3 (Quad, Top View) 1 Publication Order Number: MC34080/D MC34080 thru MC34085 MAXIMUM RATINGS Rating Symbol Value Unit VS +44 V Input Differential Voltage Range VIDR (Note 1) V Input Voltage Range VIR (Note 1) V Output Short Circuit Duration (Note 2) tSC Indefinite sec Operating Ambient Temperature Range TA 0 to +70 C Supply Voltage (from VCC to VEE) Operating Junction Temperature TJ +125 C Storage Temperature Range Tstg - 65 to +165 C NOTES: 1. Either or both input voltages must not exceed the magnitude of V CC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. Representative Schematic Diagram (Each Amplifier) VCC 200 A 50 A 850 A Q1 D1 - J1 Q6 R1 240 J2 18 RSC Inputs + + Q8 CC 5.0 pF CF 20 pF D2 700 R2 Output Q7 CM + 3.0 pF Q5 R3 1.0 k Q10 Q9 500 500 Null Adjust (MC34080, 081)* Q4 Q11 100 A D4 1 Q3 D3 R6 50 A Q2 R4 1.0 k 5 300 A R7 66 k VEE RM *Pins 1 & 5 (MC34080,081) should not be directly grounded or connected to VCC. http://onsemi.com 2 MC34080 thru MC34085 DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = - 15 V, TA = Tlow to Thigh [Note 3], unless otherwise noted.) Characteristics Symbol Input Offset Voltage (Note 4) Single TA = +25C TA = 0 to +70C (MC34080B, MC34081B) Dual TA = +25C TA = 0 to +70C (MC34082, MC34083) Quad TA = +25C TA = 0 to +70C (MC34084, MC34085) Min Typ Max VIO mV -- -- 0.5 -- 2.0 4.0 -- -- 1.0 -- 3.0 5.0 -- -- 6.0 -- 12 14 -- 10 -- V/C -- -- 0.06 -- 0.2 4.0 nA -- -- 0.02 -- 0.1 2.0 nA 25 15 80 -- -- -- 13.2 13.4 13.4 13.7 13.9 -- -- -- -- -- -- -- -14.1 -14.7 -- -13.5 -14.1 -14.0 VIO/T Average Temperature Coefficient of Offset Voltage Input Bias Current (VCM = 0 Note 5) TA = +25C TA = 0 to +70C IIB Input Offset Current (VCM = 0 Note 5) TA = +25C TA = 0 to +70C IIO Large Signal Voltage Gain (VO = 10 V, RL = 2.0 k) TA = +25C TA = Tlow to Thigh AVOL Output Voltage Swing RL = 2.0 k, TA = +25C RL = 10 k, TA = +25C RL = 10 k, TA = Tlow to Thigh VOH RL = 2.0 k, TA = +25C RL = 10 k, TA = +25C RL = 10 k, TA = Tlow to Thigh VOL Output Short Circuit Current (TA = +25C) Input Overdrive = 1.0 V, Output to Ground Source Sink V/mV V ISC mA 20 20 Input Common Mode Voltage Range TA = +25C Unit VICR 31 28 -- -- (VEE +4.0) to (VCC - 2.0) V Common Mode Rejection Ratio (RS 10 k, TA = +25C) CMRR 70 90 -- dB Power Supply Rejection Ratio (RS = 100 , TA = 25C) PSRR 70 86 -- dB Power Supply Current Single TA = +25C TA = Tlow to Thigh Dual TA = +25C TA = Tlow to Thigh Quad TA = +25C TA = Tlow to Thigh ID NOTES: (continued) Thigh = +70C for MC34080B 3. Tlow = 0C for MC34080B 0C for MC34081B +70C for MC34081B 0C for MC34084 +70C for MC34084 0C for MC34085 +70C for MC34085 4. See application information for typical changes in input offset voltage due to solderability and temperature cycling. 5. Limits at TA = +25C are guaranteed by high temperature (Thigh) testing. http://onsemi.com 3 mA -- -- 2.5 -- 3.4 4.2 -- -- 4.9 -- 6.0 7.5 -- -- 9.7 -- 11 13 MC34080 thru MC34085 AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = - 15 V, TA = +25C, unless otherwise noted.) Characteristics Symbol Slew Rate (Vin = -10 V to +10 V, RL = 2.0 k, CL = 100 pF) Compensated AV = +1.0 AV = -1.0 Decompensated AV = +2.0 AV = -1.0 Min Typ Max Unit SR Settling Time (10 V Step, AV = -1.0) To 0.10% (1/2 LSB of 9-Bits) To 0.01% (1/2 LSB of 12-Bits) V/s 20 -- 35 -- 25 30 50 50 -- -- -- -- -- -- 0.72 1.6 -- -- 6.0 12 8.0 16 -- -- -- -- 400 800 -- -- -- -- 55 39 -- -- -- -- 7.6 4.5 -- -- s ts Gain Bandwidth Product (f = 200 kHz) Compensated Decompensated GBW Power Bandwidth (RL = 2.0 k, VO = 20 Vpp, THD = 5.0%) Compensated AV = +1.0 Decompensated AV = - 1.0 BWp MHz kHz Phase Margin (Compensated) RL = 2.0 k RL = 2.0 k, CL = 100 pF m Gain Margin (Compensated) RL = 2.0 k RL = 2.0 k, CL = 100 pF Am Equivalent Input Noise Voltage RS = 100 , f = 1.0 kHz en -- 30 -- nV/ Hz Equivalent Input Noise Current (f = 1.0 kHz) In -- 0.01 -- pA/ Hz Input Capacitance Ci -- 5.0 -- pF Input Resistance ri -- 1012 -- THD -- 0.05 -- % Channel Separation (f = 10 kHz) -- -- 120 -- dB Open Loop Output Impedance (f = 1.0 MHz) Zo -- 35 -- Figure 1. Input Common Mode Voltage Range versus Temperature 0 -1.0 100 k VCC/VEE = 3.0 V to 22 V VIO = 5.0 mA VCC 10 k VCC/VEE = 15 V VCM = 0 V 1.0 k 3.0 2.0 1.0 VEE 0 -55 dB Figure 2. Input Bias Current versus Temperature I, IB INPUT BIAS CURRENT (pA) V ICR , INPUT COMMON MODE VOLTAGE RANGE (V) Total Harmonic Distortion AV = +10, RL = 2.0 k, 2.0 VO 20 Vpp, f = 10 kHz Degrees -25 0 25 50 75 100 100 10 1.0 -55 125 TA, AMBIENT TEMPERATURE (C) -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) http://onsemi.com 4 100 125 MC34080 thru MC34085 Figure 3. Input Bias Current versus Input Common Mode Voltage Figure 4. Output Voltage Swing versus Supply Voltage 50 VCC/VEE = 15 V TA = 25C 120 VO, OUTPUT VOLTAGE SWING (Vpp ) I IB , INPUT BIAS CURRENT (pA) 140 100 80 60 40 20 -12 -8.0 -4.0 0 4.0 8.0 VIC, INPUT COMMON MODE VOLTAGE (V) 12 RL Connected to Ground TA = 25C 40 30 20 10 0 0 0 VCC Source VCC/VEE = +15 V to +22 V TA = 25C -2.0 -3.0 Sink 1.0 0 VEE 0 4.0 8.0 12 2.0 1.0 VEE 0 300 I, SC OUTPUT SHORT CIRCUIT CURRENT (mA) V sat , OUTPUT SATURATION VOLTAGE (V) 30 k 300 k Figure 8. Output Short Circuit Current versus Temperature -0.8 2.0 VCC/VEE = +15 V RL to VCC TA = 25C VEE 30 k 3.0 k RL, LOAD RESISTANCE TO GROUND () VCC 3.0 k VCC/VEE = 15 V TA = 25C -4.0 16 0 0 300 25 VCC -2.0 Figure 7. Output Saturation versus Load Resistance to VCC 1.0 10 15 20 VCC |VEE|, SUPPLY VOLTAGE (V) 0 IL, LOAD CURRENT (mA) -0.4 5.0 Figure 6. Output Saturation vesus Load Resistance to Ground V sat , OUTPUT SATURATION VOLTAGE (V) V sat , OUTPUT SATURATION VOLTAGE (V) Figure 5. Output Saturation versus Load Current -1.0 RL = 2.0 k RL = 10 k 300 k 40 Source 30 Sink 20 VCC/VEE = 15 V RL 0.1 Vin = 1.0 V 10 0 -55 RL, LOAD RESISTANCE TO VCC () -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) http://onsemi.com 5 100 125 MC34080 thru MC34085 Figure 9. Output Impedance versus Frequency 40 20 AV = 1.0 AV = 1000 0 1.0 k AV = 100 10 k AV = 10 100 k 1.0 M 20 0 1.0 k 10 M AV = 100 AV = 1000 10 k 100 k AV = 10 AV = 2.0 1.0 M 10 M Figure 12. Output Distortion versus Frequency 0.5 VCC/VEE = 15 V RL = 2.0 k THD = 1.0% TA = 25C Compensated Units AV = +1.0 Decompensated Units AV = -1.0 8.0 4.0 100 k 1.0 M AV = 1000 0.4 0.3 0.2 AV = 100 0.1 0 10 M 10 100 AV = 1.0* 1.0 k f, FREQUENCY (Hz) Figure 13. Open Loop Voltage Gain versus Temperature 1.08 VCC/VEE = 15 V VO = -10 V to +10 V RL = 10 k f 10 Hz 1.04 1.00 0.96 0.92 -55 -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) http://onsemi.com 6 VCC/VEE = 15 V VO = 2.0 Vpp RL = 2.0 k TA = 25C *Compensated Units Only AV = 10 f, FREQUENCY (Hz) A, VOL OPEN LOOP VOLTAGE GAIN (dB NORMALIZED) VO, OUTPUT VOLTAGE SWING (Vpp ) 40 Figure 11. Output Voltage Swing versus Frequency 12 0 10 k 60 f, FREQUENCY (Hz) 24 16 VCC/VEE = 15 V VCM = 0 VO = 0 IO = 0.5 mA TA = 25C Decompensated Units Only f, FREQUENCY (Hz) 28 20 Z, O OUTPUT IMPEDANCE () 60 80 VCC/VEE = 15 V VCM = 0 VO = 0 IO = 0.5 mA TA = 25C Compensated Units Only THD, OUTPUT DISTORTION (%) Z, O OUTPUT IMPEDANCE () 80 Figure 10. Output Impedance versus Frequency 100 125 10 k 100 k MC34080 thru MC34085 Phase 60 Gain 45 90 40 135 20 Solid Line Curves Compensated Units Dashed Line Curves Decompensated Units 0 1.0 10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) 180 1.0 M 10 M 100 M 20 100 Gain Margin = 5.5 dB 10 0 -10 VCC/VEE = 15 V VO = 0 V TA = 25C Phase Margin = 43 -20 -30 -40 1.0 120 140 160 1 Gain, RL = 2.0 k 2 Gain, RL = 2.0 k, CL = 100 pF 3 Phase, RL = 2.0 k 4 Phase, RL = 2.0 k, CL = 100 pF Decompensated Units Only 2.0 3.0 5.0 7.0 180 , EXCESS PHASE (DEGREES) A, VOL OPEN LOOP VOLTAGE GAIN (dB) Figure 16. Open Loop Voltage Gain and Phase versus Frequency 200 10 20 30 50 20 100 10 -10 -20 -30 -40 1.0 5.0 7.0 10 f, FREQUENCY (Hz) 20 160 180 200 4 30 50 VCC/VEE = 15 V RL = 2.0 k 1.10 1.00 0.90 0.80 -55 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) Figure 19. Phase Margin versus Load Capacitance 70 Decompensated Units AV = +2.0 M , PHASE MARGIN (DEGREES) PERCENT OVERSHOOT 3.0 3 140 1.20 100 60 Compensated Units AV = +1.0 40 0 10 2.0 2 120 Figure 17. Normalized Gain Bandwidth Product versus Temperature Figure 18. Percent Overshoot versus Load Capacitance 20 1 1 Gain, RL = 2.0 k 2 Gain, RL = 2.0 k, CL = 100 pF 3 Phase, RL = 2.0 k 4 Phase, RL = 2.0 k, CL = 100 pF Compensated Units Only f, FREQUENCY (Hz) 80 Gain Margin = 7.6 dB VCC/VEE = 15 V VO = 0 V Phase TA = 25C Margin = 54 0 , EXCESS PHASE (DEGREES) 80 0 A, VOL OPEN LOOP VOLTAGE GAIN (dB) VCC/VEE = 15 V VO = 0 V RL = 2.0 k TA = 25C GBW, GAIN BANDWIDTH PRODUCT (NORMALIZED) A, VOL OPEN LOOP VOLTAGE GAIN (dB) 100 Figure 15. Open Loop Voltage Gain and Phase versus Frequency , EXCESS PHASE (DEGREES) Figure 14. Open Loop Voltage Gain and Phase versus Frequency VCC/VEE = 15 V RL = 2.0 k VO = 100 mVpp VO = -10 V to +10 V TA = 25C 100 60 50 40 30 20 10 0 10 1.0k VCC/VEE = 15 V RL = 2.0 k to VO = 100 mVpp VO = -10 V to +10 V TA = 25C Compensated Units AV = +1.0 CL, LOAD CAPACITANCE (pF) Decompensated Units AV = +2.0 100 CL, LOAD CAPACITANCE (pF) http://onsemi.com 7 1.0k MC34080 thru MC34085 Figure 20. Gain Margin versus Load Capacitance 8.0 60 VCC/VEE = 15 V RL = 2.0 k to VO = 100 mVpp VO = -10 V to +10 V TA = 25C Compensated Units AV = +1.0 6.0 m , PHASE MARGIN (DEGREES) A, m GAIN MARGIN (dB) 10 Figure 21. Phase Margin versus Temperature 4.0 Decompensated Units AV = +2.0 2.0 0 10 100 CL, LOAD CAPACITANCE (pF) 50 Solid Line Curves-Compensated Units AV = +1.0 CL = 10 pF Dashed Line Curves-Decompensated Units AV = +2.0 40 CL = 100 pF 30 20 CL = 360 pF 10 0 -55 10 k 6.0 CL = 10 pF VCC/VEE = 15 V RL = 2.0 k to VO = 100 mVpp VO = -10 V to +10 V 4.0 2.0 0 -55 CL = 100 pF CL = 200 pF CL = 360 pF -25 0 25 50 75 100 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 1.40 Solid Line Curves-Compensated Units AV = +1.0 Dashed Line Curves-Decompensated Units AV = +2.0 SR, SLEW RATE (NORMALIZED) A, m GAIN MARGIN (dB) 8.0 -25 Figure 23. Normalized Slew Rate versus Temperature Figure 22. Gain Margin versus Temperature 10 VO = 100 mVpp VO = -10 V to +10 V VCC/VEE = 15 V CL = 200 pF RL = 2.0 k to 1.20 1.00 0.80 0.60 -55 125 VCC/VEE = 15 V AV = +1.0 for Compensated Units AV = -1.0 for Decompensated Units RL = 2.0 k CL = 100 pF VO = -10 V to +10 V TA, AMBIENT TEMPERATURE (C) -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) http://onsemi.com 8 100 125 MC34080 thru MC34085 MC34084 Transient Response AV = +1.0, RL = 2.0 k, VCC/VEE = 15 V, TA = 25C Figure 24. Small Signal Figure 25. Large Signal CL = 100 pF 0 5.0 mV/Div 50 mV/Div CL = 10 pF 0 0.2 s/Div 0.5 s/Div MC34085 Transient Response AV = +2.0, RL = 2.0 k, VCC/VEE = 15 V, TA = 25C Figure 26. Small Signal Figure 27. Large Signal CL = 100 pF 0 5.0 mV/Div 50 mV/Div CL = 10 pF 0 0.2 s/Div 0.5 s/Div http://onsemi.com 9 100 TA = -55C TA = 25C 80 TA = 125C VCC/VEE = 15 V VS = 3.0 V VO = 0 V 60 VCC VCC 40 + - 20 VO Compensated Units AV = +1.0 Decompensated Units AV = +2.0 VEE VEE 0 0.1 1.0 10 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M Figure 29. Power Supply Rejection Ratio versus Frequency PSSR, POWER SUPPLY REJECTION RATIO (dB) Figure 28. Common Mode Rejection Ratio versus Frequency 10 M 120 VCC/VEE = 15 V VS = 3.0 V VO = 0 V TA = 25C 100 80 60 40 + - 100 90 + - 80 70 -55 VCC VCC Compensated Units AV = +1.0 Decompensated Units AV = +2.0 VEE VEE -25 VCC/VEE = 15 V VS = 3.0 V VO = 0 V f 10 Hz Positive Supply VO 0 25 50 75 100 VO 0 0.1 VEE VEE 1.0 10 100 k 1.0 M 10 M 125 TA = 125C 1.10 1.00 TA = 25C Supply Current Normalized to VCC/VEE = 15 V, TA = 25C RL = VO = 0 0.90 0.80 0.70 0 5.0 10 TA = -55C 20 25 15 VS, SUPPLY VOLTAGE (V) Figure 32. Channel Separation versus Frequency Figure 33. Spectral Noise Density 100 e, n INPUT NOISE VOLTAGE (nV/ Hz ) 120 CHANNEL SEPERATION (dB) 100 1.0 k 10 k f, FREQUENCY (Hz) 1.20 TA, AMBIENT TEMPERATURE (C) 100 80 60 40 20 Negative Supply 20 Figure 31. Normalized Supply Current versus Supply Voltage 110 Negative Supply Positive Supply VCC VCC Figure 30. Power Supply Rejection Ratio versus Temperature I, CC SUPPLY CURRENT (NORMALIZED) PSSR, POWER SUPPLY REJECTION RATION (dB) CMRR, COMMON MODE REJECTION RATIO (dB) MC34080 thru MC34085 VCC/VEE = 15 V TA = 25C 0 10 k 100 k 1.0 M f, FREQUENCY (Hz) 60 40 20 0 10 10 M VCC/VEE = 15 V VCM = 0 TA = 25C 80 100 1.0 k f, FREQUENCY (Hz) http://onsemi.com 10 10 k 100 k MC34080 thru MC34085 APPLICATIONS INFORMATION input stage also allows a differential up to 44 V, provided the maximum input voltage range is not exceeded. The supply voltage operating range is from 5.0 V to 22 V. For optimum frequency performance and stability, careful component placement and printed circuit board layout should be exercised. For example, long unshielded input or output leads may result in unwanted input-output coupling. In order to reduce the input capacitance, resistors connected to the input pins should be physically close to these pins. This not only minimizes the input pole for optimum frequency response, but also minimizes extraneous "pickup" at this node. Supply decoupling with adequate capacitance close to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit large impedance changes over temperature. Primarily due to the JFET inputs of the op amp, the input offset voltage may change due to temperature cycling and board soldering. After 20 temperature cycles (- 55 to 165C), the typical standard deviation for input offset voltage is 559 V in the plastic packages. With respect to board soldering (260C, 10 seconds), the typical standard deviation for input offset voltage is 525 V in the plastic package. Socketed devices should be used over a minimal temperature range for optimum input offset voltage performance. The bandwidth and slew rate of the MC34080 series is nearly double that of currently available general purpose JFET op-amps. This improvement in AC performance is due to the P-channel JFET differential input stage driving a compensated miller integration amplifier in conjunction with an all NPN output stage. The all NPN output stage offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. With a 10 k load resistance, the op amp can typically swing within 1.0 V of the positive rail (VCC), and within 0.3 V of the negative rail (VEE), providing a 28.7 p-p swing from 15 V supplies. This large output swing becomes most noticeable at lower supply voltages. If the load resistance is referenced to VCC instead of ground, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to VCC during the positive swing and the NPN output transistor will pull the output very near VEE during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull-up capability. The all NPN transistor output stage is also inherently fast, contributing to the operation amplifier 's high gain-bandwidth product and fast settling time. The associated high frequency output impedance is 50 (typical) at 8.0 MHz. This allows driving capacitive loads from 0 pF to 300 pF without oscillations over the military temperature range, and over the full range of output swing. The 55C phase margin and 7.6 dB gain margin as well as the general gain and phase characteristics are virtually independent of the sink/source output swing conditions. The high frequency characteristics of the MC34080 series is especially useful for active filter applications. The common mode input range is from 2.0 V below the positive rail (VCC) to 4.0 V above the negative rail (VEE). The amplifier remains active if the inputs are biased at the positive rail. This may be useful for some applications in that single supply operation is possible with a single negative supply. However, a degradation of offset voltage and voltage gain may result. Phase reversal does not occur if either the inverting or noninverting input (or both) exceeds the positive common mode limit. If either input (or both) exceeds the negative common mode limit, the output will be in the high state. The Figure 34. Offset Nulling Circuit VCC 3 + 2 4 VEE http://onsemi.com 11 7 6 1 5 5.0 k MC34080 thru MC34085 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 626-05 ISSUE K 8 5 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. -B- 1 4 F DIM A B C D F G H J K L M N -A- NOTE 2 L C J -T- N SEATING PLANE D M K MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10 0.030 0.040 G H 0.13 (0.005) T A M B M M D SUFFIX PLASTIC PACKAGE CASE 751-05 (SO-8) ISSUE R D A 8 E 5 0.25 H 1 M B M 4 h B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C X 45 e A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A S http://onsemi.com 12 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.18 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7 MC34080 thru MC34085 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE L 14 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F DIM A B C D F G H J K L M N L C J N H G D SEATING PLANE K M DW SUFFIX PLASTIC PACKAGE CASE 751G-02 (SO-16L) ISSUE A -A- 16 9 -B- 8X P 0.010 (0.25) 1 M B M 8 16X 0.010 (0.25) M T A S B S F R X 45 C -T- 14X G K SEATING PLANE M http://onsemi.com 13 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0 10 0.39 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. J D INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0 10 0.015 0.039 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029 MC34080 thru MC34085 NOTES http://onsemi.com 14 MC34080 thru MC34085 NOTES http://onsemi.com 15 MC34080 thru MC34085 ON Semiconductor is a trademark and is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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