NJIOUuU 6G S355 Series SERIAL IYO REAL TIME CLOCK Mi GENERAL DESCRIPTION ME PACKAGE OUTLINE The NJU6355 series is a serial 1/0 Rea! Time Clock suitable for 4 bits microprocessor. It contains quartz crystal oscillator, counter, shift register, voltage regulator, voltage detector and in- terface control ler. The NJU6355 required only 4-port of microprocessor SA for data transfer, and the microprocessor can receive the data at any time when the microprocessor requires. NJU6355XD NJU6355xE The operating voltage is as wide as 2.0V to 5. 5V, consequently, the NJU6355 can count accurate time data even if the back up period. Furthermore, the long time back up is available as the current consumption during the back up period is less than 3yA. W@ FEATURES @ PIN CONFIGURATION @ Operating Voltage : 2.0 ~ 5.5V @ Low operating current : 3) wA (Typ.) at 3.0V Oo 4 A (Typ.) at 5.0V 1/0 [ ]1 8 |] Voo @ BCD Counts of Seconds, Minutes, Hours, Date, Days of Week, Month and Year xt [ ]2 7 [_] DATA @ Required only 4-port (DATA, CLK, CE and 1/0) @ Low Battery Detector (Low voltage alarm signal output) xT UC 3 6 | CLK @ Automatic Leap Year Compensation @ Package Outline - DIP 8/DMP 8 Ves [| 4 5 | CE @ C-M0S Technol ogy M@ LINE UP VERSION OUTPUT DATA OSC. CAPACITOR 6355 E Seconds, Minutes, Hours, Days of Week, Date, Month, Year | C,/C.a on chip F Seconds, Minutes, Hours, Days of Week C,/Ca on chip G Secends, Minutes, Hours, Days of Week, Date, Month, Year Ca on chip H Seconds, Minutes, Hours, Days of Week Cs on chip 12-30 -- New Japan Radio Co, Ltd.M@ BLOCK DIAGRAM xT NIU G35 5 Series XT +J Divider Sec. | Hin. | Hr. | Date| Day |Wontly Year Osci | lator/ Timer Counter PU0d00 Sec. | Hin.| Hr. | Date| Day [Month] Year f Shift Register Vs or <s Cp Controller/ ; Clock Counter -C CLK Low Voltage 11 Detector SJ CE @ TERMINAL DESCRIPTION NO. SYMBOL F U N CG T I O N _ Input/Output Select Terminal for DATA Terminal 1 1/0 "HA": Input, EL: Output During the CE terminal is L, the Data terminal is high impedance. 2 XT Quartz Crystal Connecting Terminal (f=32. 768kHz) 3 XT Refer to the Line-Up Table for internal Cg, Cd value. Chip Enable Input Terminal (with pull-down resistance) 5 CE YH : Data Input/Output is available LY > Data terminal is high impedance When the CE signal is which raising edge or falling edge, the CLK signal should be fixed to L. 6 CLK Clock Input Termina! The Data Input/Output is synchronized by this clock. When the CE terminal is L the data terminal is high impedance. Serial Timer Data _ 1/0 cE DATA Terminal Input/Output H H Input 7 DATA L H Output H L Hi gh-|mpedance L L High-Impedance 8 Voo Power Supply (+5V) 4 Vss GND New Japan Radio Co.Ltd. 12-31Nee 55S series @ =FUNCTIONAL DESCRIPTION 1. Timer Data structure The NJU6355 using BCD code which consisting of 4 bits per 1 digit The calendar function including the last date of each month and the leap year calculation is executed automatically The unused bit for the timer data is 0. < Timer Data Bit Map > MSB LSB Range Second | 0 | so | ss | s4 | sa {| s2 | si | so | 0-59 Minute | 0 | me | m5 | m4 | m3 | m2 | mt | mo | 0 - 59 Hour | o | of H5 | 44 | Ha | H2 [ HI | Ho | Saye of Hk Pole [mw] 1-7 Date | o | o | v5 | v4 | os | v2 | or | to | 1-31 a I 23 Month | o | o | o | m4 {ows | m2 | mt | Mo} 1-12 oO ' Year | 7 | ve | ys | v4 | v3 | y2 | v1 | Yo | 99 2. Timer Data Reading When the 1/0 terminal is L and the CE terminal is H, timer data can read out. The output is LSB first and the output data strings (depending on the version) is shown below The timer data is transferred from timer counter to shift register at rising edge of the chip enable on the CE terminal, and output the LSB of the timer data from the Data terminal Afterward the timer data in the shift register shift by synchronized at the falling edge of clock signal on CLK terminal and output from the DATA terminal lf the timer data is updated in the data output, there are one second difference between timer data and output data. < E & G Version > | Year | Month | Date | Day | Hour | Minute Second | The data is read out from LSB of Year, and first 52-bit is effective < F & H Version > | Day | Hour | Minute | Second | The data is read out from LSB of Days of Week, and first 28-bit is effective If the low voltage detector detect the low battery, (EE)u is written into each digit of timer data and read out. The code of (EE)u is a warning for the data broken. 1 2-32- New Japan Radio Co, Lid.CORC) N JU G35 5 Series < Read-Out Timing > Data Output {) Year or Day mecisren AX KKK eX KX KK KEKE The timer data is transferred to the shift register at rising @ edge of the CE(@) and LSB of the timer data is output to the Data terminal. Afterward the timer data in the shift register shift by synchronized at falling edge of the CLK(@) then output to the Data terminal time-to-time. note ) When the CE signal is which raising edge or falling edge, the CLK signal should be fixed to L. And so, before the CE signal is raised, the 1/0 signal should be fixed to L. 3. Timer Data Writing When both of 1/0 terminal and CE terminal are H, update is stopped, Oscillator divider is cleared, and the timer data can be written to the NJU6355. The timer data is written into the shift register from the Data terminal by synchronized with rising edge of the clock signal input from the CLK terminal, and the data is transferred from the shift register to the timer counter by synchronized with falling edge of the CE signal. In this time the second-counter is cleared to QO, and the oscillator divider start the operation. The input data strings are LSB first of each digit as shown below (the data format is depend on the version) : < E & G Version > | Year | Month | Date | Day Hour | Minute | The data is written from LSB of Year and last 44-bit is effective < F & H Version > The data is written from LSB of Days of Week and last 20-bit is effective New Japan Radio Co,Ltd 1 2-33. N JU G35 5S Series < Write-Down Timing > i | Data Input SHIFT REGISTER Lo XX XX The data is input into The data in the shift register the shift register at is transferred to the timer rising edge of the CLK. counter at this falling edge of the CE, then the oscil lator divider start the operation. note ) When the CE signal is which raising edge or falling edge, the CLK signal should be fixed to L. And so, before the CE signal is raised, the 1/0 signal should be fixed to H. 4. Low Voltage Detector The NJU6355 series incorporate the low battery detector. If the supply voltage reduce to the detection level, (EE) is written into each digit of the shift register as warning code for the CPU. 5. Data Access The NJU6355 series can operate from 2.0V to 5.5V. However, it is not allow the data access out of the range of 5V+10% It may be broken the data unless 5V+10%. Thus, when the data access, CE terminal should be H after the power supply rise to 5V+10%, then start the operation. Mi ABSOLUTE MAXIMUM RATINGS ( Ta=25C ) PARAMETER SYMBOL RATINGS UNIT Supply Voltage Voo -03~ +60 Vv Input Voltage Vin Vss-0.3 ~ Vont0.3 Vv oo. : 250 (DIP) Power Dissipation Pp 200 (DMP) mil Operating Temperature Topr - 30 ~ + 80 c Storage Temperature Tots -55 ~ +150 C 1 2-34-/Mew Jgoan Radio Co, LieN JU GS355 Series M ELECTRICAL CHARACTERISTICS DC Characteristics Voo=2. OV, Ta=25C ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Operating Current Ibo XT=32. 768kHz, CE=0V 3.0 4.0 HA LowBattery Detect Voer 1 7 V Voltage DC Characteristics ( Voo=5. OV410%, Ta=25C ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Operating Voltage Vop 4.5 5.5 Vv Operating Current loo XT=32. 768kHz, CE=0V 4.0 15 HA 3-st Leakage Current Iret DATA Terminal (CE=0V) -2.0 2.0 HA Input Leakage Current Jon 1/0, OLK Terminals -1.0 1.0 HA Input Current lee CE Terminal (CE=Vpp) 20 wa Vin 1/0, CE, CLK, DATA Terminals | Voox0. 8 Voo Input Voltage = Vv Viv 1/0, CE, CLK, DATA Terminals Vss Voox0. 2 Vou DATA Terminal (1 on=-0. 4mA) 41 Output Voltage V Vot DATA Terminal (1o.=1. OmA) 0.4 AC CHARACTERISTICS Voo=5. OV+10%, Ta=25C, C.=50pF ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT CLK Pulse H Period town 0.47 5000 US CLK Pulse L Period tewr 0. 47 5000 MS CE Set-up Time Before CLK Rising tes 470 ns CE Hold Time After CLK Falling ten 20 ns 1/0 Set-up Time Before CLK Rising tos 60 ns 1/0 Hold Time After CLK Falling ton 20 ns Write-Down Data Set-Up Time twos 100 ns Write-Down Data Hold Time twon 20 ns Data Delay Time t After CLK Falling Ree 200 ns Rise/Fall Time ter 50 ns New Japan Radio Co,Ltd. 12-35ce jbi vi Seo tN (in), -- CLK Input Data Mi APPLICATION CIRCUIT Main Power Supply 12-36 tens NJ UG S35 5 Series New Japan Radio Co,Ltd. 80% { output Date 20% Ve NJU6355 Voo DATA v0 CPU CLK CE Vss tof 20%