T3 Mapper MegaCore Function T3MAP February 20, 2001 User Guide Version 1.0 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com A-UG-IPT3MAPPER-1.0 T3 Mapper MegaCore Function (T3MAP) User Guide Altera, APEX, APEX 20K, APEX 20KE, MegaCore, MegaWizard, OpenCore, Quartus, and Quartus II are trademarks and/or service marks of Altera Corporation in the United States and other countries. Altera Corporation acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, including the following: Verilog is a registered trademark of Cadence Design Systems, Incorporated. Java is a trademark of Sun Microsystems Inc. Microsoft is a registered trademark and Windows is a trademark of Microsoft Corporation. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Copyright 2001 Altera Corporation. All rights reserved. ii Altera Corporation About this User Guide User Guide This user guide provides comprehensive information about the Altera(R) T3 Mapper MegaCore(R) Function (T3MAP). Table 1 shows the user guide revision history. Table 1. Revision History Revision How to Find Information Description 0.01 January 22, 2001 1.00 February 20, 2001 Initial release of this document Altera Corporation Date Initial beta release of this document The Adobe Acrobat Find feature allows you to search the contents of a PDF file. Click on the binoculars icon in the top tool bar to open the Find dialog box, or click the right mouse button for a pull-down menu. Bookmarks serve as an additional table of contents. Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. Numerous links, shown in green text, allow you to jump to related information. iii About this User Guide T3 Mapper MegaCore Function (T3MAP) User Guide How to Contact Altera For the most up-to-date information about Altera products, go to the Altera world-wide web site at http://www.altera.com. For additional information about Altera products, consult the sources shown in Table 2. Table 2. How to Contact Altera Information Type Access USA & Canada All Other Locations Altera Literature Services Electronic mail lit_req@altera.com (1) lit_req@altera.com (1) Non-technical customer service Telephone hotline (800) SOS-EPLD (408) 544-7000 (7:30 a.m. to 5:30 p.m. Pacific Time) Fax (408) 544-7606 (408) 544-7606 Telephone hotline (800) 800-EPLD (6:00 a.m. to 6:00 p.m. Pacific Time) (408) 544-7000 (1) (7:30 a.m. to 5:30 p.m. Pacific Time) Fax (408) 544-6401 (408) 544-6401 (1) Electronic mail telecom@altera.com telecom@altera.com FTP site ftp.altera.com ftp.altera.com Telephone (408) 544-7104 (408) 544-7104 (1) World-wide web site http://www.altera.com http://www.altera.com Technical support General product information Note: (1) iv You can also contact your local Altera sales office or sales representative. Altera Corporation T3 Mapper MegaCore Function (T3MAP) User Guide Typographic Conventions About this User Guide The T3 Mapper MegaCore Function (T3MAP) User Guide uses the typographic conventions shown in Table 3. Table 3. Conventions Visual Cue Meaning Bold Type with Initial Capital Letters Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \maxplus2 directory, d: drive, chiptrip.gdf file. Bold italic type Book titles are shown in bold italic type with initial capital letters. Example: 1999 Device Data Book. Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters. Example: AN 75 (High-Speed Board Design). Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file. Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. "Subheading Title" References to sections within a document and titles of Quartus II and MAX+PLUS II Help topics are shown in quotation marks. Example: "Configuring a FLEX 10K or FLEX 8000 Device with the BitBlasterTM Download Cable." Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix _n, e.g., reset_n. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\max2work\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. 1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. Altera Corporation v About this User Guide Abbreviations & Acronyms vi T3 Mapper MegaCore Function (T3MAP) User Guide AHDL AIRbus ATM CDR CPU EDA ESB FIFO IP LE LSb LSB Mbps MSb MSB NDF OOF PC POH RX SONET SPE STS-1 T3FRM TOH TX UTOPIA VCO VHDL VHSIC Altera Hardware Description Language Access to Internal Registers interface Asynchronous Transfer Mode Clock Data Recovery Central Processing Unit Electronic Design Automation Embedded System Block First In First Out Intellectual Property Logic Element Least Significant bit Least Significant Byte Megabits per second Most Significant bit Most Significant Byte New Data Flag Out Of Frame Personal Computer Path Overhead Receive Synchronous Optical Network Synchronous Payload Envelope Synchronous Transport Signal level 1 T3 Framer MegaCore Function Transport Overhead Transmit Universal Test & Operations Physical Interface for ATM Voltage Controlled Oscillator VHSIC Hardware Description Language Very High Speed Integrated Circuit Altera Corporation Contents User Guide Specifications General Description .........................................................................................................................9 MegaWizard Generated Files .................................................................................................9 Features ...........................................................................................................................................10 EXTRACT ................................................................................................................................10 INSERT ....................................................................................................................................10 Functional Description ..................................................................................................................12 EXTRACT ................................................................................................................................12 T3 Data Rate ....................................................................................................................12 Data Byte Acceptance ....................................................................................................13 Destuffing ........................................................................................................................13 T3 Extraction ...................................................................................................................13 INSERT ....................................................................................................................................13 T3 Bit Acceptance ...........................................................................................................13 Asynchronous Mapping ...............................................................................................13 Stuffing ............................................................................................................................14 Interfaces & Protocols ....................................................................................................................14 Midbus .....................................................................................................................................14 Receive Direction ...........................................................................................................15 Transmit Direction .........................................................................................................15 AIRbus .....................................................................................................................................16 T3 Mapper Interface ..............................................................................................................17 Receive .............................................................................................................................17 Transmit ..........................................................................................................................17 Performance ....................................................................................................................................17 I/O Signals ......................................................................................................................................18 Software Interface ..........................................................................................................................20 Memory Map ..........................................................................................................................20 Registers ..................................................................................................................................20 INSERT Block Register Description ............................................................................21 INS_CTRL - MAP_INSERT Control - 'h0 .................................................. 21 INS_STAT - MAP_INSERT Status - 'h1 ..................................................... 21 INS_IS - MAP_INSERT Interrupt Status - 'h2 ........................................... 21 INS_IE - MAP_INSERT Interrupt Enable - 'h3 ......................................... 21 INS_OH - MAP_INSERT Overhead Communications Insert - 'h4 ....... 21 EXTRACT Block Register Description ........................................................................22 EXT_CTRL - MAP_EXTRACT Control - 'h5 ............................................. 22 EXT_STAT - MAP_EXTRACT Status - 'h6 ............................................... 22 EXT_IS - MAP_EXTRACT Interrupt Status - 'h7 ...................................... 22 Altera Corporation vii Contents T3 Mapper MegaCore Function (T3MAP) User Guide EXT_IE - MAP_EXTRACT Interrupt Enable - 'h8 .................................... 22 EXT_OH - MAP_EXTRACT Overhead Communications Extract - 'h9 22 EXT_FIFO_HIGH - MAP_EXTRACT FIFO High Mark - 'hA ................ 23 EXT_FIFO_LOW - MAP_EXTRACT FIFO Low Mark - 'hB .................... 23 Getting Started Test-drive a T3MAP .......................................................................................................................25 Design Walkthrough .....................................................................................................................25 Obtaining & Installing the T3MAP .............................................................................................26 Installing the MegaCore Files ...............................................................................................26 Generating a Custom T3MAP ......................................................................................................27 Implementing the System .............................................................................................................27 Compiling & Performing Place & Route ....................................................................................27 Performing Synthesis Compilation & Post-Routing Simulation .....................................27 Using Third-Party EDA Tools ......................................................................................28 Using the Quartus II Software .....................................................................................28 Functional Simulations Using Visual IP Models .......................................................29 Downloading & Installing Visual IP Software ..........................................................29 Licensing & Configuring a Device ..............................................................................................29 viii Altera Corporation Specifications User Guide General Description The T3 Mapper MegaCore(R) Function (T3MAP) uses the MegaWizard(R) Plug-In--within the QuartusTMII software to generate variants in VHDL, AHDL, or Verilog HDL, which you can instantiate into your design. Table 1. Optional Features Note (1) Options Parameters Choices LEs ESBs Basic Configuration - - 875 2 Note (1) The numbers for LEs and ESBs are approximate as of Feb. 20, 2001. Users are strongly advised to run the MegaWizard Plug-In and Quartus II software to see exact numbers for the T3MAP. MegaWizard Generated Files When you finish going through the wizard, it generates the following files: Altera Corporation 1 Specifications Table 1 shows the optional features available for the T3MAP. One of the following files--depending on your EDA tool selection-- is used to instantiate a T3MAP into your design: - An AHDL text design file (.tdf); - A VHDL design file (.vhd); - A Verilog design file (.v); Sample Verilog instantiation of Black Box (_inst.v); Black Box module (_bb.v); Symbol files (.bsf) for the Quartus II software are used to instantiate the T3MAP into a schematic design; An encrypted HDL netlist file (.e.vqm.v). 9 Specifications T3 Mapper MegaCore Function (T3MAP) User Guide The T3MAP complies with all applicable standards, including: - Features Telcordia, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2, Revision 2, January 1999. The T3MAP does not support the following features: - SONET/SDH line and path overhead processing; - T3 framing, including overhead processing; - Translation of maintenance signals between T3 and SONET (translation should be performed by software between the T3FRM and the SONET overhead blocks); - Automatic resynchronization after SONET new pointer, or NDF events. (The T3MAP requires a soft restart.) The T3MAP interfaces to a data bit stream at a data rate of 44.736 Mbps +/- 895 bps--via bit stuffing--to accommodate standard T3 rates. While it is expected that the T3 input stream will be within the standard limits of 44.736 Mbps +/- 895 bps, the T3MAP supports rates between 44.712 Mbps and 44.784 Mbps. The T3MAP supports STS-1, STS-3, and STS-12 data paths. It comprises two major blocks, EXTRACT and INSERT--illustrated in Figure 1. EXTRACT Supports the standard T3 rate via adaptive control of the external VCO--illustrated in Figure 2. - The FIFO buffer is 32 bytes deep. Accepts data bytes from a SONET framer Performs destuffing Extracts a raw T3 bit stream, and forwards it optionally to a T3FRM INSERT 10 Performs asynchronous mapping Uses a 32-byte FIFO buffer Performs payload bit stuffing Provides payload bytes to a SONET framer Accepts a T3 bit stream that is either raw or from a T3FRM Altera Corporation T3 Mapper MegaCore Function (T3MAP) User Guide Specifications Figure 1 illustrates the T3MAP, including the Midbus and AIRbus interfaces. 1 ds3_txclk EXTRACT ds3_txdata Specifications Midbus mrxdat[7:0] mrxena mrxfoh mrxeoh mrxval vco_increase vco_decrease Figure 1. Block Diagram T3 Mapper Interface rxclk_en rxclk rxreset_n T3MAP (T3 Mapper) Midbus mtxdat[7:0] mtxena mtxfoh mtxeoh mtxval ds3_rxclk INSERT ds3_rxdata T3 Mapper Interface read sel irq dtack rdata[7:0] addr[3:0] wdata[7:0] txclk_en txclk txreset_n AIRbus Altera Corporation 11 Specifications T3 Mapper MegaCore Function (T3MAP) User Guide Figure 2 shows the T3MAP providing asynchronous mapping of T3 data over STS1FRM. It also depicts the interface to an external VCO, for the purpose of adjusting the ds3_txclk clock. Figure 2. Core Clocking rxclk RX mrxdat (2) STS1FRM (1) (SONET STS-1 Framer) EXTRACT ds3_txclk ds3_txdata T3MAP (T3 Mapper) txclk TX VCO vco_increase vco_decrease Low-Pass Filter mtxdat (2) INSERT INSERT ds3_rxclk ds3_rxdata Notes : (1) (2) The T3 Mapper also supports the STS-3 and STS-12 framers. For a more detailed view of the Midbus see Figure 1. Functional Description EXTRACT T3 Data Rate The T3MAP provides support of the standard T3 rates by maintaining adaptive control of an external VCO. In this case, a Phase Lock Loop (PLL) is formed using the FIFO buffer fill status as the phase comparator. The FIFO buffer stores extracted T3 data from the SONET SPE. The low-pass filter and VCO are external to the core. A software programmable threshold--either EXT_FIFO_HIGH or EXT_FIFO_LOW--will assert either vco_increase or vco_decrease when the number of bytes in the FIFO buffer is below or above those software registers. This indicates a change is required in the T3 clock rate, ds3_txclk. See "Core Clocking" on page 12. 12 vco_decrease indicates the 32-byte FIFO buffer is emptying and the clock should decrease. vco_increase indicates the 32-byte FIFO buffer is filling and the clock should increase. Altera Corporation T3 Mapper MegaCore Function (T3MAP) User Guide Specifications Data Byte Acceptance The T3MAP accepts data bytes from a SONET framer via a Midbus interface. See "Midbus" on page 14 for more details. Destuffing The destuffing mechanism compensates for the frequency differences between the SONET and T3 data paths. 1 T3 Extraction INSERT T3 Bit Acceptance The T3MAP accepts a raw T3 bit stream, or takes T3 data from the T3FRM with the overhead intact (optional). Asynchronous Mapping In order to generate an output conforming to T3-SPE mapping, the INSERT block takes data from an internal 32-byte deep FIFO buffer containing T3 data collected from the T3 Mapper interface. The INSERT block also inserts the two software programmable overhead communication bits (INS_OH) into the SPE payload where designated by the T3-SPE standard. The INSERT block synchronizes with the Midbus when the INSERT software enable (CTRL_ENABLE) register is asserted. Synchronization status of the INSERT block is kept in the INS_STAT register. Altera Corporation 13 Specifications The T3MAP extracts a T3 bit stream from the input SONET SPE. The T3MAP is also capable of forwarding the T3 bit stream to a T3FRM (optional). The EXTRACT block extracts the two overhead communications bits from the SPE and stores them in a register (EXT_OH). The EXTRACT block synchronizes with the Midbus when the EXTRACT software enable (CTRL_ENABLE) register is asserted. Synchronization status, for the EXTRACT block, is kept in the EXT_STAT register. Specifications T3 Mapper MegaCore Function (T3MAP) User Guide Stuffing The T3MAP bit stuffing mechanism compensates for the frequency differences between T3 and SONET data. The T3MAP also handles SONET positive and negative stuffing. This stuffing action is performed in the SONET network to compensate for frequency differences within the SONET network. SONET positive/negative stuffing, and T3MAP stuffing mechanisms are independent of each other. 1 Interfaces & Protocols A SONET NDF or new pointer event requires a soft restart of the T3MAP. To do a soft restart you need to toggle the INSERT block control enable register, "INS_CTRL - MAP_INSERT Control 'h0" on page 21, and the EXTRACT clock control enable register, "EXT_CTRL - MAP_EXTRACT Control - 'h5" on page 22. The NDF state is not detected by the T3MAP, but it reflects a major movement in the position of the mapped data in the SONET stream requiring the T3MAP to resynchronize itself to the payload. Three interfaces support the T3MAP: the Middle interface (Midbus), the Access to Internal Registers (AIRbus) interface, and the T3 Mapper interface. These interfaces are illustrated in Figure 1. Midbus The Midbus interface is a simple synchronous full-duplex data path bus. The T3MAP Midbus transports data over a single-byte lane in each direction. The required frequency of the Midbus varies depending on the SONET framer supported--see Table 2. Table 2. Midbus Clocks Configuration Clock Rate (MHz) Clock Nominal Enable Rate (1) (txclk_en or rxclk_en) STS-1 6.48 Held active every clock STS-1x3 19.44 Active: 1 in 3 clocks STS-1x12 77.76 Active: 1 in 12 clocks Note: (1) 14 In the case of higher bandwidth interfaces, the signals, txclk_en and rxclk_en, are used to match the data rate with the clock rate. This column shows the expected nominal duty cycle of the enable signal. Altera Corporation T3 Mapper MegaCore Function (T3MAP) User Guide Specifications In the receive direction (RX), the data is transferred from the Midbus master to the slave (T3MAP). In the transmit direction (TX), data is transferred from the slave (T3MAP) to the Midbus master. In each direction the Midbus can carry eight bits per clock cycle. It includes midbus receive data (mrxdat[7:0]) and midbus receive enable (mrxena) lines to indicate a valid data transfer in the RX direction, and midbus transmit data (mtxdat[7:0]) and midbus transmit enable (mtxena) lines to indicate a valid data request in the TX direction. Receive Direction 1 mrxval indicates that the following strobes are valid, see Figure 3. - mrxena indicates mrxdat is user payload (PL) - mrxfoh indicates mrxdat is a fixed frame overhead (A1, A2, J0, Z0, B1, E1, F1) this includes all section and line overhead, and undefined/growth. - mrxeoh indicates mrxdat is an embedded frame overhead (J1, B3) this includes all path overhead. Transmit Direction Figure 4 shows the Midbus signals in the transmit direction, which provide position commands (listed below) that indicate the type of byte being processed on the next clock pulse. mtxval indicates that the following strobes are valid, see Figure 4. - mtxena indicates user payload - mtxfoh indicates a fixed frame overhead (A1, A2, J0, Z0, B1, E1, F1) this includes all section and line overhead, and undefined/growth - mtxeoh indicates an embedded frame overhead (J1, B3) this includes all path overhead When enabled (INS_CTRL register) and synchronized (INS_STAT register) the T3MAP puts valid data on mtxdat on the rising edge of txclk, following an asserted high mtxval. Altera Corporation 15 Specifications Figure 3 shows the Midbus signals in the receive direction. The T3MAP reads data on mrxdat, on the rising edge of rxclk. The following position indicators are also presented with the data. Specifications T3 Mapper MegaCore Function (T3MAP) User Guide Figures 3 and 4 illustrate the Midbus timing for the T3MAP interfacing to an STS-1 Framer. Figure 3. T3MAP Receive Midbus Timing Diagram rxclk mrxdat P L A1 A1 A1 A2 A2 A2 J0 Z0 Z0 J1 P L P L P L B1 U U E1 U U F1 U U B3 P L P L U E1 U U F1 U U B3 PL mrxena mrxval ... mrxfoh mrxeoh Figure 4. T3MAP Transmit Midbus Timing Diagram txclk mtxdat PL PL A1 A1 A1 A2 A2 A2 J0 Z0 Z0 J1 PL PL PL B1 U mtxena mtxval ... mtxfoh mtxeoh AIRbus The AIRbus interface provides access to internal registers using a simple synchronous internal processor bus protocol. This consists of separate read (rdata) and write (wdata) data buses, a data transfer acknowledge (dtack) signal, and a select (sel) signal. An address bus (addr[3:0]) and read (read) signal indicate the location and type of access within the block. The rdata buses and dtack signals can be merged from multiple blocks using a simple OR function. The dtack signal is sustained until the block sel is removed (four-way handshaking) meaning the AIRbus can cross clock domain boundaries. The T3MAP is an AIRbus slave with a data width of eight bits. 1 f 16 The internal registers are run on the current Midbus clock. Thus, the EXTRACT side registers are run using rxclk (rxclk_en), and the INSERT side registers are run with txclk (txclk_en). For more detailed information on the Midbus and AIRbus refer to the Altera web site at http://www.altera.com/IPmegastore. Altera Corporation T3 Mapper MegaCore Function (T3MAP) User Guide Specifications T3 Mapper Interface The T3 Mapper interface is used to convey full T3 data. The T3MAP also provides users with the option of receiving and transmitting framed T3 data from/to a T3 Framer. The DS3 bit stream, including overhead bits, is then mapped into a SONET framer SPE asynchronously. Receive A new DS3 bit is expected to be present on the ds3_rxdata signal at the rising edge of ds3_rxclk--see Figure 5. Specifications Figure 5. Receive T3 Mapper Timing Diagram ds3_rxclk ds3_rxdat X1 I1 I2 I84 F1 I1 I2 I84 Transmit A new DS3 bit is expected to be present on the ds3_txdata signal at the rising edge of ds3_txclk--see Figure 6. Figure 6. Transmit T3 Mapper Timing Diagram ds3_txclk X1 ds3_txdat Performance I1 I2 I84 F1 I1 I2 I84 Table 3 shows the required speed and estimated gate count of the T3MAP in an APEX 20KE device. Table 3. Performance Note (1) LEs ESBs fMAX (MHz) (2) 875 2 44.784 required Notes: (1) (2) Altera Corporation 1 All LE and ESB numbers are approximate as of Feb. 20, 2001. If the T3MAP interfaces to an STS-12 line rate the fMAX will be 77.76 MHz. 17 Specifications I/O Signals T3 Mapper MegaCore Function (T3MAP) User Guide Table 4 lists the I/O signals for the T3MAP. Table 4. I/O Signals Port Direction Description RX Signals rxclk Input Receive data clock rxclk_en Input Receive clock enable rxreset_n Input Receive active low reset txclk Input Transmit data clock txclk_en Input Transmit clock enable txreset_n Input Transmit active low reset mrxdat[7:0] Input Midbus receive data mrxena Input Midbus receive enable mrxfoh Input Midbus receive fixed overhead mrxeoh Input Midbus receive embedded overhead mrxval Input Midbus receive valid data mtxdat[7:0] Output Midbus transmit data mtxena Input Midbus transmit enable mtxfoh Input Midbus transmit fixed overhead mtxeoh Input Midbus transmit embedded overhead mtxval Input Midbus transmit valid data sel Input Select signal. When this signal goes high, it selects internal registers read Input Read/write control signal High: Reads data from data bus Low: Writes data to data bus irq Output Interrupt request signal. When the signal is `1', this indicates an interrupt request dtack Output Data transfer acknowledge signal that comes from the internal registers to indicate the internal registers are ready to send or accept data rdata[7:0] Output Read data signals from internal register addr[3:0] Input Register address wdata[7:0] Input Write data signals to internal register TX Signals Midbus Signals AIRbus Signals T3 Mapper Interface Signals ds3_rxclk 18 Input T3 Mapper Interface receive clock at 44.736 MHz Altera Corporation T3 Mapper MegaCore Function (T3MAP) User Guide Specifications Table 4. I/O Signals Port Description ds3_rxdata Input T3 Mapper Interface receive data--serial bit stream ds3_txclk Input T3 Mapper Interface transmit clock at 44.736 MHz. This clock is controlled by the T3 Mapper via external VCO ds3_txdata Output T3 Mapper Interface transmit data--serial bit stream 1 vco_decrease Output This pin indicates the extract block's FIFO buffer is emptying and the T3 clock rate should be decreased vco_increase Output This pin indicates the extract block's FIFO buffer is filling and the T3 clock rate should be increased 19 Specifications Altera Corporation Direction Specifications Software Interface T3 Mapper MegaCore Function (T3MAP) User Guide Memory Map All addresses are 8-bit accesses and are shown as hex values. The access addresses for each register increment by units of 1, since the accesses are 8 bits wide. Address Register Description 'h0 'h1 INS_CTRL MAP_INSERT Control INS_STAT MAP_INSERT Status 'h2 INS_IS MAP_INSERT Interrupt Status 'h3 INS_IE MAP_INSERT Interrupt Enable 'h4 INS_OH MAP_INSERT Overhead Communications Insert 'h5 'h6 EXT_CTRL MAP_EXTRACT Control EXT_STAT MAP_EXTRACT Status 'h7 EXT_IS MAP_EXTRACT Interrupt Status 'h8 EXT_IE MAP_EXTRACT Interrupt Enable 'h9 EXT_OH MAP_EXTRACT Overhead Communications Extract 'hA EXT_FIFO_HIGH MAP_EXTRACT FIFO High Mark 'hB EXT_FIFO_LOW MAP_EXTRACT FIFO Low Mark Registers The following is a list of access codes used to describe the type of register bits. Code 20 Description RW RO Read/Write RW1C Read/Write 1 to Clear RW0S Read/Write 0 to Set RTC Read to Clear RTS Read to Set RTCW Read to Clear/Write RTSW Read to Set/Write RWTC Read/Write any value to Clear RWTS Read/Write any value to Set RWSC Read/Write Self-Clearing RWSS Read/Write Self-Setting UR0 Unused bits/Read as 0 UR1 Unused bits/Read as 1 Read-Only Altera Corporation T3 Mapper MegaCore Function (T3MAP) User Guide Specifications INSERT Block Register Description INS_CTRL - MAP_INSERT Control - 'h0 Field ENABLE Bits 0 Access RW Function When '0', MAP_INSERT produces static undefined output ('b1111 1111). Initially after rising edge MAP_INSERT will synchronize to mtxefp, then produce valid output. Default 0 INS_STAT - MAP_INSERT Status - 'h1 Field 0 Access RO Function When asserted, the T3MAP has been synchronized to the mtxeoh pulse. Default 0 INS_IS - MAP_INSERT Interrupt Status - 'h2 Field Bits Access Function Default FIFO_CORRUPT 1 RTC A '1' indicates MAP_INSERT's internal FIFO has either underflowed or overflowed. 0 STS_CORRUPT 0 RTC A '1' indicates MAP_INSERT has received an mtxeoh/mtxena pattern that it could not handle (90 ticks between poh strobes with 84 enable intermediate). A software resynchronization is required. 0 INS_IE - MAP_INSERT Interrupt Enable - 'h3 Field Bits Access Function Default FIFO_CORRUPT 1 RW This is the MAP_INSERT FIFO_CORRUPT interrupt enable. 0 STS_CORRUPT 0 RW This is the MAP_INSERT STS_CORRUPT interrupt enable. 0 INS_OH - MAP_INSERT Overhead Communications Insert - 'h4 Field COMM_INSERT Altera Corporation Bits 1:0 Access RW Function This register controls overhead communications bits being inserted into byte C3. Default 0 21 1 Specifications MAP_SYNC Bits Specifications T3 Mapper MegaCore Function (T3MAP) User Guide EXTRACT Block Register Description EXT_CTRL - MAP_EXTRACT Control - 'h5 Field ENABLE Bits 0 Access RW Function Default When '0', MAP_EXTRACT produces static undefined output 0 ('b0). Initially after rising edge MAP_EXTRACT will synchronize to mrxeoh, then produce valid output. EXT_STAT - MAP_EXTRACT Status - 'h6 Field MAP_SYNC Bits 0 Access RO Function Default When asserted, the T3MAP has been synchronized to the mrxeoh pulse. 0 EXT_IS - MAP_EXTRACT Interrupt Status - 'h7 Field Bits Access Function Default FIFO_CORRUPT 1 RTC A '1' indicates the MAP_EXTRACT register's internal FIFO 0 has either underflowed or overflowed. STS_CORRUPT 0 RTC A '1' indicates MAP_EXTRACT register has received a 0 mrxeoh/mrxena pattern that it could not handle. A software resynchronization is required. EXT_IE - MAP_EXTRACT Interrupt Enable - 'h8 Field Bits Access Function Default FIFO_CORRUPT 1 RW This is the MAP_EXTRACT FIFO_CORRUPT interrupt enable. 0 STS_CORRUPT 0 RW This is the MAP_EXTRACT STS_CORRUPT interrupt enable. 0 EXT_OH - MAP_EXTRACT Overhead Communications Extract - 'h9 Field Bits COMM_EXTRACT 1:0 22 Access RO Function Default These are the overhead communications bits extracted from 0 byte C3. Altera Corporation T3 Mapper MegaCore Function (T3MAP) User Guide Specifications EXT_FIFO_HIGH - MAP_EXTRACT FIFO High Mark - 'hA Field MARK Bits 4:0 Access RW Function Default This is a threshold value for the number of bytes in the FIFO 0 buffer. When the number of bytes in the FIFO buffer exceeds this value, the FIFO buffer is getting full. The vco_increase signal is then toggled and the ds3_txclk is increased. 1 EXT_FIFO_LOW - MAP_EXTRACT FIFO Low Mark - 'hB MARK Altera Corporation Bits 4:0 Access RW Function Default This is the threshold value for the number of bytes in the 0 FIFO buffer. When the number of bytes in the FIFO buffer falls below this value, the FIFO buffer is getting empty. The vco_decrease signal is then toggled and the ds3_txclk is decreased. 23 Specifications Field Notes: Getting Started User Guide Test-drive a T3MAP This section describes how to obtain a variant from the T3 Mapper MegaCore(R) Function (T3MAP). It explains how to install the T3MAP on your PC, and walks you through the process of implementing the variant in a design. Only when you are ready to generate programming files, do you need to obtain licenses through your local Altera sales representative. Design Walkthrough This design walkthrough involves the following steps: 1. Obtaining and installing the T3MAP. 2. Generating a custom T3MAP for your system using the MegaWizard(R) Plug-In. 3. Implementing the rest of your system using the AHDL, VHDL, or Verilog HDL. 4. Compiling your design and performing place-and-route. 5. Licensing the T3MAP to configure the device. The instructions assume that: Altera Corporation You are using a PC You are familiar with the Quartus II software The most current available version of the Quartus II software is installed in the default location You are using the OpenCore feature to test-drive a T3MAP, or you have licensed it. 25 Getting Started You can test-drive a T3MAP using the Altera(R) OpenCoreTM feature-- within the QuartusTMII software--to instantiate it, to perform place-androute, to perform static timing analysis, and to simulate it using a thirdparty simulator, within your custom logic. 2 Getting Started Obtaining & Installing the T3MAP T3 Mapper MegaCore Function (T3MAP) User Guide In order to start using the T3MAP, you need to obtain the MegaCore package from your local Altera representative. The package includes: MegaWizard Plug-In - Encrypted gate level netlist - Place-and-route constraints (where necessary) - Secure RTL simulation model Sanity testbench Midbus and AIRbus Interface Functional Specifications Data Sheet User Guide Installing the MegaCore Files Use the MegaWizard Plug-In to generate the files and install them on your PC. The following instructions describe this process. 1 Before you can use the MegaWizard Plug-In, your PC must have Java runtime environment version 1.2 installed. This file can be downloaded from the Java web site, http://www.java.sun.com. For Windows, follow the instructions below: 26 1. Click Run (Start Menu) 2. Type <path name>\<filename>.exe, where <pathname> is the location of the downloaded T3MAP, and <filename> is the filename of the T3MAP. Click OK. 3. The MegaCore Installer dialog box appears. Follow the wizard instructions to finish the installation. 4. After you have finished installing the files, you must specify the directory in which you installed them as a user library in the Quartus II software. Search for "User Libraries" in Quartus II Help for instructions on how to add these libraries. Altera Corporation T3 Mapper MegaCore Function (T3MAP) User Guide Generating a Custom T3MAP GettingGetting Started This section describes the design flow using the Altera T3MAP, and the Quartus II development system. A MegaWizard Plug-In Manager is provided with the T3MAP. The MegaWizard Plug-In Manager--used within the Quartus II software-- allows you to create, or modify design files to meet the needs of your application. You can use them to instantiate the T3MAP in your design file. To create a custom T3MAP using the wizard, follow these steps: 1. Start the MegaWizard Plug-In by choosing the MegaWizard Plug-In Manager command (File menu) in the Quartus II software. The MegaWizard Plug-In Manager dialog box is displayed. Refer to Quartus II Help for detailed instructions on how to use the MegaWizard Plug-In Manager. 2. Specify that you want to create a new custom variant and click Next. 3. On the second page of the wizard, select T3MAP from the T3 folder. 4. Choose the type of output files, specify the folder and name for the files the wizard creates, and click Next. 5. Select the optional parameters and choices that you require. 6. The final screen lists the design files that the wizard creates. Click Finish. Implementing the System Once you have created your custom T3MAP, you are ready to implement it. You can use the files generated by the MegaWizard in your design. You can use the Quartus II software, or other EDA tools to create your design. Compiling & Performing Place & Route You can use the Quartus II software to compile and place-and-route your design. Refer to Quartus II Help for instructions on performing compilation. After you have verified that your design is functionally correct, you are ready to perform system verification. Performing Synthesis Compilation & Post-Routing Simulation The Quartus II software works seamlessly with tools from all EDA vendors, including: Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, and Viewlogic. After you have licensed the T3MAP, you can generate EDIF, VHDL, Verilog HDL, and Standard Delay Output Files from the Quartus II software and use them with your existing EDA tools to perform functional modeling and post-route simulation of your design. Altera Corporation 27 Getting Started 1 2 Getting Started T3 Mapper MegaCore Function (T3MAP) User Guide Using Third-Party EDA Tools To synthesize your design in a third-party EDA tool and perform postroute simulation, follow these steps: 1. Create your custom design instantiating a T3MAP. 2. Synthesize the design using your third-party EDA tool. Your EDA tool should treat the T3MAP as a black box by either setting attributes or ignoring the instantiation. 3. After compilation, generate a hierarchical netlist file in your thirdparty EDA tool. 4. Open your netlist file in the Quartus II software. 5. Add the pre-synthesized and encrypted .e.vqm.v file from your working directory. Using the Quartus II Software 28 1. Select the Compile mode (Processing menu). 2. Specify the Compiler settings in the Compiler Settings dialog box (Processing menu), or use the Compiler Settings wizard. 3. Specify the user libraries for the project and the order in which the Compiler searches the libraries. 4. Specify the input settings for the project. Choose EDA Tool Settings (Project menu). Select Custom EDIF in the Design Entry/Synthesis Tool list. Click Settings. In the EDA Tool Input Settings dialog box, make sure that the relevant tool name or option is selected in the Design Entry/Synthesis Tool list. 5. Depending on the type of output file you want, specify Verilog HDL output settings or VHDL output settings in the General Settings dialog box (Project menu). Use the 1993 VHDL Language option. 6. Add the pre-synthesized and encrypted .e.vqm.v file from your working directory. 7. Compile your design. The Quartus II Compiler synthesizes and performs place-and-route on your design, and generates output and programming files. 8. Import your Quartus II-generated output files (.edo, .vho, .vo, or .sdo) into your third-party EDA tool for post-route, device-level, and system-level simulation. Altera Corporation GettingGetting Started T3 Mapper MegaCore Function (T3MAP) User Guide Functional Simulations Using Visual IP Models This section describes Visual IP Model verification and provides instructions for using Visual IP Models. Figure 1 shows an example Visual IP Model arrangement. Figure 1. General Arrangement Tb (RTL) Hook-Up 2 Visual IP Model Utility 1 (RTL) 1 Utility 2 (RTL) Getting Started Black Box Verilog or VHDL Wrapper Empty I/O Declaration User Design (RTL) Utility 3 (RTL) The top level of the Visual IP Model can be treated as a sub-block of a design, or as the main design unit. Downloading & Installing Visual IP Software The Visual IP software facilitates the use of Visual IP simulation models by allowing waveforms to be viewed using third-party simulation tools. To view the simulation model, you must have Visual IP software installed on your system. To download the software, or for instructions on how to use it, refer to the Altera web site, http://www.altera.com/IPmegastore. Licensing & Configuring a Device After you have compiled and analyzed your design, you are ready to configure your targeted Altera semiconductor device. If you are evaluating the T3MAP with the OpenCore feature, you must license the function before you can generate programming files. To obtain a licence contact your local Altera sales representative. 1 Altera Corporation All current T3MAP variants use a single license with ordering code: PLSM-T3MAP. 29 Notes: