MPC8309CVMAGDCA - NXP SEMICONDUCTORS

Freescale Semiconductor

Technical Data

This document provides an overview of the MPC8309

PowerQUICC II Pro processor features. The MPC8309 is a

cost-effective, highly integrated communications processor

that addresses the requirements of several networking

applications, including residential gateways,

modem/routers, industrial control, and test and measurement

applications. The MPC8309 extends current PowerQUICC

offerings, adding higher CPU performance, additional

functionality, and faster interfaces, while addressing the

requirements related to time-to-market, price, power

consumption, and board real estate. This document describes

the electrical characteristics of MPC8309.

T o locate published errata or updates for this document, refer

to the MPC8309 product summary page on our website

listed on the back cover of this document or contact your

local Freescale sales office.

Document Number:MPC8309EC

Rev 4, 12/2014

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 1 1

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13

6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 22

9. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10. HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1 1. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

12. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

13. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

14. eSDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

15. FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

16. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

17. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

18. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

19. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

20. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

21. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

22. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 52

23. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

24. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

25. System Design Information . . . . . . . . . . . . . . . . . . . 75

26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 78

27. Document Revision History . . . . . . . . . . . . . . . . . . . 80

MPC8309

PowerQUICC II Pro Integrated

Communications Processor

Family Hardware Specifications

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

2Freescale Semiconductor

Overview

1 Overview

The MPC8309 incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology,

which includes 16 Kbytes of each L1 instruction and data caches, dual integer uni ts, and on-chip memory

management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and

a 16/32-bit DDR2 memory controller with 8-bit ECC.

A new communications complex based on QUICC Engine technology forms the heart of the networking

capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit

RISC controller. Protocol support is provided by the main workhorses of the device—the unified

communication controllers (UCCs). A block diagram of the MPC8309 is shown in the following figure.

Figure 1. MPC8309 Block Diagram

Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII

Ethernet, HDLC and TDM.

In summary, the MPC8309 provides users with a highly integrated, fully programmable communications

processor. This helps to ensure that a low-cost system solution can be quickly developed and offers

flexibility to accommodate new standards and evolving system requirements.

2 RMII/MII

2x TDM Ports

16-KB

D-Cache

16-KB

I-Cache

e300c3 Core with Powe r

2x DUART

Interrupt

I2C

Timers

GPIO

Enhanced DDR2

Controller

Baud Rate

Generators

Accelerators

Single 32-bit RISC CP Serial DMA

Serial Interface

QUICC Engine™ Block

UCC7

UCC5

UCC3

UCC2

UCC1

Time Slot Assigner

16 KB Multi-User RAM

FPU

Management

SPI

RTC

Local Bus

2x HDLC

1 RMII/MII

2x IEEE 1588

USB 2.0 HS

Host/Device/OTG

ULPI

4 FlexCAN

eSDHC

48 KB Instruction RAM

DMA

Engine 2

DMA

Engine 1

PCI Controller

Sequencer

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 3

Overview

1.1 Features

The major features of the device are as follows:

• e300c3 Power Architecture processor core

— Enhanced version of the MPC603e core

— High-performance, superscalar processor core with a four-stage pipeline and low interrupt

latency times

— Floating-point, dual integer units, load/store, system register, and branch processing units

— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities

— Dynamic power management

— Enhanced hardware program debug features

— Software-compatible with Freescale processor families implementing Power Architecture

technology

— Separate PLL that is clocked by the system bus clock

— Performance monitor

• QUICC Engine block

— 32-bit RISC controller for flexible support of the communications peripherals with the

following features:

– One clock per instruction

– Separate PLL for operating frequency that is independent of system’s bus and e300 core

frequency for power and performance optimization

– 32-bit instruction object code

– Executes code from internal IRAM

– 32-bit arithmetic logic unit (ALU) data path

– Modular architecture allowing for easy functional enhancements

– Slave bus for CPU access of registers and multiuser RAM space

– 48 Kbytes of instruction RAM

– 16 Kbytes of multiuser data RAM

– Serial DMA channel for receive and transmit on all serial channels

— Five unified communication controllers (UCCs) supporting the following protocols and

interfaces:

– 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.

– IEEE Std. 1588™ support

– HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)

– HDLC Bus (bit rate up to 10 Mbps)

– Asynchronous HDLC (bit rate up to 2 Mbps)

– Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each

running at 64 kbps

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

4Freescale Semiconductor

Overview

For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference

Manual with Protocol Interworking.

• DDR SDRAM memory controller

— Programmable timing supporting DDR2 SDRAM

— Integrated SDRAM clock generation

— Supports 8-bit ECC

— 16/32-bit data interface, up to 333-MHz data rate

— 14 address lines

— The following SDRAM configurations are supported:

– Up to two physical banks (chip selects), 512-Mbyte addressable space for 32 bit data

interface

– 64-Mbit to 2-Gbit devices with x8/x16/x32 data ports (no direct x4 support)

— One 16-bit device or two 8-bit devices on a 16-bit bus, or two 16-bit devices or four 8-bit

devices on a 32-bit bus Support for up to 16 simultaneous open pages for DDR2

— Two clock pair to support up to 4 DRAM devices

— Supports auto refresh

— On-the-fly power management using CKE

• Enhanced local bus controller (eLBC)

— Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz

— Eight chip selects supporting eight external slaves

– Four chip selects dedicated

– Four chip selects offered as multiplexed option

— Supports boot from parallel NOR Flash and parallel NAND Flash

— Supports programmable clock ratio dividers

— Up to eight-beat burst transfers

— 16- and 8-bit ports, separate LWE for each 8 bit

— Three protocol engines available on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

– NAND Flash control machine (FCM)

— Variable memory block sizes for FCM, GPCM, and UPM mode

— Default boot ROM chip select with configurable bus width (8 or 16)

— Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC

slave devices

• Integrated programmable interrupt controller (IPIC)

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for external and internal discrete interrupt sources

— Programmable highest priority request

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 5

Overview

— Six groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Unique vector number for each interrupt source

•PCI interface

— Designed to comply with PCI Local Bus Specification, Revision 2.3

— 32-bit PCI interface operating at up to 66 MHz

— PCI 3.3-V compatible

— Not 5-V compatible

— Support for host and agent modes

— Support for PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses and support for delayed read transactions

— Support for posting of processor-to-PCI and PCI-to-memory writes

— On-chip arbitration, supporting three masters on PCI

— Arbiter support for two-level priority request/grant signal pairs

— Support for accesses to all PCI address spaces

— Support for parity

— Selectable hardware-enforced coherency

— Address translation units for address mapping between host and peripheral

— Mapping from an external 32-/64-bit address space to the internal 32-bit local space

— Support for dual address cycle (DAC) (as a target only)

— Internal configuration registers accessible from PCI

— Selectable snooping for inbound transactions

— Four outbound Translation Address Windows

– Support for mapping 32-bit internal local memory space to an external 32-bit PCI address

space and translating that address within the PCI space

— Four inbound Translation Address Windows corresponding to defined PCI BARs

– The first BAR is 32-bits and dedicated to on-chip register access

– The second BAR is 32-bits for general use

– The remaining two BARs may be 32- or 64-bits and are also for general use

• Enhanced secure digital host controller (eSDHC)

— Compatible with the SD Host Controller Standard Specification Version 2.0 with test event

— Compatible with the MMC System Specification Version 4.2

— Compatible with the SD Memory Card Specification Version 2.0 and supports the high capacity

SD memory card

— Compatible with the SD Input/Output (SDIO) Card Specification, Version 2.0

— Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,

MMCplus, and RS-MMC cards

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

6Freescale Semiconductor

Overview

— Card bus clock frequency up to 33.33 MHz.

— Supports 1-/4-bit SD and SDIO modes, 1-/4-bit modes

– Up to 133 Mbps data transfer for SD/SDIO/MMC cards using 4 parallel data lines

— Supports block sizes of 1 ~ 4096 bytes

• Universal serial bus (USB) dual-role controller

— Designed to comply with Universal Serial Bus Revision 2.0 Specification

— Supports operation as a stand-alone USB host controller

— Supports operation as a stand-alone USB device

— Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations.

Low speed is only supported in host mode.

• FlexCAN module

— Full implementation of the CAN protocol specification version 2.0B

— Up to 64 flexible message buffers of zero to eight bytes data length

— Powerful Rx FIFO ID filtering, capable of matching incoming IDs

— Selectable backwards compatibility with previous FlexCAN module version

— Programmable loop-back mode supporting self-test operation

— Global network time, synchronized by a specific message

— Independent of the transmission medium (an external transceiver is required)

— Short latency time due to an arbitration scheme for high-priority messages

• Dual I2C interfaces

— Two-wire interface

— Multiple-master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

—I

2C1 can be used as the boot sequencer

• DMA Engine1

— Support for the DMA engine with the following features:

– Sixteen DMA channels

– All data movement via dual-address transfers: read from source, write to destination

– T ransfer control descriptor (TCD) organized to support two-deep, nested transfer operations

– Channel activation via one of two methods (for both the methods, one activation per

execution of the minor loop is required):

– Explicit software initiation

– Initiation via a channel-to-channel linking mechanism for continuous transfers

(independent channel linking at end of minor loop and/or major loop)

– Support for fixed-priority and round-robin channel arbitration

– Channel completion reported via optional interrupt requests

— Support for scatter/gather DMA processing

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 7

Electrical Characteristics

• IO Sequencer

• Direct memory access (DMA) controller (DMA Engine 2)

— Four independent fully programmable DMA channels

— Concurrent execution across multiple channels with programmable bandwidth control

— Misaligned transfer capability for source/destination address

— Data chaining and direct mode

— Interrupt on completed segment, error, and chain

• DUART

— Supports 2 DUART

— Each has two 2-wire interfaces (RxD, TxD)

– The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

• Serial peripheral interface (SPI)

— Master or slave support

• Power managemnt controller (PMC)

— Supports core doze/nap/sleep/ power management

— Exits low power state and returns to full-on mode when

– The core internal time base unit invokes a request to exit low power state

– The power management controller detects that the system is not idle and there are

outstanding transactions on the internal bus or an external interrupt.

• Parallel I/O

— General-purpose I/O (GPIO)

– 56 parallel I/O pins multiplexed on various chip interfaces

– Interrupt capability

• System timers

— Periodic interrupt timer

— Software watchdog timer

— Eight general-purpose timers

• Real time clock (RTC) module

— Maintains a one-second count, unique over a period of thousands of years

— Two possible clock sources:

– External RTC clock (RTC_PIT_CLK)

– CSB bus clock

• IEEE Std. 1149.1™ compliant JTAG boundary scan

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8309. The MPC8309 is currently targeted to these specifications. Some of these specifications are

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

8Freescale Semiconductor

Electrical Characteristics

independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer

design specifications.

2.1 Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1 Absolute Maximum Ratings

The following table provides the absolute maximum ratings.

Table 1. Absolute Maximum Ratings1

Characteristic Symbol Max Value Unit Notes

Core supply voltage VDD –0.3 to 1.26 V —

PLL supply voltage AVDD1

AVDD2

AVDD3

–0.3 to 1.26 V —

DDR2 DRAM I/O voltage GVDD –0.3 to 1.98 V —

PCI, Local bus, DUART, system control and power management,

I2C, SPI, MII, RMII, MII management, eSDHC, FlexCAN, USB and

JTAG I/O voltage

OVDD –0.3 to 3.6 V 2

Input voltage DDR2 DRAM signals MVIN –0.3 to (GVDD +0.3) V 3

DDR2 DRAM reference MVREF –0.3 to (GVDD +0.3) V 3

Local bus, DUART, SYS_CLK_IN,

system control and power

management, I2C, SPI, and JTAG

signals

OVIN –0.3 to (OVDD +0.3) V 4

PCI OVIN –0.3 to (OVDD + 0.3) V

Storage temperature range TSTG –55to150 C—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.

3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

power-on reset and power-down sequences.

4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

power-on reset and power-down sequences.

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 9

Electrical Characteristics

2.1.2 Power Supply Voltage Specification

The following table provides the recommended operating conditions for the MPC8309. Note that these

values are the recommended and tested operating conditions. Proper device operation outside of these

conditions is not guaranteed.

The following figure shows the undershoot and overshoot voltages at the interfaces of the MPC8309

Figure 2. Overshoot/Und ershoot Voltage for GVDD/OVDD

Table 2. Recommended Operating Conditions

Characteristic Symbol Recommended

Value Unit Note

Core supply voltage VDD 1.0 V ± 50 mV V 1

PLL supply voltage AVDD1

AVDD2

AVDD3

1.0 V ± 50 mV V 1

DDR2 DRAM I/O voltage GVDD 1.8 V ± 100 mV V 1

PCI, Local bus, DUART, system control and power management,

I2C, SPI, MII, RMII, MII management, eSDHC, FlexCAN,USB and

JTAG I/O voltage

OVDD 3.3 V ± 300 mV V 1, 3

Junction temperature TA/TJ0to105 C2

Notes:

1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative

direction.

2. Minimum temperature is specified with TA(Ambient Temperature); maximum temperature is specified with TJ(Junction

Temperature).

3. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.

GND

GND – 0.3 V

GND – 0.7 V Not to Exceed 10%

G/OVDD + 20%

G/OVDD

G/OVDD + 5%

of tinterface1

1. tinterface refers to the clock period associated with the bus clock interface.

VIH

VIL

Note:

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

10 Freescale Semiconductor

Electrical Characteristics

2.1.3 Output Driver Characteristics

The following table provides information on the characteristics of the output driver strengths.

2.1.4 Input Capacitance Specification

The following table describes the input capacitance for the SYS_CLK_IN pin in the MPC8309.

2.2 Power Sequencing

The device does not require the core supply voltage (VDD) and I/O supply voltages (GVDD and OVDD) to

be applied in any particular order. Note that during power ramp-up, before the power supplies are stable

and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input

and output pins are actively driven and cause contention and excessive current. In order to avoid actively

driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O

voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up. In the case

where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before

the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are

stable, wait for a minimum of 32 clock cycles before negating PORESET.

NOTE

There is no specific power down sequence requirement for the device. I/O

voltage supplies (GVDD and OVDD) do not have any ordering requirements

with respect to one another.

Table 3. Output Drive Capability

Driver Type Output Impedance

()Supply Voltage (V)

Local bus interface utilities signals 42 OVDD =3.3

PCI Signal 25

DDR2 signal 18 GVDD =1.8

DUART, system control, I2C, SPI, JTAG 42 OVDD =3.3

GPIO signals 42 OVDD =3.3

Table 4. Input Capacitance Specification

Parameter/Condition Symbol Min Max Unit Note

Input capacitance for all pins except SYS_CLK_IN and

QE_CLK_IN

CI68pF—

Input capacitance for SYS_CLK_IN and QE_CLK_IN CICLK_IN 10 — pF 1

Note:

1. The external clock generator should be able to drive 10 pF.

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 11

Power Characteristics

Figure 3. MPC8309 Power-Up Sequencing Example

3 Power Characteristics

The typical power dissipation for this family of MPC8309 devices is shown in the following table.

Table 5. MPC8309 Power Dissipation

Core

Frequency (MHz) QUICC Engine

Frequency (MHz) CSB

Frequency (MHz) Typical Maximum Unit Note

266 233 133 0.341 0.920 W 1, 2, 3

333 233 133 0.361 0.938 W 1, 2, 3

400 233 133 0.381 0.969 W 1,2,3

417 233 167 0.429 1.003 W 1,2,3

Notes:

1. The values do not include I/O supply power (OVDD and GVDD), but it does include VDD and AVDD power. For I/O power

values, see Table 6 .

2. Typical power is based on a nominal voltage of VDD = 1.0 V, ambient temperature, and the core running a Dhrystone

benchmark application. The measurements were taken on the evaluation board using WC process silicon.

3. Maximum power is based on a voltage of VDD = 1.05 V, WC process, a junction TJ = 105C, and a smoke test code.

90%

Core Voltage (VDD)

I/O Voltage (GVDD and OVDD)

0.7 V

PORESET

>= 32 tSYS_CLK_IN / PCI_SYNC_IN

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

12 Freescale Semiconductor

Clock Input Timing

The following table shows the estimated typical I/O power dissipation for the device.

4 Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8309.

NOTE

The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This

should be enforced especially on clock signals. Rise time refers to signal

transitions from 10% to 90% of OVDD; fall time refers to transitions from

90% to 10% of OVDD.

4.1 DC Electrical Characteristics

The following table provides the clock input (SYS_CLK_IN/PCI_SYNC_IN) DC specifications for the

MPC8309. These specifications are also applicable for QE_CLK_IN.

Table 6. Typical I/O Power Dissipation

Interface Parameter GVDD

(1.8 V) OVDD

(3.3 V) Unit Comments

DDR I/O

65% utilization

1.8 V

Rs = 20 

Rt = 50 

1 pair of clocks

266 MHz, 1 16 bits

0.149

—W —

Local bus I/O load = 25 pF

1 pair of clocks

66 MHz, 26 bits

—0.415W 1

QUICC Engine block and other I/Os TDM serial, HDLC/TRAN serial,

DUART, MII, RMII, Ethernet

management, USB, PCI, SPI, Timer

output, FlexCAN, eSDHC

Note:

1. Typical I/O power is based on a nominal voltage of VDD = 3.3V, ambient temperature, and the core running a Dhrystone

benchmark application. The measurements were taken on the evaluation board using WC process silicon.

Table 7. SYS_CLK_IN DC Electrical Characteristics

Parameter Condition Symbol Min Max Unit

Input high voltage — VIH 2.4 OVDD +0.3 V

Input low voltage — VIL –0.3 0.4 V

SYS_CLK_IN input current 0 V VIN OVDD IIN —±5A

SYS_CLK_IN input current 0 V VIN 0.5 V or

OVDD – 0.5 V VIN OVDD

IIN —±5A

SYS_CLK_IN input current 0.5 V VIN OVDD – 0.5 V IIN —±50A

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 13

RESET Initialization

4.2 AC Electrical Characteristics

The primary clock source for the MPC8309 can be one of two inputs, SYS_CLK_IN or PCI_SYNC_IN,

depending on whether the device is configured in PCI host or agent mode. The following table provides

the clock input (SYS_CLK_IN/PCI_SYNC_IN) AC timing specifications for the MPC8309. These

specifications are also applicable for QE_CLK_IN.

5 RESET Initialization

This section describes the AC electrical specifications for the reset initialization timing requirements of

the MPC8309. The following table provides the reset initialization AC timing specifications for the reset

component(s).

Table 8. SYS_CLK_IN AC Timing Specifications

Parameter/Condition Symbol Min Typical Max Unit Note

SYS_CLK_IN frequency fSYS_CLK_IN 24 — 66.67 MHz 1

SYS_CLK_IN cycle time tSYS_CLK_IN 15 — 41.6 ns —

SYS_CLK_IN rise and fall time tKH, tKL 1.1 — 2.8 ns 2

PCI_SYNC_IN rise and fall time tPCH, tPCL 1.1 — 2.8 ns 2

SYS_CLK_IN duty cycle tKHK/tSYS_CLK_

40 — 60 % 3

SYS_CLK_IN jitter — — — ±150 ps 4, 5

Notes:

1. Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating

frequencies.

2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.

6. Spread spectrum is allowed up to 1% down-spread @ 33kHz (max rate).

Table 9. RESET Initialization Timing Specifications

Parameter/Condition Min Max Unit Note

Required assertion time of HRESET to activate reset flow 32 — tSYS_CLK_IN 1

Required assertion time of PORESET with stable clock applied to

SYS_CLK_IN or PCI_SYNC_IN (in agent mode)

32 — tSYS_CLK_IN 1

HRESET assertion (output) 512 — tSYS_CLK_IN 1

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

14 Freescale Semiconductor

DDR2 SDRAM

The following table provides the PLL lock times.

5.1 Reset Signals DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8309 reset signals mentioned in

Table 9.

6DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the

MPC8309. Note that DDR2 SDRAM is GVDD(typ) = 1.8 V.

6.1 DDR2 SDRAM DC Electrical Characteristics

The following table provides the recommended operating conditions for the DDR2 SDRAM component(s)

of the MPC8309 when GVDD(typ) = 1.8 V.

The following table provides the DDR2 capacitance when GVDD(typ) = 1.8 V.

Input setup time for POR configuration signals

(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET

4—t

SYS_CLK_IN 1, 2

Input hold time for POR config signals with respect to negation of

HRESET

0 — ns 1, 2

Notes:

1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8309 PowerQUICC

II Pro Integrated Communications Processor Family Reference Manual.

2. POR configuration signals consist of CFG_RESET_SOURCE[0:3].

Table 10. PLL Lock Times

Parameter/Condition Min Max Unit Note

PLL lock times — 100 s—

Table 11. Reset Signals DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit Note

Output high voltage VOH IOH = –6.0 mA 2.4 — V 1

Output low voltage VOL IOL = 6.0 mA — 0.5 V 1

Output low voltage VOL IOL = 3.2 mA — 0.4 V 1

Input high voltage VIH —2.0OV

DD +0.3 V 1

Input low voltage VIL —–0.30.8V—

Input current IIN 0 V VIN OVDD — ±5 A—

Note:

1. This specification applies when operating from 3.3 V supply.

Table 9. RESET Initialization Timing Specifications (continued)

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 15

DDR2 SDRAM

6.2 DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR2 SDRAM interface.

6.2.1 DDR2 SDRAM Input AC Timing Specifications

This table provides the input AC timing specifications for the DDR2 SDRAM (GVDD(typ) = 1.8 V).

The following table provides the input AC timing specifications for the DDR2 SDRAM interface.

Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit Note

I/O supply voltage GVDD 1.7 1.9 V 1

I/O reference voltage MVREF 0.49 GVDD 0.51 GVDD V2

I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V 3

Input high voltage VIH MVREF+ 0.125 GVDD +0.3 V —

Input low voltage VIL –0.3 MVREF – 0.125 V —

Output leakage current IOZ –9.9 9.9 A4

Output high current (VOUT = 1.35 V) IOH –13.4 — mA —

Output low current (VOUT = 0.280 V) IOL 13.4 — mA —

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5  GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V  VOUT GVDD.

Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit Note

Input/output capacitance: DQ, DQS CIO 68pF1

Delta input/output capacitance: DQ, DQS CDIO —0.5pF1

Note:

1. This parameter is sampled. GVDD = 1.8 V ± 0.100 V, f = 1 MHz, TA =25°C, V

OUT = GVDD 2,

VOUT (peak-to-peak) = 0.2 V.

Table 14. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions with GVDD of 1.8 V± 100mV.

Parameter Symbol Min Max Unit Note

AC input low voltage VIL — MVREF – 0.25 V —

AC input high voltage VIH MVREF + 0.25 — V —

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

16 Freescale Semiconductor

DDR2 SDRAM

The following figure shows the input timing diagram for the DDR controller.

Figure 4. DDR Input Timing Diagram

6.2.2 DDR2 SDRAM Output AC Timing Specifications

The following table provides the output AC timing specifications for the DDR2 SDRAM interfaces.

Table 1 5. DDR 2 SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of 1.8V ± 100mV.

Parameter Symbol Min Max Unit Note

Controller skew for MDQS—MDQ/MDM tCISKEW ps 1, 2

266 MHz –750 750

Notes:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

is captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the equation: tDISKEW =±(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute

value of tCISKEW.

Table 16. DDR2 SDRAM Output AC Timing Specifications

At recommended operating conditions with GVDD of 1.8V ± 100mV.

Parameter Symbol1Min Max Unit Note

MCK cycle time, (MCK/MCK crossing) tMCK 5.988 8 ns 2

ADDR/CMD output setup with respect to MCK tDDKHAS ns 3

333 MHz

266 MHz

2.4

2.5

—

ADDR/CMD output hold with respect to MCK tDDKHAX ns 3

333 MHz

266 MHz

2.4

2.5

—

MCK[n]

MCK[n] tMCK

MDQ[x]

MDQS[n]

tDISKEW

D1D0

tDISKEW

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 17

DDR2 SDRAM

MCS output setup with respect to MCK tDDKHCS ns 3

333 MHz

266 MHz

2.4

2.5

—

MCS output hold with respect to MCK tDDKHCX ns 3

333 MHz

266 MHz

2.4

2.5

—

MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4

MDQ/MDM output setup with respect to MDQS tDDKHDS,

tDDKLDS

ns 5

333 MHz

266 MHz

0.8

0.9

—

MDQ/MDM output hold with respect to MDQS tDDKHDX,

tDDKLDX

ps 5

333 MHz

266 MHz

900

1100

—

MDQS preamble start tDDKHMP 0.75 x tMCK —ns6

MDQS epilogue end tDDKHME 0.4 x tMCK 0.6 x tMCK ns 6

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD

setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied

cycle.

4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)

from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjusts in the

CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. See the MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual

for a description and understanding of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data

mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. tDDKHMP follows the symbol conventions described in note 1.

Table 16. DDR2 SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions with GVDD of 1.8V ± 100mV.

Parameter Symbol1Min Max Unit Note

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

18 Freescale Semiconductor

DDR2 SDRAM

The following figure shows the DDR SDRAM output timing for the MCK to MDQS skew measurement

(tDDKHMH).

Figure 5. Timing Diagram for tDDKHMH

The following figure shows the DDR2 SDRAM output timing diagram.

Figure 6. DDR2 SDRAM Output Timing Diagram

MDQS

MCK

MCK tMCK

MDQS

tDDKHMH(max) = 0.6 ns

tDDKHMH(min) = –0.6 ns

ADDR/CMD

tDDKHAS ,tDDKHCS

tDDKHMH

tDDKLDS

tDDKHDS

MDQ[x]/

MDQS[n]

MCK[n]

MCK[n] tMCK

tDDKLDX

tDDKHDX

D1D0

tDDKHAX ,tDDKHCX

Write A0 NOOP

tDDKHME

tDDKHMP

MECC[x]

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 19

Local Bus

7 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the MPC8309.

7.1 Local Bus DC Electrical Characteristics

The following table provides the DC electrical characteristics for the local bus interface.

7.2 Local Bus AC Electrical Specifications

The following table describes the general timing parameters of the local bus interface of the MPC8309.

Table 17. Local Bus DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage VIH 2OV

DD +0.3 V

Low-level input voltage VIL –0.3 0.8 V

High-level output voltage, IOH = –100 AV

OH OVDD –0.2 — V

Low-level output voltage, IOL =100AV

OL —0.2V

Input current IIN —±5A

Table 18. Local Bus General Timing Parameters

Parameter Symbol1Min Max Unit Note

Local bus cycle time tLBK 15 — ns 2

Input setup to local bus clock (LCLKn)t

LBIVKH 7 — ns 3, 4

Input hold from local bus clock (LCLKn)t

LBIXKH 1.0 — ns 3, 4

LALE output fall to LAD output transition (LATCH hold time) tLBOTOT 1.5 — ns

LALE output rise to LCLK negative edge tLALEHOV —3ns—

LALE output fall to LCLK negative edge tLALETOT -1.5 — ns —

Local bus clock (LCLKn) to output valid tLBKHOV —3ns3

Local bus clock (LCLKn) to output high impedance for LAD/LDP tLBKHOZ —4ns5

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case

for clock one(1).

2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of

LCLK0 (for all other inputs).

3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 OVDD of the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

20 Freescale Semiconductor

Local Bus

The following figure provides the AC test load for the local bus.

Figure 7. Local Bus AC Test Load

The following figures show the local bus signals. These figures has been given indicate timing parameters

only and do not reflect actual functional operation of interface.

Figure 8. Local Bus Signals

Output Z0 = 50 OVDD/2

RL = 50 

Output Signals:

LBCTL/LBCKE/LOE

tLBKHOV

LCLK[n]

Input Signals:

LAD[0:15]

Output Signals:

LAD[0:15]

tLBIXKH

tLBIVKH

tLBKHOZ

LALE

Input Signal:

LGTA

tLBIXKH

tLBIVKH

tLBIXKH

tLBOTOT

tLALEHOV tLALETOT

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 21

Local Bus

Figure 9. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2

LCLK

UPM Mode Input Signal:

LUPWAIT

tLBIXKH

tLBIVKH

tLBIXKH

tLBKHOZ

Input Signals:

LAD[0:15]/LDP[0:3]

UPM Mode Output Signals:

LCS[0:3]/LBS[0:1]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:3]/LWE

tLBKHOV

tLBKHOZ

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

22 Freescale Semiconductor

Ethernet and MII Management

Figure 10. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4

8 Ethernet and MII Management

This section provides the AC and DC electrical characteristics for Ethernet interfaces.

8.1 Ethernet Controller (10/100 Mbps)—MII/RMII Electrical

Characteristics

The electrical characteristics specified here apply to all MII (media independent interface) and RMII

(reduced media independent interface), except MDIO (management data input/output) and MDC

(management data clock). The MII and RMII are defined for 3.3 V. The electrical characteristics for MDIO

and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.”

8.1.1 DC Electrical Characteristics

All MII and RMII drivers and receivers comply with the DC parametric attributes specified in The

following table.

LCLK

UPM Mode Input Signal:

LUPWAIT

tLBIXKH

tLBIVKH

tLBIXKH

tLBKHOZ

UPM Mode Output Signals:

LCS[0:3]/LBS[0:1]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:3]/LWE

tLBKHOV

tLBKHOZ

Input Signals:

LAD[0:15]

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 23

Ethernet and MII Management

8.2 MII and RMII AC Timing Specifications

The AC timing specifications for MII and RMII are presented in this section.

8.2.1 MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.1.1 MII Transmit AC Timing Specifications

The following table provides the MII transmit AC timing specifications.

Table 19. MII and RMII DC Electrical Characteristics

Parameter Symbol Conditions Min Max Unit

Supply voltage 3.3 V OVDD —33.6V

Output high voltage VOH IOH = –4.0 mA OVDD =Min 2.40 OV

DD +0.3 V

Output low voltage VOL IOL = 4.0 mA OVDD = Min GND 0.50 V

Input high voltage VIH ——2.0OV

DD +0.3 V

Input low voltage VIL — — –0.3 0.90 V

Input current IIN 0 V VIN OVDD —±5A

Table 20. MII Transmit AC Timing Specifications

At recommended operating conditions with OVDD of 3.3 V ± 300mV.

Parameter/Condition Symbol1Min Typical Max Unit

TX_CLK clock period 10 Mbps tMTX —400—ns

TX_CLK clock period 100 Mbps tMTX —40—ns

TX_CLK duty cycle tMTXH/tMTX 35 — 65 %

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 1 5 15 ns

TX_CLK data clock rise VIL(max) to VIH(min) tMTXR 1.0 — 4.0 ns

TX_CLK data clock fall VIH(min) to VIL(max) tMTXF 1.0 — 4.0 ns

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit

timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

24 Freescale Semiconductor

Ethernet and MII Management

The following figure provides the AC test load.

Figure 11. AC Test Load

The following figure shows the MII transmit AC timing diagram.

Figure 12. MII Transmit AC Timing Diagram

8.2.1.2 MII Receive AC Timing Specifications

The following table provides the MII receive AC timing specifications.

Table 21. MII Receive AC Timing Specifications

At recommended operating conditions with OVDD of 3.3 V ± 300mV.

Parameter/Condition Symbol1Min Typical Max Unit

RX_CLK clock period 10 Mbps tMRX —400—ns

RX_CLK clock period 100 Mbps tMRX —40—ns

RX_CLK duty cycle tMRXH/tMRX 35 — 65 %

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns

RX_CLK clock rise VIL(max) to VIH(min) tMRXR 1.0 — 4.0 ns

RX_CLK clock fall time VIH(min) to VIL(max) tMRXF 1.0 — 4.0 ns

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)

going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input

signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general,

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For

example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used

with the appropriate letter: R (rise) or F (fall).

Output Z0 = 50 OVDD/2

RL = 50 

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 25

Ethernet and MII Management

The following figure shows the MII receive AC timing diagram.

Figure 13. MII Receive AC Timing Diagram

8.2.2 RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.2.1 RMII Transmit AC Timing Specifications

The following table provides the RMII transmit AC timing specifications.

The following figure provides the AC test load.

Figure 14. AC Test Load

Table 22. RMII Transmit AC Ti ming Specifications

At recommended operating conditions with OVDD of 3.3 V ± 300mV.

Parameter/Condition Symbol1Min Typical Max Unit

REF_CLK clock tRMX —20—ns

REF_CLK duty cycle tRMXH/tRMX 35 — 65 %

REF_CLK to RMII data TXD[1:0], TX_EN delay tRMTKHDX 2 — 13 ns

REF_CLK data clock rise VIL(min) to VIH(max) tRMXR 1.0 — 4.0 ns

REF_CLK data clock fall VIH(max) to VIL(min) tRMXF 1.0 — 4.0 ns

Note:

1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII

transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

RX_CLK

RXD[3:0]

tMRDXKH

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

Output Z0 = 50 OVDD/2

RL = 50 

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

26 Freescale Semiconductor

Ethernet and MII Management

The following figure shows the RMII transmit AC timing diagram.

Figure 15. RMII Transmit AC Timing Diagram

8.2.2.2 RMII Receive AC Timing Specifications

The following table provides the RMII receive AC timing specifications.

Table 23. RMII Receive AC Timing Specifications

At recommended operating conditions with OVDD of 3.3 V ± 300mV.

Parameter/Condition Symbol1Min Typical Max Unit

REF_CLK clock period tRMX —20—ns

REF_CLK duty cycle tRMXH/tRMX 35 — 65 %

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK tRMRDVKH 4.0 — — ns

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK tRMRDXKH 2.0 — — ns

REF_CLK clock rise VIL(min) to VIH(max) tRMXR 1.0 — 4.0 ns

REF_CLK clock fall time VIH(max) to VIL(min) tRMXF 1.0 — 4.0 ns

Note:

1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII

receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock

reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect

to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold

time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a

particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

REF_CLK

TXD[1:0]

tRMTKHDX

tRMX

tRMXH

tRMXR

tRMXF

TX_EN

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 27

Ethernet and MII Management

The following figure shows the RMII receive AC timing diagram.

Figure 16. RMII Receive AC Timing Diagram

8.3 Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock). The electrical characteristics for

MII, and RMII are specified in Section 8.1, “Ethernet Controller (10/100 Mbps)—MII/RMII Electrical

Characteristics.”

8.3.1 MII Management DC Electrical Characteristics

MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for

MDIO and MDC are provided in the following table.

8.3.2 MII Management AC Electrical Specifications

The following table provides the MII management AC timing specifications.

Table 24. MII Management DC Electrical Characteristics When Powered at 3.3 V

Parameter Symbol Conditions Min Max Unit

Supply voltage (3.3 V) OVDD —33.6V

Output high voltage VOH IOH = –1.0 mA OVDD =Min 2.40 OV

DD + 0.3 V

Output low voltage VOL IOL = 1.0 mA OVDD = Min GND 0.50 V

Input high voltage VIH —2.00—V

Input low voltage VIL — — 0.80 V

Input current IIN 0 V VIN OVDD —±5A

Table 25. MII Management AC Timing Specifications

At recommended operating conditions with OVDD is 3.3 V ± 300mV.

Parameter/Condition Symbol1Min Typical Max Unit Note

MDC frequency fMDC —2.5—MHz—

MDC period tMDC —400—ns—

MDC clock pulse width high tMDCH 32 — — ns —

REF_CLK

RXD[1:0]

tRMRDXKH

tRMX

tRMXH

tRMXR

tRMXF

CRS_DV

RX_ER

tRMRDVKH

Valid Data

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

28 Freescale Semiconductor

Ethernet and MII Management

The following figure shows the MII management AC timing diagram.

Figure 17. MII Management Interface Timing Diagram

8.3.3 IEEE 1588DC Specifications

The IEEE 1588 DC timing specifications are given in the following table.

MDC to MDIO delay tMDKHDX 10 — 70 ns —

MDIO to MDC setup time tMDDVKH 8.5 — — ns —

MDIO to MDC hold time tMDDXKH 0——ns—

MDC rise time tMDCR — — 10 ns —

MDC fall time tMDHF — — 10 ns —

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes

management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data

hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the

valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

Table 26. IEEE 1588 DC Electrical Characteristics

Characteristic Symbol Condition Min Max unit

Output high voltage VOH IOH = -8.0 mA 2.4 — V

Output low voltage VOL IOL = 8.0 mA — 0.5 V

Output low voltage VOL IOL = 3.2mA — 0.4 V

Table 25. MII Management AC Timing Specifications (continued)

At recommended operating conditions with OVDD is 3.3 V ± 300mV.

Parameter/Condition Symbol1Min Typical Max Unit Note

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

MPC8309 PowerQUICC II Pro Integrated Co mmunications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor 29

Ethernet and MII Management

8.3.4 IEEE 1588 AC Specifications

The IEEE 1588 AC timing specifications are given in the following table.

Input high voltage VIH — 2.0 OVDD + 0.3 V

Input low voltage VIL — - 0.3 0.8 V

Input current IIN 0V ≤ VIN ≤ OVDD —± 5μA

Table 27. IEEE 1588 AC Timing Specifications

At recommended operating conditions with OVDD of 3.3 V ± 300mV.

Parameter/Condition Symbol Min Typ Max Unit Note

QE_1588_CLK clock period tT1588CLK 2.5 — TRX_CLK 9ns 1, 3

QE_1588_CLK duty cycle tT1588CLKH/tT1588CLK 40 50 60 % —

QE_1588_CLK peak-to-peak jitter tT1588CLKINJ ——250ps—

Rise time QE_1588_CLK

(20%–80%)

tT1588CLKINR 1.0 — 2.0 ns —

Fall time QE_1588_CLK

(80%–20%)

tT1588CLKINF 1.0 — 2.0 ns —

QE_1588_CLK_OUT clock period tT1588CLKOUT 2tT1588CLK ——ns—

QE_1588_CLK_OUT duty cycle tT1588CLKOTH

/tT1588CLKOUT

30 50 70 % —

QE_1588_PULSE_OUT tT1588OV 0.5 — 3.0 ns —

QE_1588_TRIG_IN pulse width tT1588TRIGH 2tT1588CLK_MAX ——ns2

Notes:

1.TRX_CLK is the max clock period of QUICC engine receiving clock selected by TMR_CTRL[CKSEL]. See the MPC8309

PowerQUICC II Pro Integrated Communications Processor Reference Manual, for a description of TMR_CTRL registers.

2. It needs to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8309 PowerQUICC

II Pro Integrated Communicat i ons Processor Reference Manual, for a description of TMR_CTRL registers.

3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For

example, for 10/100 Mbps modes, the maximum value of tT1588CLK is 3600 and 280ns, respectively.

Table 26. IEEE 1588 DC Electrical Characteristics

Characteristic Symbol Condition Min Max unit

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30 Freescale Semiconductor

TDM/SI

The following figure provides the data and command output timing diagram.

Figure 18. IEEE1588 Output AC Timing

The following figure provides the data and command input timing diagram.

Figure 19. IEEE1588 Input AC Timing

9TDM/SI

This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial

interface of the MPC8309.

9.1 TDM/SI DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8309 TDM/SI.

Table 28. TDM/SI DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Output high voltage VOH IOH = –2.0 mA 2.4 — V

Output low voltage VOL IOL = 3.2 mA — 0.5 V

Input high voltage VIH —2.0OV

DD +0.3 V

Input low voltage VIL —–0.30.8V

Input current IIN 0 V VIN OVDD —±5A

TSEC_1588_CLK_OUT

TSEC_1588_PULSE_OUT

TSEC_1588_TRIG_OUT

tT1588OV

tT1588CLKOUT

tT1588CLKOUTH

Note: The output delay is count starting rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is

count starting falling edge.

TSEC_1588_CLK

TSEC_1588_TRIG_IN

tT1588TRIGH

tT1588CLK

tT1588CLKH

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Freescale Semiconductor 31

HDLC

9.2 TDM/SI AC Timing Specifications

The following table provides the TDM/SI input and output AC timing specifications.

The following figure provides the AC test load for the TDM/SI.

Figure 20. TDM/SI AC Test Load

The following figure represents the AC timing from Table 29. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 21. TDM/SI AC Timing (External Clock) Diagram

10 HDLC

This section describes the DC and AC electrical specifications for the high level data link control (HDLC),

of the MPC8309.

Tabl e 29. TDM/SI AC Timing Specifications1

Characteristic Symbol2Min Max Unit

TDM/SI outputs—External clock delay tSEKHOV 214ns

TDM/SI outputs—External clock High Impedance tSEKHOX 210ns

TDM/SI inputs—External clock input setup time tSEIVKH 5—ns

TDM/SI inputs—External clock input hold time tSEIXKH 2—ns

Notes:

1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI

outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O)

are invalid (X).

Output Z0 = 50 OVDD/2

RL = 50 

TDM/SICLK (Input)

tSEIXKH

tSEIVKH

tSEKHOV

Input Signals:

TDM/SI

(See Note)

Output Signals:

TDM/SI

(See Note)

Note: The clock edge is selectable on TDM/SI.

tSEKHOX

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32 Freescale Semiconductor

HDLC

10.1 HDLC DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8309 HDLC protocol.

10.2 HDLC AC Timing Specifications

The following table provides the input and output AC timing specifications for HDLC protocol.

The following figure provides the AC test load.

Figure 22. AC Test Load

Table 30. HDLC DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Output high voltage VOH IOH = –2.0 mA 2.4 — V

Output low voltage VOL IOL = 3.2 mA — 0.5 V

Input high voltage VIH —2.0OV

DD +0.3 V

Input low voltage VIL —–0.30.8V

Input current IIN 0 V  VIN OVDD — ±5 A

Table 31. HDLC AC Timing Specifications1

Characteristic Symbol2Min Max Unit

Outputs—Internal clock delay tHIKHOV 09ns

Outputs—External clock delay tHEKHOV 1 12 ns

Outputs—Internal clock high impedance tHIKHOX 05.5ns

Outputs—External clock high impedance tHEKHOX 18ns

Inputs—Internal clock input setup time tHIIVKH 9—ns

Inputs—External clock input setup time tHEIVKH 4—ns

Inputs—Internal clock input hold time tHIIXKH 0—ns

Inputs—External clock input hold time tHEIXKH 1—ns

Notes:

1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs

internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

Output Z0 = 50 OVDD/2

RL = 50 

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Freescale Semiconductor 33

PCI

Figure 23 and Figure 24 represent the AC timing from Table 31. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

The following figure shows the timing with external clock.

Figure 23. AC Timing (External Clock) Diagram

The following figure shows the timing with internal clock.

Figure 24. AC Timing (Internal Clock) Diagram

11 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the MPC8309.

11.1 PCI DC Electrical Characteristics

Table 32 provides the DC electrical characteristics for the PCI interface of the MPC8309.

Table 32. PCI DC Electrical Characteristics1,2

Parameter Symbol Test Condition Min Max Unit

High-level input voltage VIH VOUT VOH (min) or 2 OVDD + 0.3 V

Low-level input voltage VIL VOUT  VOL (max) –0.3 0.8 V

High-level output voltage VOH OVDD = min,

IOH = –100 A

OVDD – 0.2 — V

Serial CLK (Input)

tHEIXKH

tHEIVKH

tHEKHOV

Input Signals:

(See Note)

Output Signals:

(See Note)

Note: The clock edge is selectable.

tHEKHOX

Serial CLK (Output)

tHIIXKH

tHIKHOV

Input Signals:

(See Note)

Output Signals:

(See Note)

tHIIVKH

tHIKHOX

Note: The clock edge is selectable.

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34 Freescale Semiconductor

PCI

11.2 PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus of the MPC8309. Note that the

PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8309 is

configured as a host or agent device. Table 33 shows the PCI AC timing specifications at 66 MHz.

Table 34 shows the PCI AC timing specifications at 33 MHz.

Low-level output voltage VOL OVDD = min,

IOL = 100 A

—0.2V

Input current IIN 0 V VIN OVDD — ±5 A

Notes:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.

2. Ranges listed do not meet the full range of the DC specifications of the PCI 2.3 Local Bus Specifications.

Table 33. PCI AC Timing Specifications at 66 MHz

Parameter Symbol1Min Max Unit Notes

Clock to output valid tPCKHOV —6.0ns2

Output hold from clock tPCKHOX 1—ns2

Clock to output high impedance tPCKHOZ —14ns2, 3

Input setup to clock tPCIVKH 3.0 — ns 2, 4

Input hold from clock tPCIXKH 0 — ns 2, 4

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing

(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference

(K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset

(R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

Table 34. PCI AC Timing Specifications at 33 MHz

Parameter Symbol1Min Max Unit Notes

Clock to output valid tPCKHOV —11ns2

Output hold from clock tPCKHOX 2—ns2

Clock to output high impedance tPCKHOZ —14ns2, 3

Table 32. PCI DC Electrical Characteristics1,2

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Freescale Semiconductor 35

PCI

Figure 25 provides the AC test load for PCI.

Figure 25. PCI AC Test Load

Figure 26 shows the PCI input AC timing conditions.

Figure 26. PCI Input AC Timing Measurement Conditions

Figure 27 shows the PCI output AC timing conditions.

Figure 27. PCI Output AC Timing Measurement Condition