1
®
DAC7744
16-Bit, Quad Voltage Output
DIGITAL-TO-ANALOG CONVERTER
®
DAC7744
DESCRIPTION
The DAC7744 is a 16-bit, quad voltage output digital-
to-analog converter with guaranteed 16-bit monotonic
performance over the specified temperature range. It
accepts 16-bit parallel input data, has double-buffered
DAC input logic (allowing simultaneous update of all
DACs), and provides a readback mode of the internal
input registers. Programmable asynchronous reset
clears all registers to a mid-scale code of 8000H or to
a zero-scale of 0000H. The DAC7744 operates from
either a single +15V supply or from a +15V, –15V,
and +5V supply.
Low power and small size per DAC make the DAC7744
ideal for automatic test equipment, DAC-per-pin pro-
grammers, data acquisition systems, and closed-loop
servo-control. The DAC7744 is available in a 48-
lead SSOP package, and offers guaranteed specifica-
tions over the –40°C to +85°C temperature range.
FEATURES
● LOW POWER: 200mW
● UNIPOLAR OR BIPOLAR OPERATION
● SINGLE-SUPPLY OUTPUT RANGE: +10V
● DUAL SUPPLY OUTPUT RANGE: ±10V
● SETTLING TIME: 10µs to 0.003%
● 16-BIT MONOTONICITY: –40°C to +85°C
● PROGRAMMABLE RESET TO MID-SCALE
OR ZERO-SCALE
● DATA READBACK
● DOUBLE-BUFFERED DATA INPUTS
APPLICATIONS
● PROCESS CONTROL
● ATE PIN ELECTRONICS
● CLOSED-LOOP SERVO-CONTROL
● MOTOR CONTROL
● DATA ACQUISITION SYSTEMS
● DAC-PER-PIN PROGRAMMERS
© 1999 Burr-Brown Corporation PDS-1534A Printed in U.S.A. November, 1999
DAC7744
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
For most current data sheet and other product
information, visit www.burr-brown.com
DAC A
DAC
Register A
Input
Register A
DAC7744
I/O
Buffer
Control
Logic
DAC B
DAC
Register B
Input
Register B
DAC C
DAC
Register C
Input
Register C
DAC D
DAC
Register D
Input
Register D
V
REF
L AB V
REF
H AB V
REF
H
AB Sense
V
REF
L
AB Sense
V
OUT
D
V
OUT
C
V
OUT
B
V
OUT
A
V
OUT
B
Sense
V
REF
L CD V
REF
H CD
RST LOADDACs
A1
A0
CS
R/W
DATA I/O 16
RSTSEL
AGND DGND
V
OUT
C
Sense
V
OUT
D
Sense
V
OUT
A
Sense
V
CC
V
SS
V
DD
V
REF
L
CD Sense V
REF
H
CD Sense
SBAS120
2
®
DAC7744
DAC7744E DAC7744EB DAC7744EC
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
ACCURACY
Linearity Error T = 25°C±3✻±2 LSB
TMIN to TMAX ±4✻±3 LSB
Linearity Match ±4✻±2 LSB
Differential Linearity Error T = 25°C±3±2±1 LSB
TMIN to TMAX ±3±2±1 LSB
Monotonicity, TMIN to TMAX 14 15 16 Bits
Bipolar Zero Error
T = 25°C±0.01 ±0.025 ✻✻% of FSR
Bipolar Zero Error, T
MIN
to T
MAX
±0.05 ✻✻% of FSR
Full-Scale Error T = 25°C±0.025 ✻✻% of FSR
Full-Scale Error, TMIN to TMAX ±0.05 ✻✻% of FSR
Bipolar Zero Matching Channel-to-Channel ±0.024 ✻✻% of FSR
Matching
Full-Scale Matching Channel-to-Channel ±0.024 ✻✻% of FSR
Matching
Power Supply Rejection Ratio (PSRR)
At Full Scale 25 ✻✻ppm/V
ANALOG OUTPUT
Voltage Output VREFLV
REFH✻✻✻✻V
Output Current ±5✻✻ mA
Maximum Load Capacitance 500 ✻✻pF
Short-Circuit Current ±20 ✻✻mA
Short-Circuit Duration To VSS, VDD or GND Indefinite ✻✻
REFERENCE INPUT
Ref High Input Voltage Range
VREFL + 1.25
+10 ✻✻✻✻V
Ref Low Input Voltage Range –10
VREFH – 1.25
✻✻✻✻V
Ref High Input Current –0.3 2.6 ✻✻mA
Ref Low Input Current –3.2 –0.3 ✻✻mA
DYNAMIC PERFORMANCE
Settling Time To ±0.003%, 20V 9 11 ✻✻ ✻✻ µs
Output Step
Channel-to-Channel Crosstalk See Figure 5 0.5 ✻✻LSB
Digital Feedthrough 2 ✻✻nV-s
Output Noise Voltage f = 10kHz 60 ✻✻nV/√Hz
DIGITAL INPUT
VIH 0.7 • VDD VDD ✻✻ V
VIL 0 0.3 • VDD ✻V
IIH ±10 ✻µA
IIL ±10 ✻µA
DIGITAL OUTPUT
VOH IOH = –0.8mA 3.6 4.5 ✻✻ ✻✻ V
VOL IOL = 1.6mA 0.3 0.4 ✻✻ ✻✻ V
POWER SUPPLY
VDD +4.75 +5.0 +5.25 ✻✻✻✻✻✻ V
VCC +14.25 +15.0 +15.75 ✻✻✻✻✻✻ V
VSS –14.25 –15.0 –15.75 ✻✻✻✻✻✻ V
IDD 50 ✻✻µA
ICC 6✻✻mA
ISS –5 ✻✻mA
Power 170 200 ✻✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻✻✻°C
✻ Specifications same as grade to the left.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
SPECIFICATIONS (Dual Supply)
At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, and VREFL = –10V, unless otherwise noted.
3
®
DAC7744
DAC7744E DAC7744EB DAC7744EC
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
ACCURACY
Linearity Error(1) T = 25°C±3✻±2 LSB
TMIN to TMAX ±4✻±3 LSB
Linearity Match ±4✻±2 LSB
Differential Linearity Error T = 25°C±3±2±1 LSB
TMIN to TMAX ±3±2±1 LSB
Monotonicity, TMIN to TMAX 14 15 16 Bits
Unipolar Zero T = 25°C±0.01 ±0.025 ✻✻% of FSR
Unipolar Zero Error,
TMIN to TMAX
±0.05 ✻✻% of FSR
Full-Scale Error T = 25°C±0.025 ✻✻% of FSR
Full-Scale Error,
TMIN to TMAX
±0.05 ✻✻% of FSR
Unipolar Zero Matching Channel-to-Channel ±0.024 ✻✻% of FSR
Matching
Full-Scale Matching Channel-to-Channel ±0.024 ✻✻% of FSR
Matching
Power Supply Rejection Ratio (PSRR)
At Full Scale 25 ✻✻ppm/V
ANALOG OUTPUT
Voltage Output VREFL = 0V, VSS = 0V 0 VREFH✻✻✻✻V
R = 10kΩ
Output Current ±5✻✻ mA
Maximum Load Capacitance 500 ✻✻pF
Short-Circuit Current ±20 ✻✻mA
Short-Circuit Duration To VSS, VCC or GND Indefinite ✻✻
REFERENCE INPUT
Ref High Input Voltage Range
VREFL + 1.25
+10 ✻✻✻✻V
Ref Low Input Voltage Range 0
VREFH – 1.25
✻✻✻✻V
Ref High Input Current –0.3 1.0 ✻✻mA
Ref Low Input Current –1.5 –0.3 ✻✻mA
DYNAMIC PERFORMANCE
Settling Time To ±0.003%, 10V 8 10 ✻✻ ✻✻ µs
Output Step
Channel-to-Channel Crosstalk See Figure 6 0.5 ✻✻LSB
Digital Feedthrough 2 ✻✻nV-s
Output Noise Voltage f = 10kHz 60 ✻✻nV/√Hz
DIGITAL INPUT
VIH 0.7 • VDD VDD ✻✻ V
VIL 0 0.3 • VDD ✻V
IIH ±10 ✻µA
IIL ±10 ✻µA
DIGITAL OUTPUT
VOH IOH = –0.8mA 3.6 4.5 ✻✻ ✻✻ V
VOL IOL = 1.6mA 0.3 0.4 ✻✻ ✻✻ V
POWER SUPPLY
VDD +4.75 +5.0 +5.25 ✻✻✻✻✻✻ V
VCC +14.25 +15.0 +15.75 ✻✻✻✻✻✻ V
VSS 0✻✻V
IDD 50 ✻✻µA
ICC 3.5 ✻✻mA
Power 50 70 ✻✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻✻✻°C
✻ Specifications same as grade to the left.
NOTE: (1) If VSS = 0V, the specification applies at code 0021H and above, due to possible negative zero scale error.
SPECIFICATIONS (Single Supply)
At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = GND, VREFH = +10V, and VREFL = +50mV, unless otherwise noted.
4
®
DAC7744
ABSOLUTE MAXIMUM RATINGS(1)
VCC to VSS ........................................................................... –0.3V to +32V
VCC to AGND ...................................................................... –0.3V to +16V
VSS to AGND ...................................................................... +0.3V to –16V
AGND to DGND................................................................. –0.3V to +0.3V
VREFH to AGND .....................................................................–9V to +11V
VREFL to AGND...................................................................... –11V to +9V
VDD to GND...........................................................................–0.3V to +6V
VREFH to VREFL ........................................................................ –1V to 22V
Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND................................. –0.3V to VDD + 0.3V
Maximum Junction Temperature................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
LINEARITY DIFFERENTIAL PACKAGE SPECIFICATION
ERROR NONLINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT
PRODUCT (LSB) (LSB) PACKAGE NUMBER RANGE NUMBER(1) MEDIA
DAC7744E ±4±3 48-Lead SSOP 333 –40°C to +85°C DAC7744E Rails
"" """ "DAC7744E/1K Tape and Reel
DAC7744EB ±4±2 48-Lead SSOP 333 –40°C to +85°C DAC7744EB Rails
"" """ "DAC7744EB/1K Tape and Reel
DAC7744EC ±3±1 48-Lead SSOP 333 –40°C to +85°C DAC7744EC Rails
"" """ "DAC7744EC/1K Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC7744E/1K” will get a single 1000-piece Tape and Reel.
RefH V
OUT
Sense
V
CC
V
SS
V
DD
DGND
4
V
CC
AGND
V
SS
V
DD
DGND
V
OUT
RefH Sense
RefL Sense
RefL
1 of 2 1 of 4
Typ of Each
Logic Input Pin
Typ of Each
I/O Pin
ESD PROTECTION CIRCUITS
5
®
DAC7744
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1 DB15 Data Bit 15, MSB
2 DB14 Data Bit 14
3 DB13 Data Bit 13
4 DB12 Data Bit 12
5 DB11 Data Bit 11
6 DB10 Data Bit 10
7 DB9 Data Bit 9
8 DB8 Data Bit 8
9 DB7 Data Bit 7
10 DB6 Data Bit 6
11 DB5 Data Bit 5
12 DB4 Data Bit 4
13 DB3 Data Bit 3
14 DB2 Data Bit 2
15 DB1 Data Bit 1
16 DB0 Data Bit 0, LSB
17 RSTSEL Reset Select. Determines the action of RST. If
HIGH, a RST command will set the DAC regis-
ters to mid-scale. If LOW, a RST command will
set the DAC registers to zero.
18 RST Reset, Edge-Triggered. Depending on the state
of RSTSEL, the DAC Input and Output registers
are set to either mid-scale or zero.
19 LOADDACs DAC Output Registers Load Control. Rising edge
triggered.
20 R/W Enabled by the CS, controls data read and write
from the input register.
21 A1 Enabled by the CS, in combination with A0
selects the Individual DAC Input Registers.
22 A0 Enabled by the CS, in combination with A1
selects the individual DAC input registers.
23 CS Chip Select, Active LOW.
24 DGND Digital Ground
25 VDD Positive Power Supply
26 VCC Positive Power Supply
27 AGND Analog Ground
28 VSS Negative Power Supply
29 VOUTD DAC D Voltage Output
30 VOUTD Sense DAC D’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
31 VREFL CD Sense DAC C and D Reference Low Sense Input
32 VREFL CD DAC C and D Reference Low Input
33 VREFH CD DAC C and D Reference High Input
34 VREFH CD Sense DAC C and D Reference High Sense Input
35 VOUTC DAC C Voltage Output
36 VOUTC Sense DAC C’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
37 VOUTB DAC B Voltage Output
38 VOUTB Sense DAC B’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
39 VREFH AB Sense DAC A and B Reference High Sense Input
40 VREFH AB DAC A and B Reference High Input
41 VREFL AB DAC A and B Reference Low Input
42 VREFL AB Sense DAC A and B Reference Low Sense Input
43 VOUTA DAC A Voltage Input
44 VOUTA Sense DAC A’s Output Amplifier Inverting Input. Used
to close the feedback loop at the load.
45 NC No Connection
46 NC No Connection
47 NC No Connection
48 NC No Connection
Top View SSOP
PIN CONFIGURATION
DB15 (MSB)
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
RSTSEL
RST
LOADDACs
R/W
A1
A0
CS
DGND
NC
NC
NC
NC
V
OUT
A Sense
V
OUT
A
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
V
OUT
C Sense
V
OUT
C
V
REF
H CD Sense
V
REF
H CD
V
REF
L CD
V
REF
L CD Sense
V
OUT
D Sense
V
OUT
D
V
SS
AGND
V
CC
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7744
6
®
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
+25°C
+85°C
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
7
®
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
+85°C (cont.)
–40°C
8
®
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
Temperature (°C)
–40 –30 –10 0–20 10 20 40 5030 70 80 9060
ZERO-SCALE ERROR vs TEMPERATURE
Zero-Scale Error (mV)
DAC A
DAC D
DAC B
DAC C
Code (0040
H
)Code (0021
H
)
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
Temperature (°C)
–40 –30 –10 0–20 10 20 40 5030 70 80 9060
FULL-SCALE ERROR vs TEMPERATURE
Positive Full-Scale Error (mV)
DAC A
DAC D
DAC B
DAC C
Code (FFFF
H
)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
V
REF
Current (mA)V
REF
Current (mA)
CURRENT vs CODE
All DACS Sent to Indicated Code
(DAC C and D)
V
REFH
V
REFL
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Digital Input Code
0 2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
I
CC
(mA)
No Load
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
V
REF
Current (mA)V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC A and B)
V
REFH
V
REFL
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
Temperature (°C)
–40 –30 –10 0–20 10 20 40 5030 70 80 9060
POWER SUPPLY CURRENT vs TEMPERATURE
Quiescent Current (mA)
I
CC
I
DD
Data = FFFF
H
(all DACs)
No Load
9
®
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
BROADBAND NOISE
Time (100µs/div)
Noise Voltage (20µV/div)
BW = 10kHz
Code = 8000H
+5V
LDAC
0
Time (2µs/div)
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +10V)
Output Voltage
Small-Signal Settling Time: 3LSB/div
Large-Signal Settling Time: 5V/div
+5V
LDAC
0
Time (2µs/div)
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to 0V)
Output Voltage
Small-Signal Settling Time: 3LSB/div
Large-Signal Settling Time: 5V/div
120
100
80
60
40
20
0
Frequency (Hz)
100 1k 10k 100k 1M
OUTPUT NOISE VOLTAGE vs FREQUENCY
Noise (nV/√Hz)
+5V
LDAC
0
Time (1µs/div)
OUTPUT VOLTAGE
MIDSCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
7FFF
H
to 8000
H
+5V
LDAC
0
Time (1µs/div)
Output Voltage (50mV/div)
8000
H
to 7FFF
H
OUTPUT VOLTAGE
MIDSCALE GLITCH PERFORMANCE
10
®
DAC7744
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
Frequency (Hz)
100 1k 10k 100k 1M
POWER SUPPLY REJECTION RATIO vs FREQUENCY
PSRR (dB)
+15V
+5V
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified.
20
15
10
5
0
–5
–10
–15
–20
Input Code
0000
H
2000
H
4000
H
6000
H
8000
H
A000
H
0000
H
E000
H
FFFF
H
SINGLE-SUPPLY CURRENT LIMIT
vs INPUT CODE
I
OUT
(mA)
Short to Ground
Short to V
CC
16
14
12
10
8
6
4
2
0
R
LOAD
(kΩ)
0.01 0.1 1 10 100
OUTPUT VOLTAGE vs R
LOAD
V
OUT
(V)
Source
Sink
12
10
8
6
4
2
0
LOGIC SUPPLY CURRENT
vs LOGIC INPUT LEVEL FOR DATA BITS
Logic Supply Current (mA)
Logic Input Level for Data Bits (V)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
+5V
CS
0
Time (500ns/div)
DIGITAL-TO-ANALOG OUTPUT GLITCH
Output Voltage (50mV/div)
2LSB/div
11
®
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = –15V
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
+25°C
+85°C
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
12
®
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
+85°C (cont.)
–40°C
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
13
®
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
2.0
1.5
1.0
0.5
0
-0.5
–1.0
–1.5
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
V
REF
Current (mA)V
REF
Current (mA)
CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC A and B)
V
REFH
V
REFL
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
V
REF
Current (mA)V
REF
Current (mA)
CURRENT vs CODE
All DACs Sent to Indicated Code
(DAC C and D)
V
REFH
V
REFL
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
Temperature (°C)
–40 –20 100020406080
BIPOLAR ZERO SCALE ERROR vs TEMPERATURE
(Code 8000
H
)
Bipolar Zero Scale Error (mV)
DAC B DAC D
DAC A
DAC C
2
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Temperature (°C)
–40 –10 0–30 –20 9010 20 30 40 50 60 70 80
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFF
H
)
Positive Full-Scale Error (mV)
DAC B
DAC A
DAC C
DAC D
2
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
Temperature (°C)
–40 –10 0–30 –20 9010 20 30 40 50 60 70 80
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
(Code 0000
H
)
Negative Full-Scale Error (mV)
DAC B
DAC A
DAC C
DAC D
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
Temperature (°C)
–40 –10 0–30 –20 9010 20 30 40 50 60 70 80
POWER SUPPLY CURRENT vs TEMPERTURE
Quiescent Current (mA)
I
SS
I
CC
I
DD
Data = FFFF
H
(all DACs)
No Load
14
®
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Frequency (Hz)
100 1k 10k 100k 1M
POWER SUPPLY REJECTION RATIO vs FREQUENCY
PSRR (dB)
–15V +15V
+5V
15
10
5
0
–5
–10
–15
R
LOAD
(kΩ)
0.01 0.1 1 10 100
OUTPUT VOLTAGE vs R
LOAD
V
OUT
(V)
Sink
Source
Time (2µs/div)
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to –10V)
Output Voltage
Large-Signal Settling Time: 5V/div
Small-Signal Settling Time: 3LSB/div
+5V
LDAC
0
Time (2µs/div)
OUTPUT VOLTAGE vs SETTLING TIME
(–10V to +10V)
Output Voltage
Large-Signal Settling Time: 5V/div
Small-Signal Settling Time: 3LSB/div
+5V
LDAC
0
20
15
10
5
0
–5
–10
–15
–20
DUAL SUPPLY CURRENT LIMIT vs INPUT CODE
Short to Ground
I
OUT
(mA)
Digital Input Code
0000
H
2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
SUPPLY CURRENT vs CODE
(mA)
Digital Input Code
0000
H
2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
I
CC
I
DD
I
SS
15
®
DAC7744
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified.
Time (1µs/div)
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
7FFFH to 8000H
+5V
LDAC
0Time (1µs/div)
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
8000H to 7FFFH
+5V
LDAC
0
16
®
DAC7744
FIGURE 1. DAC7744 Architecture.
FIGURE 2. Basic Single-Supply Operation of the DAC7744.
THEORY OF OPERATION
The DAC7744 is a quad voltage output, 16-bit digital-to-
analog converter (DAC). The architecture is an R-2R ladder
configuration with the three MSB’s segmented followed by
an operational amplifier that serves as a buffer. Each DAC
has its own R-2R ladder network, segmented MSBs and
output op amp (see Figure 1). The minimum voltage output
(zero scale) and maximum voltage output (full scale) are set
by the external voltage references (VREFL and VREFH, re-
spectively). The digital input is a 16-bit parallel word and
the DAC input registers offer a readback capability. The
converters can be powered from either a single +15V supply
or a dual ±15V supply. The device offers a reset function
which immediately sets all DAC output voltages and DAC
registers to mid-scale code 8000H or to zero scale, code
0000H. See Figures 2 and 3 for the basic operation of the
DAC7744.
R
2R
2R2R 2R 2R 2R 2R 2R 2R
V
REF
H
V
OUT
V
OUT
Sense
V
REF
H Sense
V
REF
L
V
REF
L Sense
R
F
DB15 (MSB)
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
RSTSEL
RST
LOADDACS
R/W
A1
A0
CS
DGND
NC
NC
NC
NC
V
OUT
A Sense
V
OUT
A
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
V
OUT
C Sense
V
OUT
C
V
REF
H CD Sense
V
REF
H CD
V
REF
L CD
V
REF
L CD Sense
V
OUT
D Sense
V
OUT
D
V
SS
AGND
V
CC
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7744
Reset DACs
Data
Bus
Address
Load DAC Registers
READ/WRITE
Chip Select
NC = No Connection
0V to +10V
0V to +10V
0V to +10V
0V to +10V
+10.000V
+10.000V
+15V
0.1µF1µF
+5V
0.1µF1µF
+
+
17
®
DAC7744
ANALOG OUTPUTS
When VSS = –15V (dual supply operation), the output ampli-
fier can swing to within 4V of the supply rails, guaranteed
over the –40°C to +85°C temperature range. With VSS = 0V
(single-supply operation), and with RLOAD also connected to
ground, the output can swing to ground. Care must also be
taken when measuring the zero-scale error when VSS = 0V.
Since the output voltage cannot swing below ground, the
output voltage may not change for the first few digital input
codes (0000H, 0001H, 0002H, etc.), if the output amplifier has
a negative offset. At the negative limit of –5mV, the first
specified output starts at code 0021H.
Due to the high accuracy of these D/A converters, system
design problems such as grounding and contact resistance
become very important. A 16-bit converter with a 10V full-
scale range has a 1LSB value of 152µV. With a load current
of 1mA, series wiring and connector resistance of only
150mΩ (RW2) will cause a voltage drop of 150µV, as shown
in Figure 4. To understand what this means in terms of a
system layout, the resistivity of a typical 1 ounce copper-clad
printed circuit board is 1/2 mΩ per square. For a 1mA load,
a 20 milli-inch wide printed circuit conductor 6 inches long
will result in a voltage drop of 150µV.
The DAC7744 offers a force and sense output configuration
for the high open-loop gain output amplifiers. This feature
allows the loop around the output amplifier to be closed at
the load, thus ensuring an accurate output voltage, as shown
in Figure 4.
FIGURE 3. Basic Dual-Supply Operation of the DAC7744.
FIGURE 4. Analog Output Closed-Loop Configuration
(1/2 DAC7744). RW represents wiring resis-
tances.
DB15 (MSB)
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
RSTSEL
RST
LOADDACS
R/W
A1
A0
CS
DGND
NC
NC
NC
NC
V
OUT
A Sense
V
OUT
A
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
V
OUT
C Sense
V
OUT
C
V
REF
H CD Sense
V
REF
H CD
V
REF
L CD
V
REF
L CD Sense
V
OUT
D Sense
V
OUT
D
V
SS
AGND
V
CC
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DAC7744
Reset DACs
Data
Bus
Address
Load DAC Registers
READ/WRITE
Chip Select
NC = No Connection
–10V to +10V
–10V
–10V to +10V
–10V to +10V
–10V to +10V
+10V
+10V
–10V
+5V
–15V
0.1µF1µF
+15V
0.1µF1µF
+5V
0.1µF1µF
+
+
+
NC
NC
NC
NC
V
OUT
A Sense
V
OUT
A
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
38
37
DAC7744
R
W1
R
W2
+10V
+V
V
OUT
R
W1
R
W2
V
OUT
R
LOAD
R
LOAD
18
®
DAC7744
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 4V and VCC – 4V, provided that VREFH is at
least 1.25V greater than VREFL. The minimum output of
each DAC is equal to VREFL plus a small offset voltage
(essentially, the offset of the output op amp). The maximum
output is equal to VREFH plus a similar offset voltage. Note
that VSS (the negative power supply) must either be
connected to ground or must be in the range of –14.25V to
–15.75V. The voltage on VSS sets several bias points within
the converter. If VSS is not in one of these two configura-
tions, the bias values may be in error and proper operation
of the device is not guaranteed.
The current into the VREFH input and out of VREFL depends
on the DAC output voltages and can vary from a few
microamps to approximately 2.0mA. The reference input
appears as a varying load to the reference. If the reference
can sink or source the required current, a reference buffer is
not required. The DAC7744 features a reference drive and
sense connection such that the internal errors caused by the
changing reference current and the circuit impedances can be
minimized. Figures 5 through 12 show different reference
configurations and the effect on the linearity and differential
linearity.
The analog supplies (or the analog supplies and the reference
power supplies) have to come up first. If the power supplies
for the reference come up first, then the VCC and VSS
supplies will be “powered from the reference via the ESD
protection diode”, see page 4.
FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual Supply Performance Curves (1/2 DAC7744).
FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV Used for Single-Supply Performance Curves
(1/2 DAC7744).
NC
NC
NC
NC
V
OUT
A Sense
V
OUT
A
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
38
37
DAC7744
+10V
+V
–10V
–V
V
OUT
V
OUT
1000pF
2200pF
+V
OPA2234
100Ω
1000pF 2200pF
100Ω
NC
NC
NC
NC
VOUTA Sense
VOUTA
VREFL AB Sense
VREFL AB
VREFH AB
VREFH AB Sense
VOUTB Sense
VOUTB
48
47
46
45
44
43
42
41
40
39
38
37
DAC7744
99kΩ
2kΩ
+0.050V
+10V
+V
VOUT
VOUT
NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage
drops across the 100Ω resistor and the output stage of the buffer op amp.
1000pF
2200pF
+V
OPA350
OPA227
100Ω
1000pF 2200pF
100Ω
19
®
DAC7744
FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 8.
FIGURE 8. Dual-Supply Buffered Referenced with VREFL = –5V and VREFH = +5V (1/2 DAC7744).
NC
NC
NC
NC
VOUTA Sense
VOUTA
VREFL AB Sense
VREFL AB
VREFH AB
VREFH AB Sense
VOUTB Sense
VOUTB
48
47
46
45
44
43
42
41
40
39
38
37
DAC7744
+5V
–V
+V
–5V
VOUT
VOUT
1000pF
2200pF
+V
OPA2234
100Ω
1000pF 2200pF
100Ω
–V
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0
–0.5
–1.0
LE (LSB)DLE (LSB)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0
–0.5
–1.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0
–0.5
–1.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0
–0.5
–1.0
LE (LSB)DLE (LSB)
20
®
DAC7744
FIGURE 9. Single-Supply Buffered Reference with a Reference Low of 50mV and Reference High of +5V.
FIGURE 10. Integral Linearity and Differential Linearity Error Curves for Figure 9.
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0
–0.5
–1.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0
–0.5
–1.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0
–0.5
–1.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0
–0.5
–1.0
LE (LSB)DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
NC
NC
NC
NC
V
OUT
A Sense
V
OUT
A
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
38
37
DAC7744
V
OUT
V
OUT
99kΩ
0.05V
1kΩ
+5V
+V
1000pF
2200pF
+V
OPA350
OPA227
100Ω
1000pF 2200pF
100Ω
21
®
DAC7744
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7744. Note
that each DAC register is edge triggered and not level
triggered. When the LOADDACS signal is transitioned to
HIGH, the digital word currently in the DAC register is
latched. The first set of registers (the input registers) are
triggered via the A0, A1, R/W, and CS inputs. Only one of
these registers is transparent at any given time.
The double-buffered architecture is designed mainly so that
each DAC input register can be written to at any time and
then all DAC voltages updated simultaneously by the rising
edge of LOADDACS. It also allows a DAC input register to
be written to at any point then the DAC output voltages can
be synchronously changed via a trigger signal connected to
LOADDACS.
DIGITAL TIMING
Figure 11 and Table II provide detailed timing for the digital
interface of the DAC7744.
DIGITAL INPUT CODING
The DAC7744 input data is in Straight Binary format. The
output voltage is given by Equation 1.
where N is the digital input code. This equation does not
include the effects of offset (zero scale) or gain (full scale)
errors.
INPUT DAC
A1 A0 R/W CS RST RSTSEL
LOADDACS
REGISTER REGISTER MODE DAC
LLLLXXX Write Hold Write Input A
L H L L X X X Write Hold Write Input B
H L L L X X X Write Hold Write Input C
H H L L X X X Write Hold Write Input D
L L H L X X X Read Hold Read Input A
L H H L X X X Read Hold Read Input B
H L H L X X X Read Hold Read Input C
H H H L X X X Read Hold Read Input D
XXXHXX↑Hold Write Update All
X X X H X X H Hold Hold Hold All
XXXX↑L X Reset to Zero Reset to Zero All
XXXX↑H X Reset to Midscale Reset to Midscale All
TABLE I. DAC7744 Logic Truth Table.
DIGITALLY-PROGRAMMABLE
CURRENT SOURCE
The DAC7744 offers a unique set of features that allows a
wide range of flexibility in designing applications circuits
such as programmable current sources. The DAC7744 offers
both a differential reference input as well as an open-loop
configuration around the output amplifier. The open-loop
configuration around the output amplifier allows transistor
to be placed within the loop to implement a digitally-
programmable, uni-directional current source. The availabil-
ity of a differential reference also allows programmability
for both the full-scale and zero-scale currents. The output
current is calculated as:
Figure 12 shows a DAC7744 in a 4-to-20mA current output
configuration. The output current can be determined by
Equation 3:
At full scale, the output current is 16mA plus the 4mA for
the zero current. At zero scale, the output current is the offset
current of 4mA (1V/250Ω).
(1)
VVL
VHVLN
OUT REF REF REF
=+
()
–•
,65 536
(3)
IVV N V
OUT
=
+
51
250 65 536 1
250
–•,ΩΩ
(2)
IVHVL
RN
VLR
OUT REF REF
SENSE
REF SENSE
=
+
()
–•,
/
65 536
22
®
DAC7744
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tRCS CS LOW for Read 100 ns
tRDS R/W HIGH to CS LOW 10 ns
tRDH R/W HIGH after CS HIGH 10 ns
tDZ CS HIGH to Data Bus in High Impedance 10 70 ns
tCSD CS LOW to Data Bus Valid 85 130 ns
tWCS CS LOW for Write 40 ns
tWS R/W LOW to CS LOW 0 ns
tWH R/W LOW after CS HIGH 10 ns
tAS Address Valid to CS LOW 0 ns
tAH Address Valid after CS HIGH 15 ns
tLS CS LOW to LOADDACS HIGH 40 ns
tLH CS LOW after LOADDACS HIGH 80 ns
tLX LOADDACS HIGH 40 ns
tDS Data Valid to CS LOW 0 ns
tDH Data Valid after CS HIGH 15 ns
tLWD LOADDACS LOW 40 ns
tSS RSTSEL Valid Before RESET HIGH 0 ns
tSH RSTSEL Valid After RESET HIGH 120 ns
tRSS RESET LOW Before RESET HIGH 10 ns
tRSH RESET LOW After RESET HIGH 10 ns
tSSettling Time 11 µs
TABLE II. Timing Specifications (TA = –40°C to +85°C).
FIGURE 11. Digital Input and Output Timing.
t
RCS
CS
t
RDS
t
RDH
t
AS
t
CSD
t
DZ
t
AH
R/W
A0/A1
Data Out Data Valid
t
WCS
CS
t
WS
t
AS
t
AH
t
WH
R/W
A0/A1
t
LS
t
LWD
t
LH
t
S
±0.003% of FSR
Error Band
±0.003% of FSR
Error Band
t
LX
LOADDACS t
DS
t
DH
Data In
V
OUT
Data Read Timing Data Write Timing
t
RSH
RST
V
OUT
,RESET SEL LOW
+FS
–FS
t
SS
t
SH
RESET SEL
V
OUT
,RESET SEL HIGH MS
+FS
–FS
DAC7744 Reset Timing
t
RSS
23
®
DAC7744
FIGURE 12. 4-to-20mA Digitally-Controlled Current Source (1/2 DAC7744).
NC
NC
NC
NC
V
OUT
A Sense
V
OUT
A
V
REF
L AB Sense
V
REF
L AB
V
REF
H AB
V
REF
H AB Sense
V
OUT
B Sense
V
OUT
B
48
47
46
45
44
43
42
41
40
39
38
37
DAC7744
I
OUT
V
PROGRAMMED
R
SENSE
250Ω
I
OUT
V
PROGRAMMED
R
SENSE
250Ω
GND
80kΩ
+1.0V
20kΩ
+V
1000pF
2200pF
+V
OPA2350
100Ω
1000pF 2200pF
100Ω
PACKAGE OPTION ADDENDUM
www.ti.com 27-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC7744E ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744E/1K ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744E/1KG4 ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744EB ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744EB/1K ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744EB/1KG4 ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744EBG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744EC ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744EC/1K ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744EC/1KG4 ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744ECG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7744EG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Oct-2011
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC7744E/1K SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
DAC7744EB/1K SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
DAC7744EC/1K SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC7744E/1K SSOP DL 48 1000 367.0 367.0 55.0
DAC7744EB/1K SSOP DL 48 1000 367.0 367.0 55.0
DAC7744EC/1K SSOP DL 48 1000 367.0 367.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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