© Semiconductor Components Industries, LLC, 2016
December, 2016 − Rev. 1 1Publication Order Number:
NL3HS3124A/D
NL3HS3124A
3.3 V, 2 Channel, 2:1
Differential Mux/Demux
The NL3HS3124A is a 2 channel, 2−to−1 differential multiplexer /
demultiplexer for USB 3.0, PCI Express Generation 3, or other
high−speed serial interface applications. The NL3HS3124A can
switch two differential signals to one of two locations. The device has
minimal channel−to−channel skew as well as minimal channel−to−
channel crosstalk, making the device ideal for high−speed serial
interface applications.
Features
•2 Bidirectional Channel, 2 : 1 Differential Multiplexer/Demultiplexer
•High−speed Signal Switching for 8 Gbps Applications
•High Bandwidth: > 6.3 GHz at −3 dB
•Low Insertion Loss:
♦−0.5 dB at 100 MHz
♦−2.8 dB at 4.0 GHz
•Low Return Loss: −9.27 dB at 4 GHz
•Low Crosstalk: −35 dB at 4 GHz
•Low Off−state Isolation: −19 dB at 4 GHz
•Low Intra−pair Skew: 5 ps Typical
•Low Inter−pair Skew: 35 ps Maximum
•VDD Operating Range: 3.0 V to 3.6 V
•Shutdown Pin (SD) for Power−saving Mode
•Standby Current less than 1 mA
•ESD Tolerance:
♦4000 V HBM
♦300 V MM
♦2000 V CDM
•2.5 mm x 4.5 mm QFN20 Package
•This Device is Pb−Free, Halogen−Free/BFR−Free and is
RoHS−Compliant
Applications
•Routing of High−speed Differential Signals
♦USB 3.0
♦PCIe Gen3
♦DisplayPort 1.2
♦SATA 6 Gbps
MARKING DIAGRAM
3HS3124A = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
www.onsemi.com
(Note: Microdot may be in either location)
QFN20
MN SUFFIX
CASE 485AA
1
3HS3
124A
ALYWG
G
Device Package Shipping†
ORDERING INFORMATION
NL3HS3124AMNTWG QFN20
(Pb−Free) 3000 / Tape
& Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NL3HS3124A
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3
Figure 3. Pinout (Top Through View)
B0P
B0N
B1P
B1N
C0P
C0N
C1P
C1N
SD
A0P
A0N
GND
VDD
A1P
A1N
SEL
VDD
GND
GND
VDD
120
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Table 2. PIN ASSIGNMENT
Pin Name Pin Type Description
A0P 3 I/O Channel 0, Port A Differential Signal I/O
A0N 4 I/O
A1P 7 I/O Channel 1, Port A Differential Signal I/O
A1N 8 I/O
B0P 19 I/O Channel 0, Port B Differential Signal I/O
B0N 18 I/O
B1P 17 I/O Channel 1, Port B Differential Signal I/O
B1N 16 I/O
C0P 15 I/O Channel 0, Port C Differential Signal I/O
C0N 14 I/O
C1P 13 I/O Channel 1, Port C Differential Signal I/O
C1N 12 I/O
SEL 9 Input (CMOS) Mux/Demux Select Pin
SD 2 Input (CMOS) Shutdown Pin
VDD 1, 6, 10 Power Power
GND 5, 11, 20, Center Pad Power Ground
NL3HS3124A
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Table 3. MAXIMUM RATINGS
Symbol Rating Value Unit
VDD Positive DC Supply Voltage −0.5 to +4.6 V
VIN Digital Control Input Voltage (SEL, SD) −0.5 to VDD+0.5 V
TsStorage Temperature −65 to +150 °C
ESD ESD Performance V
HBM (JESD22−A114) All Pins 4000
MM (JESD22−A115−A) All Pins 300
CDM (JESD22−C101) All Pins 2000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
Table 4. RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
VDD Positive DC Supply Voltage 3.0 3.3 3.6 V
VIN Digital Control Input Voltage (SEL, SD) (Note 1) 0 VDD V
VIS Differential Pin Input Voltage (An, Bn, Cn) 0 2.4 V
VIC Common−Mode Input Voltage (An, Bn, Cn) 0 2 V
VID Differential Input Voltage (An, Bn, Cn), peak−to−peak 0 1.6 V
TAOperating Temperature −40 85 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Control input must be held High or Low. It must not float.
Table 5. DC ELECTRICAL CHARACTERISTICS
Voltages referenced to GND. All typical values are at TA = 25°C unless otherwise specified.
Symbol Parameter Conditions VCC (V)
TA = −40°C to +85°C
Unit
Min Typ Max
VIH Input Voltage High SEL, SD 3.0 – 3.6 2.0 V
VIL Input Voltage Low SEL, SD 3.0 – 3.6 0.5 V
IIN Input Leakage Current SEL, SD: VIN = 0 V or VDD 3.6 ±5mA
IIS Switch Input Leakage Current An, Bn, Cn: VIS = 0 V or 2.4 V 3.6 ±10 mA
IDD Supply Current Operating mode: SD = L 3.6 0.2 1 mA
Shutdown mode: SD = H 3.6 1 mA
NL3HS3124A
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Table 6. DYNAMIC CHARACTERISTICS Voltages referenced to GND. All typical values are at TA = 25°C unless otherwise specified.
Symbol Parameter Condition VCC (V)
TA = −40°C to +85°C
Unit
Min Typ Max
DDIL Differential Insertion Loss Channel OFF 3.0 – 3.6 dB
f = 4 GHz −19
f = 100 MHz −47
Channel ON
f = 4 GHz −2.8
f = 100 MHz −0.5
DDNEXT Differential Near−End Crosstalk Adjacent Channels ON 3.0 – 3.6 dB
f = 4 GHz −26
f = 100 MHz −62
BW −3 dB Bandwidth 3.0 – 3.6 6.3 GHz
DDRL Differential Return Loss f = 4 GHz 3.0 – 3.6 −9.27 dB
f = 100 MHz −23.2
RON Switch ON Resistance (Note 2) VIS = 2 V, IIS = 19 mA 3.3 6 W
CIO(ON) ON−State Input/Output Capacitance f = 2.5 GHz 3.0 – 3.6 2.03 pF
2. Measured by the voltage drop between A and B pins at the indicated current through the switch. ON resistance is determined by the lower
of the voltage on the two (A or B ports).
Table 7. SWITCHING CHARACTERISTICS All typical values are for VCC = 3.3 V at TA = 25°C unless otherwise specified.
Symbol Parameter Condition VCC (V)
TA = −405C to +855C
Unit
Min Typ Max
tSTARTUP Startup Time Supply Voltage Valid, or
SD going Low to channel
specified operating conditions
3.0 – 3.6 10 ms
tPD Propagation Delay Port A to Port B or C, or vice−versa 3.0 – 3.6 60 ps
tPZH OFF−State to High
Propagation Delay 3.0 – 3.6 300 ns
tPZL OFF−State to Low
Propagation Delay 3.0 – 3.6 70 ns
tPHZ High to OFF−State
Propagation Delay 3.0 – 3.6 50 ns
tPLZ Low to OFF−State
Propagation Delay 3.0 – 3.6 50 ns
tsk(dif) Differential Skew Intra−pair 3.0 – 3.6 5 ps
tsk Skew Inter−pair 3.0 – 3.6 35 ps
NL3HS3124A
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Output 1 is for an output with internal conditions such that the output is LOW except
when disabled by the output control.
Output 2 is for an output with internal conditions such that the output is HIGH except
when disabled by the output control.
The outputs are measured one at a time with one transition per measurement.
Figure 4. Voltage Waveforms, Enable and Disable Times
CL = load capacitance; includes jig and probe capacitance.
RT = termination resistance; should be equal to Zo of the pulse generator.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 5 MHz; Zo = 50 W; tr ≤ 2.5 ns; tf ≤ 2.5 ns.
Figure 5. Test Circuit for Switching Times
Figure 6. Test Circuit
Table 8. LOADING CONDITIONS FOR SWITCHING/TIMING TESTS
Test
Load
Switch
CLRL
tPLZ, tPZL (Output on B Side) 50 pF 200 W2 x VIC
tPHZ, tPZH (Output on B Side) 50 pF 200 WGND
tPD 200 WOpen
NL3HS3124A
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PACKAGE DIMENSIONS
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
QFN20, 2.5x4.5 MM
CASE 485AA
ISSUE B
DIM MIN MAX
MILLIMETERS
A
A1 0.00 0.05
A3
b0.20 0.30
D2.50 BSC
D2 0.85 1.15
E4.50 BSC
E2
e0.50 BSC
K0.20 ---
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
0.20 REF
b
D2
L
PIN ONE REFERENCE
E2
1
9
19
12
11
D
E
B
A
C0.15
C0.15
2X
2X
e
2
e
20X
20X
0.10 C
0.05 C
A B
NOTE 3
A
20X
K
20X
A1
(A3) SEATING
PLANE
C0.08
C0.10
0.80 1.00
L0.35 0.45
2.85 3.15
TOP VIEW
SIDE VIEW C
BOTTOM VIEW
20
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NL3HS3124A/D
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