© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 5
1Publication Order Number:
CAT1640/D
CAT1640, CAT1641
Supervisory Circuits with
I2C Serial 64K CMOS
EEPROM
Description
The CAT1640 and CAT1641 are complete memory and supervisory
solutions for microcontroller−based systems. A 64 kbit serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together in low power CMOS technology.
Memory interface is via a 400 kHz I2C bus.
The CAT1640 provides a precision VCC sense circuit and drives an
open drain output, RESET low whenever VCC falls below the reset
threshold voltage.
The CAT1641 provides a precision VCC sense circuit that drives an
open drain output, RESET high whenever VCC falls below the reset
threshold voltage.
The power supply monitor and reset circuit protect memory and
system controllers during power up/down and against brownout
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
200 ms after the supply voltage exceeds the reset threshold level. With
both active high and low reset options, interface to microcontrollers
and other ICs is simple. In addition, the RESET (CAT1640) pin can be
used as an input for push−button manual reset capability.
The CAT1640/41 memory features a 64−byte page. In addition,
hardware data protection is provided by a VCC sense circuit that
prevents writes to memory whenever VCC falls below the reset
threshold or until VCC reaches the reset threshold during power up.
Available packages include an 8−pin DIP, SOIC, TSSOP and
4.9 x 3 mm TDFN.
Features
•Precision Power Supply Voltage Monitor
♦5 V, 3.3 V and 3 V Systems
S+5.0 V (±5%, ±10%)
S+3.3 V (±5%, ±10%)
S+3.0 V (±10%)
•Active Low Reset, CAT1640
•Active High Reset, CAT1641
•Valid Reset Guaranteed at VCC = 1 V
•400 kHz I2C Bus
•3.0 V to 5.5 V Operation
•Low Power CMOS Technology
•64−Byte Page Write Buffer
•1,000,000 Program/Erase Cycles
•100 Year Data Retention
•8−pin DIP, SOIC, TSSOP and TDFN Packages
•Industrial Temperature Range
•These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
ORDERING INFORMATION
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PDIP−8
CASE 646AA
SOIC−8
CASE 751BD
TSSOP−8
CASE 948S
TDFN−8
CASE 511AM
For Ordering Information details, see page 13.
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Table 1. THRESHOLD VOLTAGE OPTION
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
−45 4.50 4.75
−42 4.25 4.50
−30 3.00 3.15
−28 2.85 3.00
−25 2.55 2.70
BLOCK DIAGRAM
2kbit
DOUT
ACK
SENSEAMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORDADDRESS
BUFFERS
START/ STOP
LOGIC
EEPROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
VSS
SDA
RESET Controller
Precision
Vcc Monitor
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
RESET (CAT1641)
RESET (CAT1640)
A0
A1
A2
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PIN CONFIGURATION
CAT1640
1
2
3
4
8
7
6
5
CAT1641
1
2
3
4
8
7
6
5
CAT1640
1
2
3
4
8
7
6
5
CAT1641
1
2
3
4
8
7
6
5
8
7
6
5
VCC
RESET
SCL
SDA
CAT1640
A0
A1
A2
RESET
SCL
SDA
CAT1641
A0
A1
A2
8
7
6
5
1
2
3
4
TDFN Package: 4.9 mm x 3 mm
(ZD2)
TSSOP (Y)
PDIP (L)
SOIC (W)
VCC
VSS VSS
RESET
SCL
SDA
A0
A1
A2
VSS
1
2
3
4
VCC
VCC
RESET
SCL
SDA
VSS
A0
A1
A2
VSS
A0
A1
A2
VCC
RESET
SCL
SDA
VSS
A0
A1
A2
VCC
RESET
SCL
SDA
PIN DESCRIPTION
RESET/RESET: RESET OUTPUTS
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull−down
resistor, and the RESET pin must be connected through a
pull−up resistor.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
SCL: SERIAL CLOCK
Serial clock input.
A0, A1, A2: DEVICE ADDRESS INPUTs
When hardwired, up to eight CAT1640/41 devices may be
addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the default
values are zeros.
Table 2. PIN FUNCTION
Pin Name Function
RESET Active Low Reset Input/Output
(CAT1640)
VSS Ground
SDA Serial Data/Address
SCL Clock Input
RESET Active High Reset Output
(CAT1641)
VCC Power Supply
Table 3. OPERATING TEMPERATURE RANGE
Industrial −40°C to 85°C
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SPECIFICATIONS
Table 4. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Temperature Under Bias –40 to +85 °C
Storage Temperature –65 to +105 °C
Voltage on any Pin with Respect to Ground (Note 1) −0.5 to VCC + 2.0 V
VCC with Respect to Ground −0.5 to +7.0 V
Package Power Dissipation Capability (TA = 25°C) 1.0 W
Lead Soldering Temperature (10 seconds) 300 °C
Output Short Circuit Current (Note 1) 100 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Output shorted for no more than one second. No more than one output shorted at a time.
Table 5. D.C. OPERATING CHARACTERISTICS
VCC = +3.0 V to +5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol Parameter Test Conditions Min Typ Max Units
ILI Input Leakage Current VIN = GND to VCC −2 10 mA
ILO Output Leakage Current VIN = GND to VCC −10 10 mA
ICC1 Power Supply Current (Write) fSCL = 400 kHz
VCC = 5.5 V
3 mA
ICC2 Power Supply Current (Read) fSCL = 400 kHz
VCC = 5.5 V
1 mA
ISB Standby Current VCC = 5.5 V
VIN = GND or VCC
40 mA
VIL (Note 3) Input Low Voltage −0.5 0.3 x VCC V
VIH (Note 3) Input High Voltage 0.7 x VCC VCC + 0.5 V
VOL Output Low Voltage
(SDA, RESET)
IOL = 3 mA
VCC = 3.0 V
0.4 V
VOH Output High Voltage
(RESET)
IOH = −0.4 mA
VCC = 3.0 V
VCC − 0.75 V
VTH Reset Threshold CAT164x−45
(VCC = 5.0 V)
4.50 4.75 V
CAT164x−42
(VCC = 5.0 V)
4.25 4.50
CAT164x−30
(VCC = 3.3 V)
3.00 3.15
CAT164x−28
(VCC = 3.3 V)
2.85 3.00
CAT164x−25
(VCC = 3.0 V)
2.55 2.70
VRVALID (Note 2) Reset Output Valid VCC Voltage 1.00 V
VRT (Note 2) Reset Threshold Hysteresis 15 mV
2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
3. VIL min and VIH max are reference values only and are not tested.
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Table 6. CAPACITANCE
TA = 25°C, f = 1.0 MHz, VCC = 5 V
Symbol Test Test Conditions Max Units
COUT (Note 1) Output Capacitance VOUT = 0 V 8 pF
CIN (Note 1) Input Capacitance VIN = 0 V 6 pF
Table 7. AC CHARACTERISTICS
VCC = 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle (Note 2)
Symbol Parameter Min Max Units
fSCL Clock Frequency 400 kHz
tSP Input Filter Spike Suppression (SDA, SCL) 100 ns
tLOW Clock Low Period 1.3 ms
tHIGH Clock High Period 0.6 ms
tR (Note 1) SDA and SCL Rise Time 300 ns
tF (Note 1) SDA and SCL Fall Time 300 ns
tHD; STA Start Condition Hold Time 0.6 ms
tSU; STA Start Condition Setup Time (for a Repeated Start) 0.6 ms
tHD; DAT Data Input Hold Time 0 ns
tSU; DAT Data Input Setup Time 100 ns
tSU; STO Stop Condition Setup Time 0.6 ms
tAA SCL Low to Data Out Valid 900 ns
tDH Data Out Hold Time 50 ns
tBUF (Note 1) Time the Bus must be Free Before a New Transmission Can Start 1.3 ms
tWC (Note 3) Write Cycle Time (Byte or Page) 5 ms
1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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Table 8. RESET CIRCUIT AC CHARACTERISTICS
Symbol Parameter Test Conditions Min Typ Max Units
tPURST Reset Timeout Note 2 130 200 270 ms
tRDP VTH to RESET output Delay Note 3 5ms
tGLITCH VCC Glitch Reject Pulse Width Notes 4 and 5 30 ns
MR Glitch Manual Reset Glitch Immunity Note 5 100 ns
tMRW MR Pulse Width Note 5 5ms
Table 9. POWER−UP TIMING (Notes 5 and 6)
Symbol Parameter Test Conditions Min Typ Max Units
tPUR Power−Up to Read Operation 270 ms
tPUW Power−Up to Write Operation 270 ms
Table 10. AC TEST CONDITIONS
Parameter Test Conditions
Input Pulse Voltages 0.2 VCC to 0.8 VCC
Input Rise and Fall Times 10 ns
Input Reference Voltages 0.3 VCC , 0.7 VCC
Output Reference Voltages 0.5 VCC
Output Load Current Source: IOL = 3 mA; CL = 100 pF
Table 11. RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Max Units
NEND (Note 5) Endurance MIL−STD−883, Test Method 1033 1,000,000 Cycles/Byte
TDR (Note 5) Data Retention MIL−STD−883, Test Method 1008 100 Years
VZAP (Note 5) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 Volts
ILTH (Notes 5 & 7) Latch−Up JEDEC Standard 17 100 mA
1. Test Conditions according to “AC Test Conditions” table.
2. Power−up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
3. Power−Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
7. Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to VCC + 1 V.
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DEVICE OPERATON
Reset Controller Description
The CAT1640/41 precision Reset controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with opendrain
RESET/RESET outputs.
During power−up, the RESET/RESET output remains
active until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200 ms (tPURST) after
reaching VTH. After the tPURST timeout interval, the device
will cease to drive the reset output. At this point the reset
output will be pulled up or down by their respective pull
up/down resistors.
During power−down, the RESET/RESET outputs will be
active when VCC falls below VTH. The RESET/RESET
output will be valid so long as VCC is > 1.0 V (VRVALID). The
device is designed to ignore the fast negative going VCC
transient pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Operation
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a high to low
transition.
When RESET I/O is driven to the active state, the 200 ms
timer will begin to time the reset interval. If external reset is
shorter than 200 ms, Reset outputs will remain active at least
200 ms.
Glitches shorter than 100 ns on RESET input will not
generate a reset pulse.
Hardware Data Protection
The CAT1640/41 family has been designed to solve many
of the data corruption issues that have long been associated
with serial EEPROMs. Data corruption occurs when
incorrect data is stored in a memory location which is
assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output is active, in
progress communications to the EEPROM are aborted and
no new communications are allowed. In this condition an
internal write cycle to the memory can not be started, but an
in progress internal non−volatile memory write cycle can
not be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5 ms) before VCC reaches the minimum value
of 2 V.
Figure 1. RESET/RESET Output Timing
GLITCH
t
VCC PURST
t
PURST
tRPD
t
RVALID
V
VTH
RESET
RESET
RPD
t
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Figure 2. RESET as Manual Reset Input Operation and Timing
tPURST
tMRW
RESET
(Input)
RESET
(Output)
Figure 3. Bus Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA tDH
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EMBEDDED EEPROM OPERATON
The CAT1640 and CAT1641 feature a 64 kbit embedded
serial EEPROM that supports the I2C Bus data transmission
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
Start Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1640/41 monitors the SDA
and SCL lines and will not respond until this condition is
met.
Stop Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8−bit slave address are programmable in metal and the
default is 1010.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT1640/41 monitors the bus and
responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT1640/41 then perform a Read or Write operation
depending on the R/W bit.
Figure 4. Write Cycle Timing
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK8TH BIT
BYTE n
SCL
SDA
ACKNOWLEDGE
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT1640/41 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
When the CAT1640/41 begins a READ mode it transmits
8 bits of data, releases the SDA line and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT1640/41 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
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WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8−bit
address bytes that are to be written into the address pointers
of the device. After receiving another acknowledge from the
Slave, the Master device transmits the data to be written into
the addressed memory location. The CAT1640/41
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an internal
programming cycle to non−volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
Figure 5. Start/Stop Timing
START BIT
A
SD
STOP BIT
SCL
Figure 6. Acknowledge Timing
ACKNOWLEDGE
1
RTSTA
SCL FROM
MASTER 8
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
9
Figure 7. Slave Address Bits
1
Default Configuration 0 1 0 A2 A1 A0 R/W
Page Write
The CAT1640/41 writes up to 64 bytes of data in a single
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to
additional 63 bytes. After each byte has been transmitted, the
CAT1640/41 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1640/41 in a single write cycle.
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Figure 8. Byte Write Timing
* = Don’t Care Bit
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
TA7–A0
BYTE ADDRESS
A
C
K
***
Figure 9. Page Write Timing
* = Don’t Care Bit
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
ACTIVITY:
MASTER
SDA LINE
S
T
A
R
TA7–A0
BYTE ADDRESS
DATA n+63DATA
A
C
K
S
T
O
P
A
C
K
DATA n
A
C
K
P
A
C
K
***
BUS
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation, the
CAT1640/41 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the device is still busy with the write operation,
no ACK will be returned. If a write operation has completed,
an ACK will be returned and the host can then proceed with
the next read or write operation.
Read Operations
The READ operation for the CAT1640/41 is initiated in
the same manner as the write operation with one exception,
that R/W bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
Figure 10. Immediate Address Read Timing
SCL
SDA8TH BIT
STOPNO ACKDATA OUT
8
SLAVE
ADDRESS
S
A
C
K
DATA N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
9
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Immediate/Current Address Read
The CAT1640 and CAT1641 address counter contains the
address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N+1. For all devices, N = E = 4,095. The
counter will wrap around to Zero and continue to clock out
valid data. After the CAT1640 and CAT1641 receives its
slave address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8−bit byte
requested. The master device does not send an acknowledge,
but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1640 and CAT1641 acknowledges, the Master
device sends the START condition and the slave address
again, this time with the R/W bit set to one. The CAT1640
and CAT1641 then responds with its acknowledge and sends
the 8−bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1640 and CAT1641 sends the
initial 8−bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more data.
The CAT1640 and CAT1641 will continue to output an 8−bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1640 and
CAT1641 is sent sequentially with the data from address N
followed by data from address N+1. The READ operation
address counter increments all of the CAT1640 and
CAT1641 address bits so that the entire memory array can
be read during one operation.
Figure 11. Selective Read Timing
* = Don’t Care Bit
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
TA7–A0
BYTE ADDRESS SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
DATA
P
***
S
T
A
R
T
S
T
O
P
Figure 12. Sequential Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+xDATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
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ORDERING INFORMATION
Orderable Part Numbers − CAT1640 Series
(See Notes 1 − 5)
Device Reset Threshold Package Shipping
CAT1640LI−45−G4.50 V − 4.75 V
PDIP
3000 Tape & Reel
CAT1640LI−42−G4.25 V − 4.50 V
CAT1640LI−30−G3.00 V − 3.15 V
CAT1640LI−28−G2.85 V − 3.00 V
CAT1640LI−25−G2.55 V − 2.70 V
CAT1640WI−45−GT3 4.50 V − 4.75 V
SOIC
CAT1640WI−42−GT3 4.25 V − 4.50 V
CAT1640WI−30−GT3 3.00 V − 3.15 V
CAT1640WI−28−GT3 2.85 V − 3.00 V
CAT1640WI−25−GT3 2.55 V − 2.70 V
CAT1640YI−45−GT3 4.50 V − 4.75 V
TSSOP
CAT1640YI−42−GT3 4.25 V − 4.50 V
CAT1640YI−30−GT3 3.00 V − 3.15 V
CAT1640YI−28−GT3 2.85 V − 3.00 V
CAT1640YI−25−GT3 2.55 V − 2.70 V
CAT1640ZD2I45GT3 4.50 V − 4.75 V
TDFN
CAT1640ZD2I42GT3 4.25 V − 4.50 V
CAT1640ZD2I30GT3 3.00 V − 3.15 V
CAT1640ZD2I28GT3 2.85 V − 3.00 V
CAT1640ZD2I25GT3 2.55 V − 2.70 V
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
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Orderable Part Numbers − CAT1641 Series
(See Notes 1 − 5)
Device Reset Threshold Package Shipping
CAT1641LI−45−G4.50 V − 4.75 V
PDIP
3000 Tape & Reel
CAT1641LI−42−G4.25 V − 4.50 V
CAT1641LI−30−G3.00 V − 3.15 V
CAT1641LI−28−G2.85 V − 3.00 V
CAT1641LI−25−G2.55 V − 2.70 V
CAT1641WI−45−GT3 4.50 V − 4.75 V
SOIC
CAT1641WI−42−GT3 4.25 V − 4.50 V
CAT1641WI−30−GT3 3.00 V − 3.15 V
CAT1641WI−28−GT3 2.85 V − 3.00 V
CAT1641WI−25−GT3 2.55 V − 2.70 V
CAT1641YI−45−GT3 4.50 V − 4.75 V
TSSOP
CAT1641YI−42−GT3 4.25 V − 4.50 V
CAT1641YI−30−GT3 3.00 V − 3.15 V
CAT1641YI−28−GT3 2.85 V − 3.00 V
CAT1641YI−25−GT3 2.55 V − 2.70 V
CAT1641ZD2I45GT3 4.50 V − 4.75 V
TDFN
CAT1641ZD2I42GT3 4.25 V − 4.50 V
CAT1641ZD2I30GT3 3.00 V − 3.15 V
CAT1641ZD2I28GT3 2.85 V − 3.00 V
CAT1641ZD2I25GT3 2.55 V − 2.70 V
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. TDFN not available in NiPdAu (–G) version.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
CAT1640, CAT1641
http://onsemi.com
15
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
CAT1640, CAT1641
http://onsemi.com
16
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
E1
D
A
L
eb
b2
A1
A2
E
eB
c
TOP VIEW
SIDE VIEW END VIEW
PIN # 1
IDENTIFICATION
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
SYMBOL MIN NOM MAX
A
A1
A2
b
b2
c
D
e
E1
L
0.38
2.92
0.36
6.10
1.14
0.20
9.02
2.54 BSC
3.30
5.33
4.95
0.56
7.11
1.78
0.36
10.16
eB 7.87 10.92
E 7.62 8.25
2.92 3.80
3.30
0.46
6.35
1.52
0.25
9.27
7.87
CAT1640, CAT1641
http://onsemi.com
17
TDFN8, 3x4.9
CASE 511AM−01
ISSUE A
E
D
PIN #1
IDENTIFICATION
PIN #1 IDENTIFICATION
DAP SIZE
2.6 x 3.3mm
DETAIL A
D2
A2
A3A1
A
b
L
e
E2
A
A1
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
SYMBOL MIN NOM MAX
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.25 0.30 0.35
D 2.90 3.00 3.10
D2 0.90 1.00 1.10
E 4.90
E2 0.90 1.00 1.10
e
4.80
0.65 TYP
5.00
L 0.50 0.60 0.70
TOP VIEW SIDE VIEW BOTTOM VIEW
FRONT VIEW
DETAIL A
A2 0.45 0.55 0.65
CAT1640, CAT1641
http://onsemi.com
18
TSSOP−8
CASE 948S−01
ISSUE C
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B4.30 4.50 0.169 0.177
C--- 1.10 --- 0.043
D0.05 0.15 0.002 0.006
F0.50 0.70 0.020 0.028
G0.65 BSC 0.026 BSC
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
____
SEATING
PLANE
PIN 1
14
85
DETAIL E
B
C
D
A
G
L
2X L/2
−U−
S
U0.20 (0.008) TS
U
M
0.10 (0.004) V S
T
0.076 (0.003)
−T−
−V−
−W−
8x REFK
IDENT
K0.19 0.30 0.007 0.012
S
U0.20 (0.008) T
DETAIL E
F
M
0.25 (0.010)
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
K1
K
JJ1
SECTION N−N
J0.09 0.20 0.004 0.008
K1 0.19 0.25 0.007 0.010
J1 0.09 0.16 0.004 0.006
N
N
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