Integrated Device Technology, Inc. CMOS DUAL-PORT RAM 32K (4K x 8-BIT) IDT7134SA IDT7134LA FEATURES: * High-speed access Military: 35/45/55/70ns (max.) Commercial: 25/35/45/55/70ns (max.) Low-power operation IDT7134SA Active: 500mW (typ.) Standby: 5mW (typ.) IDT7134LA Active: 500mW (typ.) Standby: imW (typ.) Fully asynchronous operation from either port Battery backup operation2V data retention TTL-compatible; single 5V (10%) power supply Available in several popular hermetic and plastic packages Military product compliant to MIL-STD-883, Class B Industrial temperature range (40C to +85C) is available, tested to military electrical specifications DESCRIPTION: The IDT7134 is an extremely high-speed 4K x 8 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contentian when both sides simultaneously access the same Dual-Port RAM location. The IDT7 134 provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. Itis the users responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter avery low standby power mode. Fabricated using IDTs CMOS high-performance technology, these Dual-Port typically on only 500mW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200uUW from a 2V battery. The IDT7134 is packaged on either a sidebraze or plastic 48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Ceramic Flatpack. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class 8, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM RMWL R/WR CEL 4 ! CER OEL OER , VvOoL - VO7L. <______ COLUMN y_N\\ COLUMN je 1/00R- OTR A ADDRESS MEMORY ADDRESS. a RE Aol - A11L *] DECODE ARRAY DECODE [* AoR- AtNR LOGIC LOGIC The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1983 Integrated Device Technology, Inc. 6.6 2720 drw 01 NOVEMBER 1993 psc O79/2IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT} MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS a om ce.d1 ~~ asbvec og SQ we ge ges AW. 2 47 CEB INDEX alOoqaZ2rloslor zac Aut Q3 46 LJ R/Wa CE aT Ato. C] 4 45C Aur Yy RELALILELILAT PLA LALLA LITLE OE OS 44 D Aion 765 43 2 y 52 51 50 49 48 47 _ Ao. (16 43 [JOER ALPE 28 460] OER Aw (7 42 [] Aor Aa fig 457 TAor Ao C8 41 AIA Eo aacd a, As. 9 40 D Aer Aa f = He qAin As. O10 IDT7 se Aer Aa fii 437 J Aor As. O11 134 38 GAaa = aor] ALOli2 P81 37 GAse Aa fo 1? <hr A7v_()13 & 36 [J Aer Aa 213 pre 134 410 J Asa AsC]14 C48-2 35 A7R an ti14 S2- 405] Asp Ao. 15 34 DAsrR a 45 397 VOut}i6 DIP 33 Agr Aa fs = 4 ASR VO1.0]17 TOP VIEW 32 HVor Ao [216 1 a ew 387 Java vOa (18 31 Hoer = ol -4 vO. C19 30 LIVO5A VOo. fs 17 S70 Asa Oa. 20 29 DvosA VOups 18 367 J Aor VOs. 21 28 LJVO3A yOu [219 35 Two VOet Lj22 27 Lvoer b 09 -4 von C23 26 FI] VOR HO Fa 31 20 29 24 25 26 27 28 29.30 319238 OF GND [424 25 D1 \/o0r \ / FUFUrtririyrrriPrPirrvryvririvera a aemreadgaacedtkckre: zr or 2 6855225055086 2720 drw 03. ABSOLUTE MAXIMUM RATINGS Symbol Rating Coml. Mil. Unit VTERM4 Terminal Voltage | -0.5to+7.0 | 0.5to+7.0| V with Respect ae Sc to Ground INDEX 28 g Els Is 88 8 z z I Ta Operating Oto +70 | -5510 +125] C /Trititrcrrurtururerurel Temperature 6 5 4 3 2 &4 48 47 46 45 44 43 Taias |Temperature ~55 to +125 | 6510 +135] C ALE 7 1 420 J Aor Under Bias Aafia 41cC] Ain Tsta |Storage -55to +125 | -65to+150] C Aa foo 400] Aza Temperature Aa 310 390] Asr Prt?) [Power Dissipation 1.5 15 w As. Fo 11 380 J AaR lour__]DC Output Current] _50 50 mA Aol f= 12 IDT7134 S7u TAsR An 313 360 J Aca 2720 tbl 01 L48-1 7 NOTE: Aa [314 & 350 J Avr 1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS Ast E215 F48-1 345] Asa may cause permanent damage to the device. This is a stress rating only 4 and functional operation of the device at these or any other conditions VOo fa 16 LCC/Flatpack 334 J ASR above those indicated in the operational sections of this specificationisnot VOILE 317 TOP VIEW 320 J vo7r implied. Exposure to absolute maximum rating conditions for extended vO [218 317] VOer periods may affect reliability. 19 20 21 22 23 24 25 26 27 28 29 30 2. VTERM must not exceed Vcc + 0.5V. FUrvrirerarervarvririry rf 3. VTERM = 5,5V. 72 aa@ fo E z & 5 = 5 9eo0o00 02 o () SPB S325 5; 0535353 53585 CAPACITANCE' (Ta = +25C, f = 1.0MHz) Symbol Parameter Conditions | Max. | Unit 2720 drw 04 CIN input Capacitance VIN = OV 11 pF * Index Indicator is PIN 1 ID in package outline. CoutT Output Capacitance VouT = OV 11 pF 2720 thi 02 NOTE: 1. This parameter is determined by device characterization but is not production tested. 6.6 2IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES RECOMMENDED OPERATING RECOMMENDED DC OPERATING CONDITIONS TEMPERATURE AND SUPPLY VOLTAGE Symbol Parameter Min. Typ. Max. | Unit Ambient Veco Supply Voltage 45 5.0 5.5 Vv Grade Temperature GND Vec GND Ground 0 0 0 V Military 55C to +125C ov 5.0V + 10% Vin inputHigh Voltage | 22 | Joo] v 1 iO, o> + Tey Commercial 0C to +70C ov 5.0V + 10% VIL input Low Voltage 50) _ 08 Vv 2720 tb1 08 NOTES: 2720 tbl 04 1. Vit (min.) = -3.0V for pulse width less than 20ns. 2. VTERM must not exceed Vcc + 0.5V. DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (Vcc = 5V + 10%) IDT7134SA IDT7134LA Symbol Parameter Test Conditions Min. Max. Min. Max. Unit {HL Input Leakage Current] Vcc = 5.5V, VIN= OV to Vcc _ 10 5 LA {ILo} Output Leakage Current | CE = Vin, VouT = OV to Voc 10 5 pA VoL Output Low Voltage lo. = 6MA 0.4 _ 0.4 Vv loL = 8mMA _ 0.5 _ 0.5 Vv VOH Output High Voltage loH = ~4mA 2.4 _ 2.4 _ V 2720 thi 05 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE" (vcc = 5.0V + 10%) 7134x254) 7134X35 7134X45 7134X55 7134X70 Symbol Parameter Test Conditions | Version | Typ.@] Max.| Typ.2) | Max. | Typ.| Max. | Typ. | Max. | Typ.)| Max. | Unit Icc Dynamic Operating [CE < ViL MIL. Ss} | | 300 | | 280] | 270 | | 270 | mA Current Outputs Open L} _ _ 260 _ 240 _ 220 _ 220 (Both Ports Active) |f = fuax) COML. S} | 280] 260 | | 240] | 240 | 240 L| | 240] 220 | | 200] | 200 | | 200 iss: | Standby Current CEL and CER> Vin |MIL. S| | 2 75 25 70 25 70 25 70 mA (Both PortsTTL | f = fwax L] | 25 55 25 50 | 25 50 25 50 Level Inputs) COM'L. S} 25 80 | 25 75 25 70 25 70 25 70 L} 25 50 | 25 45 25 40 25 40 25 40 Ise | Standby Current CELorCER>ViqH |MIL. Ss} |} |200/ | 190] |180 | | 180] mA {One PortTTL Active Port Outputs Ll} _ 170 _ 160 _ 150 _ 150 Level Inputs) Open, f = fMax [COML. S| J] 180 | 170 | | 160] | 160 | | 160 L] | 150] ~ 140 |] | 130] | 130 | |] 130 Ise Full Standby Current] Both Ports CEL and | MIL. s} _ 1.0 30 1.0 30 1.0 30 1.0 30 mA (Both PartsAll CER 2 Voc - 0.2V Ly | 02 10 0.2 | 10 | 02 | 10 0.2 | 10 CMOS Level Inputs) J Vin > Vec-0.2V or [COM'L. S] 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15 Vin < 0.2V, f = 0) L| o2 | 40] 02 | 40 | 02 | 40] 02 | 40 |] 02 | 40 ispa_ | Full Standby Current]One PortCE. or [MIL Ss] | | | 1909 | | 180] | 170 | | 170] mA (One PortAll CER > Voc - 0.2V tL] {| 160 | | 150] | 140 | | 140 CMOS Level Inputs) | Vin > Voc -0.2Vor |COM'L. S} 170 | 160 _ 150 _ 150 _~ 150 ViIN< 0.2V LE 140] 130 | | 120] | 120 | | 120 Active Port Outputs Open, f = fuax) NOTES: 2720 tbl 06 1. X in part number indicates power rating (SA or LA). 2. Vcc = 5V, TA= +25C. 3. fMax = 1/tRc = Allinputs cycling atf = 1/tAc (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby Isea. 4. QC to +70C temperature range. 5. At Vec<2.0V input leakages are undefined. 6.6IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (LA Version Only) Vic = 0.2V, VHC = Vcc - 0.2V Symbol Parameter Test Condition Min. | Typ. | Max. | Unit VbR VCC for Data Retention Vec = 2V 2.0 _ _ Vv IccDR Data Retention Current CE Vuc MIL. 100 | 4000 yA VIN VHC or VLC COML. 100 1500 tcorn Chip Deselect to Data Retention Time 0 _ _ ns tR) Operation Recovery Time tac _ _ ns NOTES: 2720 tbl 07 1. Vee = 2V, Ta = +25C. 2. tro = Read Cycle Time. 3. This parameter is guaranteed but not tested. LOW Vcc DATA RETENTION WAVEFORM Il DATA RETENTION MODE I Voc Vor > 2V tcDR tA CE VIR Vor ViH 2720 dew 0S. AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Falt Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figures 1 and 2 2720 tbl 08 +5V 45V 12500 125022 DATAouT + DATAout 4 .%$ 7750 | 30pF * 2720 drw 06a Figure 1. Output Load 77522 5pF * 1 2720 drw 06b Figure 2. Output Load (for tLz, tHz, twz, tow) *Including scope and jig 6.6 4IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE 7134x259 | 7134x35 | 7134X45 7134X55 | 7134X70 Symbol! Parameter Min. | Max. Min. | Max. Min. | Max. Min. | Max. | Min. | Max. Unit READ CYCLE tRC Read Cycle Time 25 _ 35 _ 45 _ 55 _ 70 _ ns TAA Address Access Time _ 25 - 35 _ 45 _ 55 ~_ 70 ns TACE Chip Enable Access Time _ 25 _ 35 _ 45 _ 55 _ 70 ns tAQE Output Enable Access Time _ 15 _ 20 _ 25 _ 30 _ 40 ns 1OH Output Hold from Address Change 0 _ a _ 0 _ 0 _ 0 _ ns tLZ Output Low-Z Time" 4) Oo |o |] 5 |5 5 ~ ns tHz Output High-Z Time! 2) | 16 | | 2 | | 2 | |] 25 | | 30 ns tPU Chip Enable to Power Up Time! 0 _ 0 _ 0 _ 0 _- 0 _ ns {PD Chip Disable to Power Down Time?) | 50 _ 50 _- 50 _ 50 _ 50 ns NOTES: 2720 tol 09 1. Transition is measured +500mV from low or high impedance voltage with load (Figures 1 and 2). 2. This parameter is guaranteed but not tested. 3. OC ta +70C temperature range only. 4. X" in part number indicates power rating (SA or LA). TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE"? | trac >| ADDRESS K TAA | 10H | | toH 1 DATAouT PREVIOUS DATA VALIC DATA VALID 2720 dew 07 TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE: 9) tACE CE OE DATAouT VALID DATA loc tPuU >| 1PD CURRENT at 50% 50% \sB 2720 drw 08 NOTES: 1. RAW is high for Read Cycles. 2. Device is continuously enabled, CE = Vit. 3. Addresses valid prior to or coincident with CE transition low. 4, OE = ViL. 6.6 5IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE 7134x250) 7134X35 7134X45 7134X55 7134X70 Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit WRITE CYCLE two Write Cycle Time 25 _ 35 _ 45 > 55 _ 70 _ ns tew Chip Enable to End-of-Write 20 _ 30 _ 40 50 60 _ ns taw Address Valid to End-of-Write 20 _ 30 _ 40 _ 50 _ 60 _ ns tas Address Set-up Time 0 _ 0 _ 0 _ 0 - 0 _ ns twe Write Pulse Width 20 _ 25 _ 40 _ 50 _ 60 _ ns 1wR Write RecoveryTime 0 _ 0 _ 0 _ 0 _ 0 _ ns 1DW Data Valid to End-of-Write 15 _ 20 _ 20 _ 25 _ 30 _ ns tHz Output High-Z Time!" + 15 | | 20 | 20 | | 25 | YT 30 ns {DH Data Hold Time!) 0 | 3 3 | 3 3 ns twz Write Enabled to Output in High-z!" _ 15 _ 20 _ 20 _ 25 _ 30 ns tow Output Active from End-of-Writel? #9) 3 _- 3 _ 3 _ 3 _ 3 ns twoo | Write Pulse to Data Delay!) 50 | 70 | so | | so | | go ns topp | Write Data Valid to Read Data Delay) | 35 | | 55 J 55 | | 65 | | 70 ns NOTES: 2720 tol 10 1. Transition is measured +500mV from low or high impedance voltage with load (Figures 1 and 2). 2. This parameter is guaranteed but not tested. 3. The specification for to must be met by the device supplying write data to the RAM under all operating conditions. Although toy and tow values will vary over voltage and temperature, the actual tou will always be smaller than the actual tow. 4. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Read with Port-to-Port Delay. 5. 0C to +70C temperature range only. 6. X" in part number indicates power rating (SA or LA). TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY) two ADDRa MATCH DATANR ADDR. DATAOUTL VALID 2720 drw 09 NOTE: 1. Write cycle parameters should be adhered to, in order to ensure proper writing. 6.6 6IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING": 2 * 4:6 7) twe ADDRESS >< >< ae tasm| Yy_ OE J TAW <atWR CE Ye twp (7) p tHZ ht RAW N x haitwz ) tHz ) tz tow DATAouT (4) i tow ~] toH DATAN 2720 drw 10 TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING": 2: 3:5) two N\ VY ADDRESS x xK tAW } / CE JA jp tAsm Tew Pe - tWR RAV \ / tow tDH DATAN 2720 drw 11 NOTES: . Either RAV or CE must be high during all address transitions. . Awrite occurs during the overlap (tew or twe) of a low CE and a RW. . twA is measured from the earlier of CE or RAW going high to the end-of-write cycle. . During this period, the I/O pins are in the output state, and input signals must not be applied. If the CE low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. . Transition is measured +500mV from steady state with a 5pF load {including scope and jig). This parameter is sampled and not 100% tested. . If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of twe or (twz + tow) to allow the I/O drivers to turn off data to be placed on the bus for the required tow. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp. NOM RON = 6.6 7IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTIONAL DESCRIPTION The IDT7134 provides two ports with separate control, address, and |/O pins that permit independent access for reads ar writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE high). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable contro! (OE). Inthe read mode, the port's OE turns on the output drivers when set LOW. Non-contention READ/ WRITE conditions are illustrated in the table below. TABLE | - READ/WRITE CONTROL 6.6 Left or Right Port! RAW | CE|GE] Doz Function X H x Zz Port Disabled and in Power Down Mode, Issz or Isa4 x H | xX Z CEr = CEL = H, Power Down Mode, IsB1 or IsB3 L L X DATAIN | Data on port written into memory H L L | DATAouT | Data in memory output on port x x H Z High impedance outputs 2720 th 11 NOTE: 1. Aoi - A11L # Aor- Arr H = HIGH, L = LOW, X = Don't Care, Z = High Impedance 8IDT7134SA/LA CMOS DUAL-PORT RAM 32K (4K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXX A 999 A A Device Type Power Speed Package Process/ Temperature Range Biank Commercial (0 C to +70 C) B Military (-55 C 104125 C) Compliant to MIL-STD-883, Class B P 48-pin Plastic DI (Cae. Cc 48-pin Ceramic DIP (C48-2) J 52- bin PLCC (J52-1) LA 8 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1) 25 Commercial Only 45 Speed in Nanoseconds | LA Low Power | SA Standard Power | 7134 32K (4K x 8-Bit) Dual-Port RAM 2720 drw 12 6.6 9