LMR14203XMK/NOPB - Texas Instruments

0.00 0.05 0.10 0.15 0.20 0.25 0.30

100

EFFICIENCY (%)

LOAD CURRENT (A)

1.2Vout

3.3Vout

0.00 0.05 0.10 0.15 0.20 0.25 0.30

100

EFFICIENCY (%)

LOAD CURRENT (A)

1.2Vout

3.3Vout

LMR14203

www.ti.com

SNVS732C –OCTOBER 2011–REVISED APRIL 2013

LMR14203 SIMPLE SWITCHER

42Vin, 0.3A Step-Down Voltage Regulator in SOT-23

Check for Samples: LMR14203

1FEATURES DESCRIPTION

The LMR14203 is a PWM DC/DC buck (step-down)

2• Input Voltage Range of 4.5V to 42V regulator. With a wide input range from 4.5V-42V, it is

• Output Voltage Range of 0.765V to 34V suitable for a wide range of applications such as

• Output Current up to 0.3A power conditioning from unregulated sources. They

feature a low RDSON (0.9Ωtypical) internal switch for

• 1.25 MHz Switching Frequency maximum efficiency (85% typical). Operating

• Low Shutdown Iq, 16 µA Typical frequency is fixed at 1.25 MHz allowing the use of

• Short Circuit Protected small external components while still being able to

have low output voltage ripple. Soft-start can be

• Internally Compensated implemented using the shutdown pin with an external

• Soft-Start Function RC circuit allowing the user to tailor the soft-start time

• Thin SOT-23-6 Package (2.97 x 1.65 x 1mm) to a specific application.

• Fully Enabled for WEBENCH® Power Designer The LMR14203 is optimized for up to 300 mA load

current.

PERFORMANCE BENEFITS Additional features include: thermal shutdown, VIN

• Tight Accuracy for Powering Digital ICs under-voltage lockout, and gate drive under-voltage

• Extremely Easy to Use lockout. The LMR14203 is available in a low profile

SOT-6L package.

• Tiny Overall Solution Reduces System Cost

APPLICATIONS

• Point-of-Load Conversions from 5V, 12V, and

24V Rails

• Space Constrained Applications

• Battery Powered Equipment

• Industrial Distributed Power Applications

• Power Meters

• Portable Hand-Held Instruments

System Performance

Efficiency vs Load Current Efficiency vs Load Current

VIN = 12V, VOUT = 1.2V and 3.3V VIN = 24V, VOUT = 1.2V and 3.3V

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CB 1

3 4

LMR14203

GND

PIN 1 ID VIN

SHDN

LMR14203

VOUT

VIN

CBOOT

CIN COUT

GND

SHDN

VIN

LMR14203

SNVS732C –OCTOBER 2011–REVISED APRIL 2013

www.ti.com

Connection Diagram

Top View

Figure 1. 6 Lead SOT Package

See Package Number DDC0006A

Pin Descriptions

Pin Name Function

1 CB SW FET gate bias voltage. Connect CBOOT cap between CB and SW.

2 GND Ground connection.

Feedback pin: Set feedback voltage divider ratio with VOUT = VFB (1+(R1/R2)). Resistors should be

3 FB in the 100-10K range to avoid input bias errors.

4 SHDN Logic level shutdown input. Pull to GND to disable the device and pull high to enable the device. If

this function is not used tie to VIN or leave open.

5 VIN Power input voltage pin: 4.5V to 42V normal operating range.

6 SW Power FET output: Connect to inductor, diode, and CBOOT cap.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LMR14203

LMR14203

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SNVS732C –OCTOBER 2011–REVISED APRIL 2013

Absolute Maximum Ratings(1)(2)

VIN -0.3V to +45V

SHDN -0.3V to (VIN+0.3V) <45V

SW Voltage -0.3V to +45V

CB Voltage above SW Voltage 7V

FB Voltage -0.3V to +5V

Maximum Junction Temperature 150°C

Power Dissipation(3) Internally Limited

For soldering specifications:http://www.ti.com/lit/SNOA549

ESD Susceptibility(4)

Human Body Model 1.5 kV

(1) Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the

device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test

conditions, see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal

resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated

using: PD(MAX) = (TJ(MAX) −TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and

the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal

shutdown engages at TJ=175°C (typ.) and disengages at TJ=155°C (typ).

(4) Human Body Model, applicable std. JESD22-A114-C.

Operating Conditions

Operating Junction Temperature Range(1) −40°C to +125°C

Storage Temperature −65°C to +150°C

Input Voltage VIN 4.5V to 42V

SW Voltage Up to 42V

(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are

100% production tested. All limits at temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC)

methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).

Product Folder Links: LMR14203

LMR14203

SNVS732C –OCTOBER 2011–REVISED APRIL 2013

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Electrical Characteristics

Specifications in standard type face are for TJ= 25°C and those with boldface type apply over the full Operating

Temperature Range ( TJ=−40°C to +125°C). Minimum and Maximum limits are ensured through test, design, or statistical

correlation. Typical values represent the most likely parametric norm at TJ= +25°C, and are provided for reference purposes

only. Unless otherwise stated the following conditions apply: VIN = 12V.

Parameter Test Conditions Min(1) Typ(2) Max(1) Units

IQQuiescent current SHDN = 0V 16 40 µA

Device On, Not Switching 1.30 1.75 mA

Device On, No Load 1.35 1.85

RDSON Switch ON resistance See (3) 0.9 1.6 Ω

ILSW Switch leakage current VIN = 42V 0.0 0.5 µA

ICL Switch current limit See (4) 525 mA

IFB Feedback pin bias current See (5) 0.1 1.0 µA

VFB FB Pin reference voltage 0.747 0.765 0.782 V

tMIN Minimum ON time 100 ns

fSW VFB = 0.5V 0.95 1.25 1.50

Switching frequency MHz

VFB = 0V 0.35

DMAX Maximum duty cycle 81 87 %

VUVP Undervoltage lockout thresholds On threshold 4.4 3.7 V

Off threshold 3.5 3.25

VSHDN Shutdown threshold Device on 2.3 1.0 V

Device off 0.9 0.3

ISHDN Shutdown pin input bias current VSHDN = 2.3V(5) 0.05 1.5 µA

VSHDN = 0V 0.02 1.5

THERMAL SPECIFICATIONS

RθJA Junction-to-Ambient Thermal See (6) 121 °C/W

Resistance, SOT-6L Package

(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are

100% production tested. All limits at temperature extremes are ensured via correlation using standard Statistical Quality Control (SQC)

methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely norm.

(3) Includes the bond wires, RDSON from VIN pin to SW pin.

(4) Current limit at 0% duty cycle.

(5) Bias currents flow into pin.

(6) All numbers apply for packages soldered directly onto a 3" x 3" PC board with 2 oz. copper on 4 layers in still air in accordance to

JEDEC standards. Thermal resistance varies greatly with layout, copper thickness, number of layers in PCB, power distribution, number

of thermal vias, board size, ambient temperature, and air flow.

Product Folder Links: LMR14203

SWITCH CURRENT LIMIT (mA)

1.0 1.6 2.2 2.8 3.4 4.0

800

600

400

200

SHDN PIN VOLTAGE (V)

0.0 0.1 0.2 0.3

LOAD CURRENT (A)

100

EFFICIENCY (%)

VIN = 36V

VIN = 12V

VIN = 24V

LMR14203

www.ti.com

SNVS732C –OCTOBER 2011–REVISED APRIL 2013

Typical Performance Characteristics

Efficiency vs. Load Current

(VOUT = 3.3V) Input UVLO Voltage vs. Temperature

Figure 2. Figure 3.

Switch Current Limit vs. SHDN Pin Voltage

(Soft-start Implementation) SHDN Pin Current vs. SHDN Pin Voltage

Figure 4. Figure 5.

Switching Node and Output Voltage Waveforms

VIN = 12V, VOUT = 3.3V, IOUT = 200 mA

Top trace: VOUT, 10 mV/div, AC Coupled

Bottom trace: SW, 5V/div, DC Coupled

T = 1 µs/div Figure 6.

Product Folder Links: LMR14203

Max Duty

Cycle Limit

OSC

LIMIT

SET

PWM

Comp RESET FET

Driver

BUCK

DRIVE

Error

Amp

Bandgap Soft

Start Thermal

Shutdown

TSD

SHDN

Inductor

Current

Measurement

GND

UVLO

Comp

UVLO

Voltage

Regulator

VIN

LMR14203

SNVS732C –OCTOBER 2011–REVISED APRIL 2013

www.ti.com

Typical Performance Characteristics (continued)

Load Transient Waveforms Start-Up Waveform

VIN = 12V, VOUT = 3.3V, IOUT = 300 mA to 200 mA to 300 mA VIN = 12V, VOUT = 3.3V, IOUT = 50 mA

Top trace: VOUT, 20 mV/div, AC Coupled Top trace: VOUT, 1V/div, DC Coupled

Bottom trace: IOUT, 100 mA/div, DC Coupled Bottom trace: SHDN, 2V/div, DC Coupled

T = 200 µs/div T = 40 µs/div

Figure 7. Figure 8.

Block Diagram

Product Folder Links: LMR14203

L = (VIN - VOUT)VOUT

VIN x IRIPPLE x fSW

LMR14203

www.ti.com

SNVS732C –OCTOBER 2011–REVISED APRIL 2013

APPLICATION INFORMATION

Protection

The LMR14203 has dedicated protection circuitry running during normal operation to protect the IC. The thermal

shutdown circuitry turns off the power device when the die temperature reaches excessive levels. The UVLO

comparator protects the power device during supply power startup and shutdown to prevent operation at

voltages less than the minimum input voltage. A gate drive (CB) under-voltage lockout is included to ensure that

there is enough gate drive voltage to drive the MOSFET before the device tries to start switching. The

LMR14203 also features a shutdown mode decreasing the supply current to approximately 16 µA.

Continuous Conduction Mode

The LMR14203 contains a current-mode, PWM buck regulator. A buck regulator steps the input voltage down to

a lower output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady

state), the buck regulator operates in two cycles. The power switch is connected between VIN and SW. In the first

cycle of operation the transistor is closed and the diode is reverse biased. Energy is collected in the inductor and

the load current is supplied by COUT and the rising current through the inductor. During the second cycle the

transistor is open and the diode is forward biased due to the fact that the inductor current cannot instantaneously

change direction. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of

these two cycles determines the output voltage. The output voltage is defined approximately as:

D=VOUT/VIN and D’ = (1-D)

where

• D is the duty cycle of the switch. (1)

D and D' will be required for design calculations.

Design Procedure

This section presents guidelines for selecting external components.

Setting the Output Voltage

The output voltage is set using the feedback pin and a resistor divider connected to the output as shown on the

front page schematic. The feedback pin voltage is 0.765V, so the ratio of the feedback resistors sets the output

voltage according to the following equation:

VOUT=0.765V(1+(R1/R2)) (2)

Typically R2 will be given as 100Ω-10 kΩfor a starting value. To solve for R1 given R2 and VOUT use

R1=R2((VOUT/0.765V)-1).

Input Capacitor

A low ESR ceramic capacitor (CIN) is needed between the VIN pin and GND pin. This capacitor prevents large

voltage transients from appearing at the input. Use a 2.2 µF-10 µF value with X5R or X7R dielectric. Depending

on construction, a ceramic capacitor’s value can decrease up to 50% of its nominal value when rated voltage is

applied. Consult with the capacitor manufacturer's data sheet for information on capacitor derating over voltage

and temperature.

Inductor Selection

The most critical parameters for the inductor are the inductance, peak current, and the DC resistance. The

inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages.

(3)

A higher value of ripple current reduces inductance, but increases the conductance loss, core loss, and current

stress for the inductor and switch devices. It also requires a bigger output capacitor for the same output voltage

ripple requirement. A reasonable value is setting the ripple current to be 30% of the DC output current. Since the

ripple current increases with the input voltage, the maximum input voltage is always used to determine the

inductance. The DC resistance of the inductor is a key parameter for the efficiency. Lower DC resistance is

Product Folder Links: LMR14203

LMR14203

SNVS732C –OCTOBER 2011–REVISED APRIL 2013

www.ti.com

available with a bigger winding area. A good tradeoff between the efficiency and the core size is letting the

inductor copper loss equal 2% of the output power. See AN-1197 SNVA038 for more information on selecting

inductors. A good starting point for most applications is a 10 µH to 22 µH with a 0.7A or greater current rating for

the LMR14203. Using such a rating will enable the LMR14203 to current limit without saturating the inductor.

This is preferable to the device going into thermal shutdown mode and the possibility of damaging the inductor if

the output is shorted to ground or other longterm overload.

Output Capacitor

The selection of COUT is driven by the maximum allowable output voltage ripple. The output ripple in the constant

frequency, PWM mode is approximated by:

VRIPPLE = IRIPPLE(ESR+(1/(8fSWCOUT))) (4)

The ESR term usually plays the dominant role in determining the voltage ripple. Low ESR ceramic capacitors are

recommended. Capacitors in the range of 22 µF-100 µF are a good starting point with an ESR of 0.1Ωor less.

Bootstrap Capacitor

A 0.15 µF ceramic capacitor or larger is recommended for the bootstrap capacitor (CBOOT). For applications

where the input voltage is less than twice the output voltage a larger capacitor is recommended, generally 0.15

µF to 1 µF to ensure plenty of gate drive for the internal switches and a consistently low RDSON.

Soft-Start Components

The LMR14203 has circuitry that is used in conjunction with the SHDN pin to limit the inrush current on start-up

of the DC/DC switching regulator. The SHDN pin in conjunction with a RC filter is used to tailor the soft-start for a

specific application. When a voltage applied to the SHDN pin is between 0V and up to 2.3V it will cause the cycle

by cycle current limit in the power stage to be modulated for minimum current limit at 0V up to the rated current

limit at 2.3V. Thus controlling the output rise time and inrush current at startup. The resistor value should be

selected so the current sourced into the SHDN pin will be greater then the leakage current of the SHDN pin (1.5

µA ) when the voltage at SHDN is equal or greater then 2.3V.

Shutdown Operation

The SHDN pin of the LMR14203 is designed so that it may be controlled using 2.3V or higher logic signals. If the

shutdown function is not to be used the SHDN pin may be tied to VIN. The maximum voltage to the SHDN pin

should not exceed 42V. If the use of a higher voltage is desired due to system or other constraints it may be

used, however a 100 kΩor larger resistor is recommended between the applied voltage and the SHDN pin to

protect the device.

SCHOTTKY Diode

The breakdown voltage rating of the diode (D1) is preferred to be 25% higher than the maximum input voltage.

The current rating for the diode should be equal to the maximum output current for best reliability in most

applications. In cases where the duty cycle is greater than 50%, the average diode current is lower. In this case it

is possible to use a diode with a lower average current rating, approximately (1-D)IOUT, however the peak current

rating should be higher than the maximum load current. A 0.5A to 1A rated diode is a good starting point.

Layout Considerations

To reduce problems with conducted noise pick up, the ground side of the feedback network should be connected

directly to the GND pin with its own connection. The feedback network, resistors R1 and R2, should be kept

close to the FB pin, and away from the inductor to minimize coupling noise into the feedback pin. The input

bypass capacitor CIN must be placed close to the VIN pin. This will reduce copper trace resistance which effects

input voltage ripple of the IC. The inductor L1 should be placed close to the SW pin to reduce EMI and capacitive

coupling. The output capacitor, COUT should be placed close to the junction of L1 and the diode D1. The L1, D1,

and COUT trace should be as short as possible to reduce conducted and radiated noise and increase overall

efficiency. The ground connection for the diode, CIN, and COUT should be as small as possible and tied to the

system ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the

system ground plane. For more detail on switching power supply layout considerations see Application Note AN-

1149: Layout Guidelines for Switching Power Supplies SNVA021.

Product Folder Links: LMR14203

GND

VIN CB

SHDN

LMR14203

COUT

12V OUT

15V to 42V IN

60V 500 mA

CBOOT

CIN

14.7k

1k 22 PF

0.15 PF

2.2 PF

GND

SHDN

LMR14203

COUT

5V OUT

7V to 42V IN

CBOOT

CIN

5.62k

1.02k 47PF

0.15 PF

2.2 PF

VIN 60V 500 mA

GND

SHDN

LMR14203

COUT

3.3V OUT

4.5V to 42V IN

60V 500 mA

CIN

3.4k

1.02k

2.2 PF

0.15PF

47 PF

15 PH

CBOOT

VIN

LMR14203

www.ti.com

SNVS732C –OCTOBER 2011–REVISED APRIL 2013

Typical Applications

Figure 9. Application Circuit, 3.3V Output

Figure 10. Application Circuit, 5V Output

Figure 11. Application Circuit, 12V Output

Product Folder Links: LMR14203

GND

VIN CB

SHDN

LMR14203

COUT

0.8V OUT

4.5V to 12V IN

60V 500 mA

CBOOT

30.9

787

0.15 PF

2.2 PF100PF

CIN

GND

SHDN

LMR14203

COUT

15V OUT

18V to 42V IN

60V 500 mA

CBOOT

CIN

28k

1.5k

2.2 PF

0.15PF

22 PF

VIN

LMR14203

SNVS732C –OCTOBER 2011–REVISED APRIL 2013

www.ti.com

Figure 12. Application Circuit, 15V Output

Figure 13. Application Circuit, 0.8V Output

Product Folder Links: LMR14203

LMR14203

www.ti.com

SNVS732C –OCTOBER 2011–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision B (April 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 10

Product Folder Links: LMR14203

PACKAGE OPTION ADDENDUM

www.ti.com 28-Feb-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMR14203XMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SJ3B

LMR14203XMKE/NOPB ACTIVE SOT-23-THIN DDC 6 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SJ3B

LMR14203XMKX/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SJ3B

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 28-Feb-2017

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMR14203XMK/NOPB SOT-

23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMR14203XMKE/NOPB SOT-

23-THIN DDC 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMR14203XMKX/NOPB SOT-

23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Mar-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMR14203XMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0

LMR14203XMKE/NOPB SOT-23-THIN DDC 6 250 210.0 185.0 35.0

LMR14203XMKX/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Mar-2017

Pack Materials-Page 2

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