MAX1301BEUP - Maxim Integrated - Datasheet.Directory

General Description

The MAX1300/MAX1301 multirange, low-power, 16-bit,

successive-approximation, analog-to-digital converters

(ADCs) operate from a single +5V supply and achieve

throughput rates up to 115ksps. A separate digital sup-

ply allows digital interfacing with 2.7V to 5.25V systems

using the SPI-/QSPI™-/MICROWIRE®-compatible serial

interface. Partial power-down mode reduces the supply

current to 1.3mA (typ). Full power-down mode reduces

the power-supply current to 1µA (typ).

The MAX1300 provides eight (single-ended) or four (true

differential) analog input channels. The MAX1301 pro-

vides four (single-ended) or two (true differential) analog

input channels. Each analog input channel is indepen-

dently software programmable for seven single-ended

input ranges [0 to (3 x VREF)/2, (-3 x VREF)/2 to 0, 0 to 3

x VREF, -3 x VREF to 0, (±3 x VREF)/4, (±3 x VREF)/2, ±3

x VREF] and three differential input ranges [(±3 x VREF)/2,

±3 x VREF, ±6 x VREF].

An on-chip +4.096V reference offers a small convenient

ADC solution. The MAX1300/MAX1301 also accept an

external reference voltage between 3.800V and 4.136V.

The MAX1300 is available in a 24-pin TSSOP package

and the MAX1301 is available in a 20-pin TSSOP pack-

age. Each device is specified for operation from -40°C to

+85°C.

Applications

●Industrial Control Systems

●Data-Acquisition Systems

●Avionics

●Robotics

Features

●Software-Programmable Input Range for Each Channel

●Single-Ended Input Ranges (VREF = 4.096V)

0 to (3 x VREF)/2, (-3 x VREF)/2 to 0, 0 to 3 x VREF,

-3 x VREF to 0, (±3 x VREF)/4, (±3 x VREF)/2, ±3 x VREF

●Differential Input Ranges

(±3 x VREF)/2, ±3 x VREF, ±6 x VREF

●Eight Single-Ended or Four Differential Analog Inputs

(MAX1300)

●Four Single-Ended or Two Differential Analog Inputs

(MAX1301)

●±16.5V Overvoltage Tolerant Inputs

●Internal or External Reference

●115ksps Maximum Sample Rate

●Single +5V Power Supply

●20-/24-Pin TSSOP Package

Pin Configurations continued at end of data sheet.

19-3575; Rev 3; 12/11

+Denotes lead(Pb)-free/RoHS-compliant package.

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National

Semiconductor Corp.

PART TEMP RANGE PIN-

PACKAGE CHANNELS

MAX1300AEUG+ -40°C to +85°C 24 TSSOP 8

MAX1300BEUG+ -40°C to +85°C 24 TSSOP 8

MAX1301AEUP+ -40°C to +85°C 20 TSSOP 4

MAX1301BEUP+ -40°C to +85°C 20 TSSOP 4

AGND1

AGND2

AVDD2

AGND3CH2

CH1

CH0

AVDD1

TOP VIEW

REF

REFCAP

DVDD

DVDD0CH6

CH5

CH4

CH3

DGND

DGNDO

DOUT

SCLKSSTRB

DIN

CH7

TSSOP

MAX1300

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

Ordering Information

Pin Congurations

EVALUATION KIT AVAILABLE

AVDD1 to AGND1 ...................................................-0.3V to +6V

AVDD2 to AGND2 ...................................................-0.3V to +6V

DVDD to DGND .......................................................-0.3V to +6V

DVDDO to DGNDO .................................................-0.3V to +6V

DVDD to DVDDO ....................................................-0.3V to +6V

DVDD, DVDDO to AVDD1.......................................-0.3V to +6V

AVDD1, DVDD, DVDDO to AVDD2 ......................... -0.3V to +6V

DGND, DGNDO, AGND3, AGND2 to AGND1 .....-0.3V to +0.3V

CS, SCLK, DIN, DOUT, SSTRB to

DGNDO ......................................... -0.3V to (VDVDDO + 0.3V)

CH0–CH7 to AGND1 ........................................ -16.5V to +16.5V

REF, REFCAP to AGND1 ................... -0.3V to (VAVDD1 + 0.3V)

Continuous Current (any pin) ...........................................±50mA

Continuous Power Dissipation (TA = +70°C)

20-Pin TSSOP (derate 11mW/°C above +70°C) .........879mW

24-Pin TSSOP (derate 12.2mW/°C above +70°C) ...... 976mW

Operating Temperature Range ........................... -40°C to +85°C

Junction Temperature .....................................................+150°C

Storage Temperature Range ............................ -65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (Notes 1, 2)

Resolution 16 Bits

Integral Nonlinearity INL MAX130_A ±1.0 ±2 LSB

MAX130_B ±1.0 ±4

Differential Nonlinearity DNL No missing codes -1 +2 LSB

Transition Noise External or internal reference 1 LSBRMS

Offset Error Single-ended inputs Unipolar 0 ±20

mVBipolar -1.0 ±12

Differential inputs (Note 3) Bipolar -2.0 ±20

Channel-to-Channel Gain

Matching Unipolar or bipolar 0.025 %FSR

Channel-to-Channel Offset Error

Matching Unipolar or bipolar 1.0 mV

Offset Temperature Coefcient

Unipolar 3

µV/°CBipolar 1

Fully differential 2

Gain Error

Unipolar ±0.5

%FSRBipolar ±0.8

Fully differential ±1

Gain Temperature Coefcient

Unipolar 2

ppm/°CBipolar 1

Fully differential 2

DYNAMIC SPECIFICATIONS fIN(SINE-WAVE) = 5kHz, VIN = FSR - 0.05dB (Notes 1, 2)

Signal-to-Noise Plus Distortion SINAD

Differential inputs, FSR = ±6 x VREF 91

Single-ended inputs, FSR = ±3 x VREF 89

Single-ended inputs, FSR = (±3 x VREF)/2 86

Single-ended inputs, FSR = (±3 x VREF)/4 80 83

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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│

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Electrical Characteristics

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Signal-to-Noise Ratio SNR

Differential inputs, FSR = ±6 x VREF 91

Single-ended inputs, FSR = ±3 x VREF 89

Single-ended inputs, FSR = (±3 x VREF)/2 86

Single-ended inputs, FSR = (±3 x VREF)/4 83

Total Harmonic Distortion

(Up to the 5th Harmonic) THD -97 dB

Spurious-Free Dynamic Range SFDR 92 99 dB

Aperture Delay tAD Figure 21 15 ns

Aperture Jitter tAJ Figure 21 100 ps

Channel-to-Channel Isolation 105 dB

CONVERSION RATE

Byte-Wide Throughput Rate fSAMPLE

External clock mode, Figure 2 114

kspsExternal acquisition mode, Figure 3 84

Internal clock mode, Figure 4 106

ANALOG INPUTS (CH0–CH3 MAX1301, CH0–CH7 MAX1300, AGND1)

Small-Signal Bandwidth All input ranges, VIN = 100mVP-P (Note 2) 2 MHz

Full-Power Bandwidth All input ranges, VIN = 4VP-P (Note 2) 700 kHz

Input Voltage Range (Table 6) VCH_

R[2:1] = 001 (-3 x VREF)/

(+3 x VREF)/

R[2:1] = 010 (-3 x VREF)/

R[2:1] = 011 0 (+3 x VREF)/

R[2:1] = 100 (-3 x VREF)/

(+3 x VREF)/

R[2:1] = 101 -3 x VREF 0

R[2:1] = 110 0 +3 x VREF

R[2:1] = 111 -3 x VREF +3 x VREF

True-Differential Analog Common-

Mode Voltage Range VCMDR DIF/SGL = 1 (Note 4) -14 +9 V

Common-Mode Rejection

Ratio CMRR DIF/SGL = 1,

input voltage range = (±3 x VREF)/4 75 dB

Input Current ICH_ -3 x VREF < VCH_ < +3 x VREF -1250 +900 µA

Input Capacitance CCH_ 5 pF

Input Resistance RCH_ 17 kΩ

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Electrical Characteristics (continued)

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

INTERNAL REFERENCE (Bypass REFCAP with 0.1µF to AGND1 and REF with 1.0µF to AGND1)

Reference Output Voltage VREF 4.056 4.096 4.136 V

Reference Temperature

Coefcient TCREF ±30 ppm/°C

Reference Short-Circuit Current IREFSC

REF shorted to AGND1 10 mA

REF shorted to AVDD -1

Reference Load Regulation IREF = 0 to 0.5mA 0.1 10 mV

EXTERNAL REFERENCE (REFCAP = AVDD)

Reference Input Voltage Range VREF 3.800 4.136 V

REFCAP Buffer Disable

Threshold VRCTH (Note 5) VAVDD1

- 0.4

VAVDD1

- 0.1 V

Reference Input Current IREF

VREF = +4.096V, external clock mode,

external acquisition mode, internal clock

mode, or partial power-down mode

90 200 µA

VREF = +4.096V, full power-down mode ±0.1 ±10

Reference Input Resistance RREF

External clock mode, external acquisition

mode, internal clock mode, or partial

power-down mode

20 45 kΩ

Full power-down mode 40 MΩ

DIGITAL INPUTS (DIN, SCLK, CS)

Input High Voltage VIH 0.7 x

VDVDDO V

Input Low Voltage VIL 0.3 x

VDVDDO V

Input Hysteresis VHYST 0.2 V

Input Leakage Current IIN VIN = 0 to VDVDDO -10 +10 µA

Input Capacitance CIN 10 pF

DIGITAL OUTPUTS (DOUT, SSTRB)

Output Low Voltage VOL

VDVDDO = 4.75V, ISINK = 10mA 0.4 V

VDVDDO = 2.7V, ISINK = 5mA 0.4

Output High Voltage VOH ISOURCE = 0.5mA VDVDDO

- 0.4 V

DOUT Tri-State Leakage Current IDDO CS = VDVDDO -10 +10 µA

POWER REQUIREMENTS (AVDD1 and AGND1, AVDD2 and AGND2, DVDD and DGND, DVDDO and DGNDO)

Analog Supply Voltage AVDD1 4.75 5.25 V

Digital Supply Voltage DVDD 4.75 5.25 V

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Electrical Characteristics (continued)

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Preamplier Supply Voltage AVDD2 4.75 5.25 V

Digital I/O Supply Voltage DVDDO 2.70 5.25 V

AVDD1 Supply Current IAVDD1

External clock mode,

external acquisition

mode, or internal

clock mode

Internal reference 3 3.5

External reference 2.3 3

DVDD Supply Current IDVDD External clock mode, external acquisition

mode, or internal clock mode 0.8 2 mA

AVDD2 Supply Current IAVDD2 External clock mode, external acquisition

mode, or internal clock mode 13.5 20 mA

DVDDO Supply Current IDVDDO External clock mode, external acquisition

mode, or internal clock mode 0.01 1 mA

Total Supply Current Partial power-down mode 1.3 mA

Full power-down mode 0.5 µA

Power-Supply Rejection Ratio PSRR All analog input ranges ±0.5 LSB

TIMING CHARACTERISTICS (Figures 15 and 16)

SCLK Period tCP

External clock mode 0.272 62

µsExternal acquisition mode 0.228 62

Internal clock mode 0.1

SCLK High Pulse Width (Note 6) tCH

External clock mode 109

External acquisition mode 92

Internal clock mode 40

SCLK Low Pulse Width (Note 6) tCL

External clock mode 109

nsExternal acquisition mode 92

Internal clock mode 40

DIN to SCLK Setup tDS 40 ns

DIN to SCLK Hold tDH 0 ns

SCLK Fall to DOUT Valid tDO 40 ns

CS Fall to DOUT Enable tDV 40 ns

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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│

Electrical Characteristics (continued)

Note 1: Parameter tested at VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V.

Note 2: See definitions in the Parameter Definitions section at the end of the data sheet.

Note 3: Guaranteed by correlation with single-ended measurements.

Note 4: Not production tested. Guaranteed by design.

Note 5: To ensure external reference operation, VREFCAP must exceed (VAVDD1 - 0.1V). To ensure internal reference operation,

VREFCAP must be below (VAVDD1 - 0.4V). Bypassing REFCAP with a 0.1μF or larger capacitor to AGND1 sets VREFCAP ≈

4.096V. The transition point between internal reference mode and external reference mode lies between the REFCAP buffer

disable threshold minimum and maximum values (Figures 17 and 18).

Note 6: The SCLK duty cycle can vary between 40% and 60%, as long as the tCL and tCH timing requirements are met.

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CS Rise to DOUT Disable tTR 40 ns

CS Fall to SCLK Rise Setup tCSS 40 ns

CS High Minimum Pulse Width tCSPW 40 ns

SCLK Fall to CS Rise Hold tCSH 0 ns

SSTRB Rise to CS Fall Setup (Note 4) 40 ns

DOUT Rise/Fall Time CL = 50pF 10 ns

SSTRB Rise/Fall Time CL = 50pF 10 ns

PREAMPLIFIER SUPPLY CURRENT

vs. PREAMPLIFIER SUPPLY VOLTAGE

MAX1300 toc02

VAVDD2 (V)

AVDD2

(mA)

5.155.054.85 4.95

4.75 5.25

EXTERNAL CLOCK MODE

AIN1–AIN7 = AGND2

AIN0 = +FS

TA = +85°C

TA = +25°C

TA = -40°C

DIGITAL SUPPLY CURRENT

vs. DIGITAL SUPPLY VOLTAGE

MAX1300 toc03

VDVDD (V)

DVDD

(mA)

5.155.054.954.85

0.80

0.85

0.90

0.95

0.75

4.75 5.25

EXTERNAL CLOCK MODE

DATA RATE = 115ksps

TA = +85°C

TA = +25°C

TA = -40°C

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1300 toc01

VAVDD1 (V)

AVDD1

(mA)

5.155.054.954.85

2.2

2.3

2.4

2.5

2.6

2.1

4.75 5.25

EXTERNAL CLOCK MODE

TA = +85°C

TA = +25°C

TA = -40°C

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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│

Electrical Characteristics (continued)

Typical Operating Characteristics

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1300 toc05

VAVDD1 (V)

IAVDD1 (mA)

5.155.054.954.85

0.41

0.42

0.43

0.44

0.45

0.46

0.40

4.75 5.25

TA = +85°C

TA = +25°C

TA = -40°C

PARTIAL POWER-DOWN MODE

DIGITAL SUPPLY CURRENT

vs. DIGITAL SUPPLY VOLTAGE

MAX1300 toc07

VDVDD (V)

IDVDD (mA)

5.155.054.954.85

0.111

0.112

0.113

0.114

0.115

0.110

4.75 5.25

TA = +85°C

TA = +25°C

TA = -40°C

PARTIAL POWER-DOWN MODE

DIGITAL I/O SUPPLY CURRENT

vs. DIGITAL I/O SUPPLY VOLTAGE

MAX1300 toc04

VDVDDO (V)

IDVDDO (µA)

5.155.054.954.85

4.75 5.25

TA = +85°C

TA = +25°C

TA = -40°C

EXTERNAL CLOCK MODE

DATA RATE = 115ksps

PREAMPLIFIER SUPPLY CURRENT

vs. PREAMPLIFIER SUPPLY VOLTAGE

MAX1300 toc06

VAVDD2 (V)

IAVDD2 (mA)

5.155.054.954.85

0.12

0.14

0.16

0.18

0.20

0.10

4.75 5.25

TA = +85°C

TA = +25°C

TA = -40°C

PARTIAL POWER-DOWN MODE

AIN1 - AIN7 = AGND2

AIN0 = +FS

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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│

Typical Operating Characteristics (continued)

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)

Note 7: For partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples.

Partial power-down or full power-down modes were entered thereafter. By using this method, the conversion rate was found

by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down

or full power-down modes.

ANALOG SUPPLY CURRENT

vs. CONVERSION RATE

MAX1300 toc09

CONVERSION RATE (ksps)

IAVDD2 (mA)

10080604020

13.86

13.87

13.88

13.89

13.90

13.91

13.92

13.93

13.94

13.95

13.85

0 120

CONTINUOUS EXTERNAL CLOCK MODE

DIGITAL I/O SUPPLY CURRENT

vs. CONVERSION RATE

MAX1300 toc11

CONVERSION RATE (ksps)

IDVDDO (mA)

10080604020

0.02

0.04

0.06

0.08

0.10

0 120

CONTINUOUS EXTERNAL CLOCK MODE

ANALOG SUPPLY CURRENT

vs. CONVERSION RATE

MAX1300 toc08

CONVERSION RATE (ksps)

IAVDD1 (mA)

10080604020

2.33

2.34

2.35

2.36

2.37

2.38

2.39

2.32

0 120

CONTINUOUS EXTERNAL CLOCK MODE

DIGITAL SUPPLY CURRENT

vs. CONVERSION RATE

MAX1300 toc10

CONVERSION RATE (ksps)

IDVDD (mA)

10080604020

0.2

0.4

0.6

0.8

1.0

0 120

CONTINUOUS EXTERNAL CLOCK MODE

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MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

Typical Operating Characteristics (continued)

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)

GAIN DRIFT vs. TEMPERATURE

MAX1300 toc13

TEMPERATURE (°C)

GAIN ERROR (%FSR)

603510-15

-0.08

-0.06

-0.04

-0.02

0.02

0.04

0.06

0.08

0.10

-0.10

-40 85

±3 x VREF BIPOLAR RANGE

(±3 x VREF)/4 BIPOLAR RANGE

COMMON-MODE REJECTION RATIO

vs. FREQUENCY

MAX1300 toc16

FREQUENCY (kHz)

CMRR (dB)

100010010

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

1 10,000

fSAMPLE = 115ksps

±3 x VREF BIPOLAR RANGE

OFFSET DRIFT vs. TEMPERATURE

MAX1300 toc14

TEMPERATURE (°C)

OFFSET ERROR (mV)

603510-15

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

-40 85

±3 x VREF BIPOLAR RANGE

(±3 x VREF)/4 BIPOLAR RANGE

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1300 toc17

DIGITAL OUTPUT CODE

INL (LSB)

52,42839,32113,107 26,214

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

-2.0

0 65,535

fSAMPLE = 115ksps

±3 x VREF BIPOLAR RANGE

FFT AT 5kHz

MAX1300 toc19

FREQUENCY (kHz)

MAGNITUDE (dB)

5040302010

-120

-100

-80

-60

-40

-20

-140

fSAMPLE = 115ksps

fIN(SINE WAVE) = 5kHz

±3 x VREF BIPOLAR RANGE

EXTERNAL REFERENCE INPUT CURRENT

vs. EXTERNAL REFERENCE INPUT VOLTAGE

MAX1300 toc12

EXTERNAL REFERENCE VOLTAGE (V)

EXTERNAL REFERENCE CURRENT (µA)

4.14.03.9

3.8 4.2

CHANNEL-TO-CHANNEL ISOLATION

vs. INPUT FREQUENCY

MAX1300 toc15

FREQUENCY (kHz)

ISOLATION (dB)

100010010

-100

-80

-60

-40

-20

-120

1 10,000

fSAMPLE = 115ksps

±3 x VREF BIPOLAR RANGE

CH0 TO CH2

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1300/01 toc18

DIGITAL OUTPUT CODE

DNL (LSB)

52,42839,32113,107 26,214

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

-2.0

0 65,535

fSAMPLE = 115ksps

±3 x VREF BIPOLAR RANGE

Maxim Integrated

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MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

Typical Operating Characteristics (continued)

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)

SNR, SINAD, ENOB vs. SAMPLE RATE

MAX1300 toc21

SAMPLE RATE (ksps)

SNR, SINAD (dB)

100101

100

0.1 1000

fIN(SINE WAVE) = 5kHz

±3 x VREF BIPOLAR RANGE

ENOB (BITS)

ENOB

SNR, SINAD

-SFDR, THD

vs. ANALOG INPUT FREQUENCY

MAX1300 toc23

FREQUENCY (kHz)

-SFDR, THD (dB)

10010

-100

-80

-60

-40

-20

-120

1 1000

fSAMPLE = 115ksps

±3 x VREF BIPOLAR RANGE

THD

-SFDR

SMALL-SIGNAL BANDWIDTH

MAX1300 toc25

FREQUENCY (kHz)

ATTENUATION (dB)

100010010

-40

-35

-30

-25

-20

-15

-10

-5

-45

1 10,000

SNR, SINAD, ENOB

vs. ANALOG INPUT FREQUENCY

MAX1300 toc20

FREQUENCY (kHz)

SNR, SINAD (dB)

10010

100

1 1000

ENOB (BITS)

ENOB

SINAD

SNR

fSAMPLE = 115ksps

±3 x VREF BIPOLAR RANGE

-SFDR, THD vs. SAMPLE RATE

MAX1300 toc22

SAMPLE RATE (ksps)

-SFDR, THD (dB)

100101

-100

-80

-60

-40

-20

-120

0.1 1000

fIN(SINE WAVE) = 5kHz

±3 x VREF BIPOLAR RANGE

THD

-SFDR

ANALOG INPUT CURRENT

vs. ANALOG INPUT VOLTAGE

MAX1300 toc24

ANALOG INPUT VOLTAGE (V)

ANALOG INPUT CURRENT (mA)

(+3 x VREF)/20(-3 x VREF)/2

-0.6

-0.2

0.2

0.6

1.0

-1.0

-3 x VREF +3 x VREF

ALL MODES

VREF = 4.096V

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Typical Operating Characteristics (continued)

(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty

cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input

range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)

REFERENCE VOLTAGE vs. TIME

MAX1300 toc27

1V/div

4ms/div

NOISE HISTOGRAM

(CODE CENTER)

MAX1300 toc29

CODE

NUMBER OF HITS

32,776

5,000

10,000

15,000

20,000

25,000

30,000

35,000

40,000

32,779

65,534 SAMPLES

32,77732,775 32,778 32,78032,774

FULL-POWER BANDWIDTH

MAX1300 toc26

FREQUENCY (kHz)

ATTENUATION (dB)

100010010

-40

-35

-30

-25

-20

-15

-10

-5

-45

1 10,000

NOISE HISTOGRAM

(CODE EDGE)

MAX1300 toc28

CODE

NUMBER OF HITS

32,787

5,000

10,000

15,000

20,000

25,000

30,000

35,000

32,785 32,789

65,534 SAMPLES

32,786 32,788 32,790

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Typical Operating Characteristics (continued)

PIN NAME FUNCTION

MAX1300 MAX1301

1 2 AVDD1 Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass

AVDD1 to AGND1 with a 0.1µF capacitor.

2 3 CH0 Analog Input Channel 0

3 4 CH1 Analog Input Channel 1

4 5 CH2 Analog Input Channel 2

5 6 CH3 Analog Input Channel 3

6 — CH4 Analog Input Channel 4

7 — CH5 Analog Input Channel 5

8 — CH6 Analog Input Channel 6

9 — CH7 Analog Input Channel 7

10 7 CS

Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the

rising edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK.

When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance.

11 8 DIN Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is

high, transitions on DIN are ignored.

12 9 SSTRB

Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that

data is ready to be read from the device. When operating in external clock mode, SSTRB is

always low. SSTRB does not tri-state, regardless of the state of CS, and therefore requires

a dedicated I/O line.

13 10 SCLK Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT.

When CS is high, transitions on SCLK are ignored.

14 11 DOUT Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK

transition. When CS is high, DOUT is high impedance.

15 12 DGNDO Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.

16 13 DGND Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.

17 14 DVDDO Digital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage.

Bypass DVDDO to DGNDO with a 0.1µF capacitor.

18 15 DVDD Digital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage.

Bypass DVDD to DGND with a 0.1µF capacitor.

19 16 REFCAP

Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD.

For internal reference operation, bypass REFCAP with a 0.01µF capacitor to AGND1

(VREFCAP ≈ 4.096V).

20 17 REF

Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an

external reference voltage from 3.800V to 4.136V to REF. For internal reference operation,

bypassing REF with a 1µF capacitor to AGND1 sets VREF = 4.096V ±1%.

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Pin Description

Detailed Description

The MAX1300/MAX1301 multirange, low-power, 16-bit

successive-approximation ADCs operate from a single

+5V supply and have a separate digital supply allowing

digital interface with 2.7V to 5.25V systems. These 16-bit

ADCs have internal track-and-hold (T/H) circuitry that sup-

ports single-ended and fully differential inputs. For single-

ended conversions, the valid analog input voltage range

spans from -3 x VREF below ground to +3 x VREF above

ground. The maximum allowable differential input voltage

spans from -6 x VREF to +6 x VREF. Data can be con-

verted in a variety of software-programmable channel and

data-acquisition configurations. Microprocessor (μP) con-

trol is made easy through an SPI-/QSPI-/ MICROWIRE-

compatible serial interface.

The MAX1300 has eight single-ended analog input chan-

nels or four differential channels (see the Block Diagram

at the end of the data sheet). The MAX1301 has four

single-ended analog input channels or two differential

channels. Each analog input channel is independently

software programmable for seven single-ended input

ranges [0 to (+3 x VREF)/2, (-3 x VREF)/2 to 0, 0 to +3 x

VREF, -3 x VREF to 0, (±3 x VREF)/4, (±3 x VREF)/2, ±3 x

VREF] and three differential input ranges [(±3 x VREF)/2,

±3 x VREF, ±6 x VREF]. Additionally, all analog input chan-

nels are fault tolerant to ±16.5V. A fault condition on an

idle channel does not affect the conversion result of other

channels.

Figure 1. Typical Application Circuit

PIN NAME FUNCTION

MAX1300 MAX1301

21 18 AGND3 Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to

AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.

22 19 AVDD2 Analog Supply Voltage 2. Connect AVDD2 to a +4.75V to +5.25V power-supply voltage. Bypass

AVDD2 to AGND2 with a 0.1µF capacitor.

23 20 AGND2 Analog Ground 2. This ground carries approximately ve times more current than AGND1.

DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.

24 1 AGND1 Analog Ground 1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.

4–20mA

PLC

ACCELERATION

PRESSURE

TEMPERATURE

WHEATESTONE

1µF

0.1µF AGND2 DGNDOAGND3 DGND

AVDD2 DVDD

AVDD1

0.1µF 0.1µF 0.1µF

5.0V 5.0V 5.0V

MAX1300

CHO

CH1

CH2

CH3

CH4

CH5

CH6

CH7

REF

AGND1

REFCAP

0.1µF

3.3V

MC68HCXX

µC

DVDDO

SCLK

DIN

SSTRB

DOUT

VDD

SCK

I/O

MOSI

I/O

MISO

VSS

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Pin Description (continued)

Power Supplies

To maintain a low-noise environment, the MAX1300

and MAX1301 provide separate power supplies for

each section of circuitry. Table 1 shows the four sepa-

rate power supplies. Achieve optimal performance using

separate AVDD1, AVDD2, DVDD, and DVDDO supplies.

Alternatively, connect AVDD1, AVDD2, and DVDD togeth-

er as close to the device as possible for a convenient

power connection. Connect AGND1, AGND2, AGND3,

DGND, and DGNDO together as close to the device

as possible. Bypass each supply to the corresponding

ground using a 0.1μF capacitor (Table 1). If significant

low-frequency noise is present, add a 10μF capacitor in

parallel with the 0.1μF bypass capacitor.

Converter Operation

The MAX1300/MAX1301 ADCs feature a fully differen-

tial, successive-approximation register (SAR) conversion

technique and an on-chip T/H block to convert voltage

signals into a 16-bit digital result. Both single-ended and

differential configurations are supported with program-

mable unipolar and bipolar signal ranges.

Track-and-Hold Circuitry

The MAX1300/MAX1301 feature a switched-capacitor

T/H architecture that allows the analog input signal to be

stored as charge on sampling capacitors. See Figures 2,

3, and 4 for T/H timing and the sampling instants for each

operating mode. The MAX1300/MAX1301 analog input

circuitry buffers the input signal from the sampling capaci-

tors, resulting in a constant input impedance with varying

input voltage (Figure 5).

Analog Input Circuitry

Select differential or single-ended conversions using the

associated analog input configuration byte (Table 2). The

analog input signal source must be capable of driving the

ADC’s 17kΩ input resistance (Figure 6).

Figure 6 shows the simplified analog input circuit. The ana-

log inputs are ±16.5V fault tolerant and are protected by

back-to-back diodes. The summing junction voltage, VSJ,

is a function of the channel’s input common-mode voltage:

SJ CM

R1 R1

V 2.375V 1 V

R1 R 2 R 1 R 2



 

= × ++ ×



 

 



As a result, the analog input impedance is relatively con-

stant over input voltage as shown in Figure 5.

Table 1. MAX1300/MAX1301 Power Supplies and Bypassing

Table 2. Analog Input Configuration Byte

POWER

SUPPLY/GROUND

SUPPLY VOLTAGE

RANGE (V)

TYPICAL SUPPLY

CURRENT (mA) CIRCUIT SECTION BYPASSING

DVDDO/DGNDO 2.7 to 5.25 0.03 Digital I/O 0.1µF to DGNDO

AVDD2/AGND2 4.75 to 5.25 135 Analog Circuitry 0.1µF to AGND2

AVDD1/AGND1 4.75 to 5.25 3.0 Analog Circuitry 0.1µF to AGND1

DVDD/DGND 4.75 to 5.25 0.8 Digital Control Logic and Memory 0.1µF to DGND

BIT

NUMBER NAME DESCRIPTION

7 START Start Bit. The rst logic 1 after CS goes low denes the beginning of the analog input conguration byte.

6 C2

Channel-Select Bits. SEL[2:0] select the analog input channel to be congured (Tables 4 and 5).5 C1

4 C0

3DIF/SGL

Differential or Single-Ended Conguration Bit. DIF/SGL = 0 congures the selected analog input channel

for single-ended operation. DIF/SGL = 1 congures the channel for differential operation. In single-ended

mode, input voltages are measured between the selected input channel and AGND1, as shown in

Table 4. In differential mode, the input voltages are measured between two input channels, as shown in

Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.

2 R2

Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.1 R1

0 R0

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Single-ended conversions are internally referenced to

AGND1 (Tables 3 and 4). In differential mode, IN+ and

IN- are selected according to Tables 3 and 5. When con-

figuring differential channels, the differential pair follows

the analog configuration byte for the positive channel.

For example, to configure CH2 and CH3 for a ±3 x VREF

differential conversion, set the CH2 analog configuration

byte for a differential conversion with the ±3 x VREF range

(1010 1100). To initiate a conversion for the CH2 and CH3

differential pair, issue the command 1010 0000.

Analog Input Bandwidth

The MAX1300/MAX1301 input-tracking circuitry has a

2MHz small-signal bandwidth. The 2MHz input band-

width makes it possible to digitize high-speed transient

events. Harmonic distortion increases when digitizing

signal frequencies above 15kHz as shown in the THD and

-SFDR vs. Input Frequency plot in the Typical Operating

Characteristics.

Analog Input Range and Fault Tolerance

Figure 7 illustrates the software-selectable single-ended

analog input voltage range that produces a valid digital

output. Each analog input channel can be independently

programmed to one of seven single-ended input ranges

by setting the R[2:0] control bits with DIF/SGL = 0.

Figure 2. External Clock-Mode Conversion (Mode 0)

HIGH

IMPEDANCE

SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

DIN S C2 C1 C0 0 0 0 0

ANALOG INPUT

TRACK AND HOLD*

DOUT

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

BYTE 1 BYTE 2 BYTE 3 BYTE 4

SSTRB

HOLD TRACK HOLD

tACQ

HIGH

IMPEDANCE

*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.

fSAMPLE fSCLK / 32

SAMPLING INSTANT

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Figure 8 illustrates the software-selectable differential

analog input voltage range that produces a valid digital

output. Each analog input differential pair can be inde-

pendently programmed to one of three differential input

ranges by setting the R[2:0] control bits with DIF/SGL = 1.

Regardless of the specified input voltage range and

whether the channel is selected, each analog input is

±16.5V fault tolerant. The analog input fault protection is

active whether the device is unpowered or powered. Any

voltage beyond FSR, but within the ±16.5V fault tolerant

range, applied to an analog input results in a full-scale

output voltage for that channel.

Clamping diodes with breakdown thresholds in excess of

16.5V protect the MAX1300/MAX1301 analog inputs dur-

ing ESD and other transient events (Figure 6). The clamp-

ing diodes do not conduct during normal device opera-

tion, nor do they limit the current during such transients.

When operating in an environment with the potential for

high-energy voltage and/or current transients, protect the

MAX1300/MAX1301 externally.

Figure 3. External Acquisition-Mode Conversion (Mode 1)

SCLK 1234 5 678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

DIN S C2 C1 C0 0 0 0 0

ANALOG INPUT

TRACK AND HOLD* HOLD

DOUT

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

BYTE 1 BYTE 2 BYTE 3 BYTE 4

SSTRB

INTCLK** 123 14 15 16 17

TRACK HOLD

tACQ

100ns to 400ns

fINTCLK 4.5MHz

fSAMPLE fSCLK / 32 + fINTCLK / 17

*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.

**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.

SAMPLING INSTANT

HIGH IMPEDANCE

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Figure 4. Internal Clock-Mode Conversion (Mode 2)

Figure 5. Analog Input Current vs. Input Voltage Figure 6. Simplified Analog Input Circuit

SCLK 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24

DIN S C2 C1 C0 0 0 0 0

ANALOG INPUT

TRACK AND HOLD* TRACK

DOUT

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

BYTE 1 BYTE 2 BYTE 3

SSTRB

INTCLK** 1 2 3 25 26 27 28

9 10 11 12 13 14 15 16

10 11 12 13 14

HOLD HOLD

tACQ

100ns to 400ns

fINTCLK 4.5MHz

fSAMPLE fSCLK / 24 + fINTCLK / 28

*TRACK AND HOLD TIMING IS CONTROLLED BY INTCLK, AND IS NOT ACCESSIBLE TO THE USER.

**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.

SAMPLING INSTANT

HIGH IMPEDANCE

ANALOG INPUT VOLTAGE (V)

ANALOG INPUT CURRENT (mA)

-0.6

-0.2

0.2

0.6

1.0

-1.0

ALL MODES

(+3 x VREF)/2

(-3 x VREF)/2

-3 x VREF +3 x VREF

MAX1300

MAX1301

VSJ

*RSOURCE

ANALOG

SIGNAL

SOURCE

VSJ

*RSOURCE

ANALOG

SIGNAL

SOURCE

IN_+

*MINIMIZE RSOURCE TO AVOID GAIN ERROR AND DISTORTION.

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Differential Common-Mode Range

The MAX1300/MAX1301 differential common-mode

range (VCMDR) must remain within -14V to +10V to obtain

valid conversion results. The differential common-mode

range is defined as:

( ) ( )

CMDR

CH_ CH_

−++

In addition to the common-mode input voltage limitations,

each individual analog input must be limited to ±16.5V

with respect to AGND1.

The range-select bits R[2:0] in the analog input con-

figuration bytes determine the full-scale range for the

corresponding channel (Tables 2 and 6). Figures 9, 10,

and 11 show the valid analog input voltage ranges for

the MAX1300/MAX1301 when operating with FSR = (±3

x VREF)/2, FSR = ±3 x VREF, and FSR = ±6 x VREF,

respectively. The shaded area contains the valid com-

mon-mode voltage ranges that support the entire FSR.

Table 3. Input Data Word Formats

Table 4. Channel Selection in Single-Ended Mode (DIF/SGL = 0)

Table 5. Channel Selection in True-Differential Mode (DIF/SGL = 1)

OPERATION

DATA BIT

(START) D6 D5 D4 D3 D2 D1 D0

Conversion-Start Byte

(Tables 4 and 5) 1 C2 C1 C0 0 0 0 0

Analog-Input Conguration Byte

(Table 2) 1 C2 C1 C0 DIF/SGL R2 R1 R0

Mode-Control Byte

(Table 7) 1 M2 M1 M0 1 0 0 0

CHANNEL-SELECT BIT CHANNEL

C2 C1 C0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND1

0 0 0 + -

0 0 1 + -

0 1 0 + -

0 1 1 + -

1 0 0 + -

1 0 1 + -

1 1 0 + -

1 1 1 + -

CHANNEL-SELECT BIT CHANNEL

C2 C1 C0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND1

0 0 0 + -

0 0 1 RESERVED

0 1 0 + -

0 1 1 RESERVED

1 0 0 + -

1 0 1 RESERVED

1 1 0 + -

1 1 1 RESERVED

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Digital Interface

The MAX1300/MAX1301 feature a serial interface that

is compatible with SPI/QSPI and MICROWIRE devices.

DIN, DOUT, SCLK, CS, and SSTRB facilitate bidirectional

communication between the MAX1300/MAX1301 and

the master at SCLK rates up to 10MHz (internal clock

mode, mode 2), 3.67MHz (external clock mode, mode

0), or 4.39MHz (external acquisition mode, mode 1). The

master, typically a microcontroller, should use the CPOL =

0, CPHA = 0, SPI transfer format, as shown in the timing

diagrams of Figures 2, 3, and 4.

The digital interface is used to:

• Select single-ended or true-differential input channel

configurations

• Select the unipolar or bipolar input range

• Select the mode of operation:

External clock (mode 0)

External acquisition (mode 1)

Internal clock (mode 2)

Reset (mode 4)

Partial power-down (mode 6)

Full power-down (mode 7)

• Initiate conversions and read results

Chip Select (CS)

CS enables communication with the MAX1300/MAX1301.

When CS is low, data is clocked into the device from DIN

on the rising edge of SCLK and data is clocked out of

DOUT on the falling edge of SCLK. When CS is high,

activity on SCLK and DIN is ignored and DOUT is high

impedance allowing DOUT to be shared with other periph-

erals. SSTRB is never high impedance and therefore can-

not be shared with other peripherals.

Serial Strobe Output (SSTRB)

As shown in Figures 3 and 4, the SSTRB transitions high

to indicate that the ADC has completed a conversion

and results are ready to be read by the master. SSTRB

remains low in the external clock mode (Figure 2) and

consequently may be left unconnected. SSTRB is driven

high or low regardless of the state of CS, therefore SSTRB

cannot be shared with other peripherals.

Figure 7. Single-Ended Input Voltage Ranges Figure 8. Differential Input Voltage Ranges

001

010

011

100

101

110

111

(-3 x VREF)/2

-3 x VREF

+3 x VREF

(+3 x VREF)/2

EACH INPUT IS FAULT TOLERANT TO 16.5V.

VREF = 4.096V.

(CH_) - AGND1 (V)

INPUT RANGE SELECTION BITS, R[2:0]

FSR = (3 x VREF)/2

FSR = 6V

FSR = (3 x VREF)/2

FSR = 3 x VREF

FSR = 6 x VREF

001

010

011

100

101

110

111

-3 x VREF

-6 x VREF

+6 x VREF

+3 x VREF

EACH INPUT IS FAULT TOLERANT TO 16.5V.

VREF = 4.096V.

(CH_+) - (CH_-) (V)

INPUT RANGE SELECTION BITS, R[2:0]

FSR = 3 x VREF

FSR = 6 x VREF

FSR = 12 x VREF

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Table 6. Range-Select Bits

*Conversion-Start Byte (see Table 3).

**Mode-Control Byte (see Table 3).

DIF/SGL R2 R1 R0 MODE TRANSFER FUNCTION

0 0 0 0 No Range Change* —

0 0 0 1

Single-Ended

Bipolar (-3 x VREF)/4 to (+3 x VREF)/4

Full-Scale Range (FSR) = (3 x VREF)/2

Figure 12

0 0 1 0

Single-Ended

Unipolar (-3 x VREF)/2 to 0

FSR = (3 x VREF)/2

Figure 13

0 0 1 1

Single-Ended

Unipolar 0 to (+3 x VREF)/2

FSR = (+3 x VREF)/2

Figure 14

0 1 0 0

Single-Ended

Bipolar (-3 x VREF)/2 to (+3 x VREF)/2

FSR = 3 x VREF

Figure 12

0 1 0 1

Single-Ended

Unipolar -3 x VREF to 0

FSR = 3 x VREF

Figure 13

0 1 1 0

Single-Ended

Unipolar 0 to +3 x VREF

FSR = 3 x VREF

Figure 14

0 1 1 1

DEFAULT SETTING

Single-Ended

Bipolar -3 x VREF to +3 x VREF

FSR = 6 x VREF

Figure 12

1 0 0 0 No Range Change** —

1 0 0 1

Differential

Bipolar (-3 x VREF)/2 to (+3 x VREF)/2

FSR = 3 x VREF

Figure 12

1 0 1 0 Reserved —

1 0 1 1 Reserved —

1 1 0 0

Differential

Bipolar -3 x VREF to +3 x VREF

FSR = 6 x VREF

Figure 12

1 1 0 1 Reserved —

1 1 1 0 Reserved —

1 1 1 1

Differential

Bipolar -6 x VREF to +6 x VREF

FSR = 12 x VREF

Figure 12

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Start Bit

Communication with the MAX1300/MAX1301 is accom-

plished using the three input data word formats shown in

Table 3. Each input data word begins with a start bit. The

start bit is defined as the first high bit clocked into DIN with

CS low when any of the following are true:

• Data conversion is not in process and all data from the

previous conversion has clocked out of DOUT.

• The device is configured for operation in external clock

mode (mode 0) and previous conversion-result bits

B15–B3 have clocked out of DOUT.

• The device is configured for operation in external

acquisition mode (mode 1) and previous conversion-

result bits B15–B7 have clocked out of DOUT.

• The device is configured for operation in internal clock

mode, (mode 2) and previous conversion result bits

B15–B4 have clocked out of DOUT.

Output Data Format

Output data is clocked out of DOUT in offset binary format

on the falling edge of SCLK, MSB first (B15). For output

binary codes, see the Transfer Function section and

Figures 12, 13, and 14.

Conguring Analog Inputs

Each analog input has two configurable parameters:

• Single-ended or true-differential input

• Input voltage range

These parameters are configured using the analog input

configuration byte as shown in Table 2. Each analog input

has a dedicated register to store its input configuration

information. The timing diagram of Figure 15 shows how

to write to the analog input configuration registers. Figure

16 shows DOUT and SSTRB timing.

Transfer Function

An ADC’s transfer function defines the relationship

between the analog input voltage and the digital out-

put code. Figures 12, 13, and 14 show the MAX1300/

MAX1301 transfer functions. The transfer function is

determined by the following characteristics:

• Analog input voltage range

• Single-ended or differential configuration

• Reference voltage

The axes of an ADC transfer function are typically in least

significant bits (LSBs). For the MAX1300/MAX1301, an

LSB is calculated using the following equation:

REF

FSR V

1 L S B

2 4.096V

=×

where N is the number of bits (N = 16) and FSR is the

full-scale range (see Figures 7 and 8).

Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = 3 x VREF)

Figure 11. Common-Mode Voltage vs. Input Voltage (FSR = 12 x VREF)

Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 6 x VREF)

INPUT VOLTAGE (V)

COMMON-MODE VOLTAGE (V)

1260-6-12

-12

-8

-4

-16

-18 18

INPUT VOLTAGE (V)

COMMON-MODE VOLTAGE (V)

1260-6-12

-12

-8

-4

-16

-18 18

INPUT VOLTAGE (V)

COMMON-MODE VOLTAGE (V)

1260-6-12

-12

-8

-4

-16

-18 18

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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Mode Control

The MAX1300/MAX1301 contain one byte-wide mode-

control register. The timing diagram of Figure 15 shows

how to use the mode-control byte, and the mode-control

byte format is shown in Table 7. The mode-control byte is

used to select the conversion method and to control the

power modes of the MAX1300/MAX1301.

Selecting the Conversion Method

The conversion method is selected using the mode-con-

trol byte (see the Mode Control section), and the conver-

sion is initiated using a conversion-start command (Table

3, and Figures 2, 3, and 4).The MAX1300/MAX1301

convert analog signals to digital data using one of three

methods:

• External Clock Mode, Mode 0 (Figure 2)

• Highest maximum throughput (see the Electrical

Characteristics table)

• User controls the sample instant

• CS remains low during the conversion

•

User supplies SCLK throughout the ADC conversion

and reads data at DOUT

• External Acquisition Mode, Mode 1 (Figure 3)

• Lowest maximum throughput (see the Electrical

Characteristics table)

• User controls the sample instant

• User supplies two bytes of SCLK, then drives

CS high to relieve processor load while the ADC

converts

• After SSTRB transitions high, the user supplies

two bytes of SCLK and reads data at DOUT

• Internal Clock Mode, Mode 2 (Figure 4)

• High maximum throughput (see the Electrical

Characteristics table)

Figure 12. Ideal Bipolar Transfer Function, Single-Ended or

Differential Input

Figure 14. Ideal Unipolar Transfer Function, Single-Ended

Input, 0 to +FSR

Figure 13. Ideal Unipolar Transfer Function, Single-Ended

Input, -FSR to 0

1 LSB = FSR x VREF

65,536 x 4.096V

BINARY OUTPUT CODE (LSB [hex])

FFFF

FFFE

FFFD

8001

8000

7FFF

0003

0002

0001

0000

FSR

-32,768 -32,766 0 +32,765 +32,767

INPUT VOLTAGE (LSB [DECIMAL])

AGND1 (DIF/SGL = 0)

OV (DIF/SGL = 1)

FSR

-1 +1

1 LSB = FSR x VREF

65,536 x 4.096V

BINARY OUTPUT CODE (LSB [hex])

FFFF

FFFE

FFFD

8001

8000

7FFF

0003

0002

0001

0000

FSR

0 1 2 3 32,768 65,533 65,535

INPUT VOLTAGE (LSB [DECIMAL])

(AGND1)

FSR

1 LSB = FSR x VREF

65,536 x 4.096V

BINARY OUTPUT CODE (LSB [hex])

FFFF

FFFE

FFFD

8001

8000

7FFF

0003

0002

0001

0000

FSR

0 1 2 3 32,768 65,533 65,535

INPUT VOLTAGE (LSB [DECIMAL])

(AGND1)

FSR

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

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• The internal clock controls the sampling instant

• User supplies one byte of SCLK, then drives CS high

to relieve processor load while the ADC converts

• After SSTRB transitions high, the user supplies two

bytes of SCLK and reads data at DOUT

External Clock Mode (Mode 0)

The MAX1300/MAX1301’s fastest maximum throughput

rate is achieved operating in external clock mode. SCLK

controls both the acquisition and conversion of the analog

signal, facilitating precise control over when the analog

signal is captured. The analog input sampling instant is at

the falling edge of the 14th SCLK (Figure 2).

Since SCLK drives the conversion in external clock mode,

the SCLK frequency should remain constant while the

conversion is clocked. The minimum SCLK frequency

prevents droop in the internal sampling capacitor voltages

during conversion.

SSTRB remains low in the external clock mode, and as a

result may be left unconnected if the MAX1300/ MAX1301

will always be used in the external clock mode.

Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing

Figure 16. DOUT and SSTRB Timing

Table 7. Mode-Control Byte

BIT NUMBER BIT NAME DESCRIPTION

7 START Start Bit. The rst logic 1 after CS goes low denes the beginning of the mode-control byte.

6 M2

Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.5 M1

4 M0

3 1 Bit 3 must be a logic 1 for the mode-control byte.

2 0 Bit 2 must be a logic 0 for the mode-control byte.

1 0 Bit 1 must be a logic 0 for the mode-control byte.

0 0 Bit 0 must be a logic 0 for the mode-control byte.

SCLK

DIN

DOUT

1 8

START SEL2 SEL1 SEL0 R2 R1 R0

DIF/SGL

tCL

tCP

tCH

tDV

tCSS

tDS tDH

tCSH

tCSPW

tTR

1 8

START M2 M1 M0 1 0 0 0

ANALOG INPUT CONFIGURATION BYTE MODE CONTROL BYTE

HIGH

IMPEDANCE

HIGH

IMPEDANCE

HIGH

IMPEDANCE

SCLK

DOUT

tCSS

SSTRB

tSSCS

MSB

tDO

NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).

HIGH

IMPEDANCE

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External Acquisition Mode (Mode 1)

The slowest maximum throughput rate is achieved with

the external acquisition method. SCLK controls the acqui-

sition of the analog signal in external acquisition mode,

facilitating precise control over when the analog signal is

captured. The internal clock controls the conversion of the

analog input voltage. The analog input sampling instant is

at the falling edge of the 16th SCLK (Figure 3).

For the external acquisition mode, CS must remain low

for the first 15 clock cycles and the rise on or after the

falling edge of the 16th SCLK cycle as shown in Figure 3.

For optimal performance, idle DIN and SCLK during the

conversion. With careful board layout, transitions at DIN

and SCLK during the conversion have a minimal impact

on the conversion result.

After the conversion is complete, SSTRB asserts high

and CS can be brought low to read the conversion result.

SSTRB returns low on the rising SCLK edge of the sub-

sequent start bit.

Internal Clock Mode (Mode 2)

In internal clock mode, the internal clock controls both

acquisition and conversion of the analog signal. The inter-

nal clock starts approximately 100ns to 400ns after the

falling edge of the eighth SCLK and has a rate of about

4.5MHz. The analog input sampling instant occurs at the

falling edge of the 11th internal clock signal (Figure 4).

For the internal clock mode, CS must remain low for the

first seven SCLK cycles and then rise on or after the fall-

ing edge of the eighth SCLK cycle. After the conversion

is complete, SSTRB asserts high and CS can be brought

low to read the conversion result. SSTRB returns low on

the rising SCLK edge of the subsequent start bit.

Reset (Mode 4)

As shown in Table 8, set M[2:0] = 100 to reset the

MAX1300/MAX1301 to its default conditions. The default

conditions are full power operation with each channel

configured for ±3 x VREF, bipolar, single-ended conver-

sions using external clock mode (mode 0).

Partial Power-Down Mode (Mode 6)

As shown in Table 8, when M[2:0] = 110, the device enters

partial power-down mode. In partial power-down, all ana-

log portions of the device are powered down except for

the reference voltage generator and bias supplies.

To exit partial power-down, change the mode by issuing

one of the following mode-control bytes (see the Mode

Control section):

• External-Clock-Mode Control Byte

• External-Acquisition-Mode Control Byte

• Internal-Clock-Mode Control Byte

• Reset Byte

• Full Power-Down-Mode Control Byte

This prevents the MAX1300/MAX1301 from inadvertently

exiting partial power-down mode because of a CS glitch

in a noisy digital environment.

Full Power-Down Mode (Mode 7)

When M[2:0] = 111, the device enters full power-down

mode and the total supply current falls to 1μA (typ). In full

power-down, all analog portions of the device are powered

down. When using the internal reference, upon exiting full

power-down mode, allow 10ms for the internal reference

voltage to stabilize prior to initiating a conversion.

To exit full power-down, change the mode by issuing one

of the following mode-control bytes (see the Mode Control

section):

• External-Clock-Mode Control Byte

Table 8. Mode-Control Bits M[2:0]

M2 M1 M0 MODE

0 0 0 External Clock (DEFAULT)

0 0 1 External Acquisition

0 1 0 Internal Clock

0 1 1 Reserved

1 0 0 Reset

1 0 1 Reserved

1 1 0 Partial Power-Down

1 1 1 Full Power-Down

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• External-Acquisition-Mode Control Byte

• Internal-Clock-Mode Control Byte

• Reset Byte

• Partial Power-Down-Mode Control Byte

This prevents the MAX1300/MAX1301 from inadvertently

exiting full power-down mode because of a CS glitch in a

noisy digital environment.

Power-On Reset

The MAX1300/MAX1301 power up in normal operation

configured for external clock mode with all circuitry active

(Tables 7 and 8). Each analog input channel (CH0–CH7) is

set for single-ended conversions with a ±3 x VREF bipolar

input range (Table 6).

Allow the power supplies to stabilize after power-up. Do not

initiate any conversions until the power supplies have sta-

bilized. Additionally, allow 10ms for the internal reference to

stabilize when CREF = 1.0μF and CREFCAP = 0.1μF. Larger

reference capacitors require longer stabilization times.

Internal or External Reference

The MAX1300/MAX1301 operate with either an internal

or external reference. The reference voltage impacts the

ADC’s FSR (Figures 12, 13, and 14). An external refer-

ence is recommended if more accuracy is required than

the internal reference provides, and/or multiple converters

require the same reference voltage.

Internal Reference

The MAX1300/MAX1301 contain an internal 4.096V

bandgap reference. This bandgap reference is connected

to REFCAP through a nominal 5kΩ resistor (Figure 17).

The voltage at REFCAP is buffered creating 4.096V at

REF. When using the internal reference, bypass REFCAP

with a 0.1μF or greater capacitor to AGND1 and bypass

REF with a 1.0μF or greater capacitor to AGND1.

External Reference

For external reference operation, disable the internal

reference and reference buffer by connecting REFCAP

to AVDD1. With AVDD1 connected to REFCAP, REF

becomes a high-impedance input and accepts an external

reference voltage. The MAX1300/MAX1301 can accept

an external reference voltage of 4.096V or less. However,

to meet all of the electrical characteristic specifications,

VREF must be > 38V. The MAX1300/ MAX1301 external

reference current varies depending on the applied refer-

ence voltage and the operating mode (see the External

Reference Input Current vs. External Reference Input

Voltage graph in the Typical Operating Characteristics).

Applications Information

Noise Reduction

Additional samples can be taken and averaged (oversam-

pling) to remove the effect of transition noise on conver-

sion results. The square root of the number of samples

determines the improvement in performance. For example,

with 2/3LSBRMS (4LSBP-P) transition noise, 16 (42 = 16)

samples must be taken to reduce the noise to 1LSBP-P.

Interface with 0 to 10V Signals

In industrial control applications, 0 to 10V signaling is

common. For 0 to 10V applications, configure the selected

MAX1300/MAX1301 input channel for the single-ended 0

to 3 x VREF input range (R[2:0] = 110, Table 6). The 0 to 3

x VREF range accommodates 0 to 10V where the signals

saturate at approximately 3 x VREF if out of range.

Interface with 4–20mA Signals

Figure 19 illustrates a simple interface between the

MAX1300/MAX1301 and a 4–20mA signal. 4–20mA sig-

naling can be used as a binary switch (4mA represents

a logic-low signal, 20mA represents a logic-high signal),

or for precision communication where currents between

4mA and 20mA represent intermediate analog data. For

binary switch applications, connect the 4–20mA signal

to the MAX1300/MAX1301 with a resistor to ground. For

example, a 250Ω resistor converts the 4–20mA signal to

a 1V to 5V signal. Adjust the resistor value so the parallel

combination of the resistor and the MAX1300/MAX1301

source impedance is 250Ω. In this application, select the

single-ended 0 to (3 x VREF)/2 range (R[2:0] = 011, Table

6). For applications that require precision measurements

of continuous analog currents between 4mA and 20mA,

use a buffer to prevent the MAX1300/MAX1301 input from

diverting current from the 4–20mA signal.

Figure 17. Internal Reference Operation

REF

REFCAP

AGND1

4.096V

BANDGAP

REFERENCE

5kΩ

SAR

ADC REF

4.096V

1.0µF

0.1µF

VRCTH

MAX1300

MAX1301

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Bridge Application

The MAX1300/MAX1301 convert 1kHz signals more

accurately than a similar sigma-delta converter that might

be considered in bridge applications. The input impedance

of the MAX1300, in combination with the current-limiting

resistors, can affect the gain of the MAX1300. In many

applications this error is acceptable, but for applications

that cannot tolerate this error, the MAX1300 inputs can be

buffered (Figure 20). Connect the bridge to a low-offset

differential amplifier and then the true-differential inputs of

the MAX1300/MAX1301. Larger excitation voltages take

advantage of more of the (±3 x VREF)/4 differential input

voltage range. Select an input voltage range that matches

the amplifier output. Be aware of the amplifier offset and

offset-drift errors when selecting an appropriate amplifier.

Dynamically Adjusting the Input Range

Software control of each channel’s analog input range

and the unipolar endpoint overlap specification make it

possible for the user to change the input range for a chan-

nel dynamically and improve performance in some appli-

cations. Changing the input range results in a small LSB

step-size over a wider output voltage range. For example,

by switching between a (-3 x VREF)/2 to 0V range and a 0

to (+3 x VREF)/2 range, an LSB is

REF REF

( 3 V )/2 V

65,536 4.096

+× ×

but the input voltage range effectively spans from (-3 x

VREF)/2 to (+3 x VREF)/2 (FSR = 3 x VREF).

Layout, Grounding, and Bypassing

Careful PCB layout is essential for best system perfor-

mance. Boards should have separate analog and digital

ground planes and ensure that digital and analog signals

are separated from each other. Do not run analog and

digital (especially clock) lines parallel to one another, or

digital lines underneath the device package.

Figure 1 shows the recommended system ground con-

nections. Establish an analog ground point at AGND1

and a digital ground point at DGND. Connect all analog

grounds to the star analog ground. Connect the digital

grounds to the star digital ground. Connect the digital

ground plane to the analog ground plane at one point.

For lowest noise operation, make the ground return to the

star ground’s power-supply low impedance and as short

as possible.

High-frequency noise in the AVDD1 power supply

degrades the ADC’s high-speed comparator performance.

Bypass AVDD1 to AGND1 with a 0.1μF ceramic surface-

mount capacitor. Make bypass capacitor connections as

short as possible.

Parameter Denitions

Integral Nonlinearity (INL)

INL is the deviation of the values on an actual transfer

function from a straight line. This straight line is either a

best straight-line fit or a line drawn between the endpoints

of the transfer function once offset and gain errors have

been nullified. The MAX1300/MAX1301 INL is measured

using the endpoint method.

Figure 18. External Reference Operation

REF

REFCAP

AGND1

4.096V

BANDGAP

REFERENCE

5kΩ

SAR

ADC REF

4.096V

1.0µF

VRCTH

MAX1300

MAX1301

AVDD1

MAX6341

V+

1.0µF

OUT

GND

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Differential Nonlinearity (DNL)

DNL is the difference between an actual step width and

the ideal value of 1 LSB. A DNL error specification of

greater than -1 LSB guarantees no missing codes and a

monotonic transfer function.

Transition Noise

Transition noise is the amount of noise that appears at a

code transition on the ADC transfer function. Conversions

performed with the analog input right at the code transi-

tion can result in code flickering in the LSBs.

Channel-to-Channel Isolation

Channel-to-channel isolation indicates how well each

analog input is isolated from the others. The channel-

to-channel isolation for these devices is measured by

applying a near full-scale magnitude 5kHz sine wave

to the selected analog input channel while applying an

equal magnitude sine wave of a different frequency to all

unselected channels. An FFT of the selected channel out-

put is used to determine the ratio of the magnitudes of the

signal applied to the unselected channels and the 5kHz

signal applied to the selected analog input channel. This

ratio is reported, in dB, as channel-to-channel isolation.

Figure 19. 4–20mA Application

Figure 20. Bridge Application

MAX1300

250Ω

4–20mA INPUT

250Ω

4–20mA INPUT

CH0

CH8

µC

MAX1300

MAX1301

CH0

REF

µP

CH1

LOW-OFFSET

DIFFERENTIAL

AMPLIFIER

BRIDGE

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Unipolar Offset Error

-FSR to 0V

When a zero-scale analog input voltage is applied to the

converter inputs, the digital output is all ones (0xFFFF).

Ideally, the transition from 0xFFFF to 0xFFFE occurs at

AGND1 - 0.5 LSB. Unipolar offset error is the amount

of deviation between the measured zero-scale transition

point and the ideal zero-scale transition point, with all

untested channels grounded.

0V to +FSR

When a zero-scale analog input voltage is applied to the

converter inputs, the digital output is all zeros (0x0000).

Ideally, the transition from 0x0000 to 0x0001 occurs at

AGND1 + 0.5 LSB. Unipolar offset error is the amount

of deviation between the measured zero-scale transition

point and the ideal zero-scale transition point, with all

untested channels grounded.

Bipolar Offset Error

When a zero-scale analog input voltage is applied to the

converter inputs, the digital output is a one followed by

all zeros (0x8000). Ideally, the transition from 0x7FFF to

0x8000 occurs at (2N-1 - 0.5)LSB. Bipolar offset error is

the amount of deviation between the measured midscale

transition point and the ideal midscale transition point,

with untested channels grounded.

Gain Error

When a positive full-scale voltage is applied to the con-

verter inputs, the digital output is all ones (0xFFFF). The

transition from 0xFFFE to 0xFFFF occurs at 1.5 LSB

below full scale. Gain error is the amount of deviation

between the measured full-scale transition point and

the ideal full-scale transition point with the offset error

removed and all untested channels grounded.

Unipolar Endpoint Overlap

Unipolar endpoint overlap is the change in offset when

switching between complementary input voltage ranges.

For example, the difference between the voltage that

results in a 0xFFFF output in the -3 x VREF/2 to 0V input

voltage range and the voltage that results in a 0x0000

output in the 0 to +3 x VREF/2 input voltage range is the

unipolar endpoint overlap. The unipolar endpoint overlap

is positive for the MAX1300/MAX1301, preventing loss of

signal or a dead zone when switching between adjacent

analog input voltage ranges.

Small-Signal Bandwidth

A 100mVP-P sine wave is applied to the ADC, and the

input frequency is then swept up to the point where

the amplitude of the digitized conversion result has

decreased by -3dB.

Full-Power Bandwidth

A 95% of full-scale sine wave is applied to the ADC, and

the input frequency is then swept up to the point where

the amplitude of the digitized conversion result has

decreased by -3dB.

Common-Mode Rejection Ratio (CMRR)

CMRR is the ability of a device to reject a signal that is

“common” to or applied to both input terminals. The com-

mon-mode signal can be either an AC or a DC signal or

a combination of the two. CMR is expressed in decibels.

Common-mode rejection ratio is the ratio of the differen-

tial signal gain to the common-mode signal gain. CMRR

applies only to differential operation.

Power-Supply Rejection Ratio (PSRR)

PSRR is the ratio of the output-voltage shift to the

power-supply-voltage shift for a fixed input voltage. For

the MAX1300/MAX1301, AVDD1 can vary from 4.75V to

5.25V. PSRR is expressed in decibels and is calculated

using the following equation:

OUT OUT

5.25V 4.75V

PSRR[dB] 20 log V (5.25V) V (4.75V)

−



= ×





For the MAX1300/MAX1301, PSRR is tested in bipolar

operation with the analog inputs grounded.

Aperture Jitter

Aperture jitter, tAJ, is the statistical distribution of the

variation in the sampling instant (Figure 21).

Aperture Delay

Aperture delay, tAD, is the time from the falling edge of

SCLK to the sampling instant (Figure 21).

Signal-to-Noise Ratio (SNR)

SNR is computed by taking the ratio of the RMS signal to

the RMS noise. RMS noise includes all spectral compo-

nents to the Nyquist frequency excluding the fundamen-

tal, the first five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS signal

to the RMS noise plus distortion. RMS noise plus dis-

tortion includes all spectral components to the Nyquist

frequency excluding the fundamental and the DC offset.

RMS

Signal

SINAD(dB) 20 log Noise



= ×





MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

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Effective Number of Bits (ENOB)

ENOB indicates the global accuracy of an ADC at a

specific input frequency and sampling rate. With an input

range equal to the ADC’s full-scale range, calculate the

ENOB as follows:

SINAD 1.76

ENOB 6.02

−



=



Total Harmonic Distortion (THD)

For the MAX1300/MAX1301, THD is the ratio of the RMS

sum of the input signal’s first four harmonic components

to the fundamental itself. This is expressed as:

2222

2345

V V V V

THD 20 log V



+++



= ×





where V1 is the fundamental amplitude, and V2 through V5

are the amplitudes of the 2nd- through 5th-order harmonic

components.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of RMS amplitude of the fundamental

(maximum signal component) to the RMS value of the

next-largest spectral component.

Figure 21. Aperture Diagram

tAD

tAJ

INTCLK

(MODE 2)

ANALOG INPUT

TRACK AND HOLD TRACK HOLD

SAMPLE INSTANT

SCLK

(MODE 0) 13 14 15

SCLK

(MODE 1) 15 16

10 11 12

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

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PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

20 TSSOP U20+2 21-0066 90-0116

24 TSSOP U24+1 90-0118

MAX1300

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

AGND1

ANALOG

INPUT MUX

AND

MULTIRANGE

CIRCUITRY

PGA

AGND2

AVDD2

4.096V

BANDGAP

REFERENCE

5kΩ

REF

REFCAP

REF

CONTROL LOGIC AND REGISTERS

FIFO

CLOCK

OUT

SAR

ADC

SERIAL I/O

AGND2

AVDD2

AGND3

AVDD1

DGND

DVDD

DGNDO

SCLK

DOUT

SSTRB

DIN

DVDDO

AGND2

AVDD2

AGND3

REFCH1

CH0

AVDD1

AGND1

REFCAP

DVDD

DVDDO

DGNDDIN

CH3

CH2

DGNDO

DOUTSCLK

SSTRB

MAX1301

TSSOP

TOP VIEW

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Block Diagram

Pin Congurations (continued)

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

Chip Information

PROCESS: BiCMOS

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES CHANGED

0 11/06 Initial release 1

2 6/10 Updated Electrical Characteristics tables, TOCs to optimize yield. 1–10, 13, 14, 15, 17–21,

24, 25, 26, 28, 31

3 12/11 Released MAX1300 and updated the Electrical Characteristics table. 1, 2

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

│

MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs,

Serial 16-Bit ADCs

Revision History

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