SN74AHC1G04-Q1
SINGLE INVERTER GATE
SCLS540A − AUGUST 2003 − REVISED APRIL 2008
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DQualified for Automotive Applications
DESD Protection Exceeds JESD 22
− 1500-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
DOperating Range of 2 V to 5.5 V
D±8-mA Output Drive at 5 V
DLatch-Up Performance Exceeds 250 mA Per
JESD 17
description/ordering information
The SN74AHC1G04 contains one inverter gate. The
device performs the Boolean function Y = A.
ORDERING INFORMATION{
TAPACKAGE‡ORDERABLE
PART NUMBER
TOP-SIDE
MARKING§
40°C to 125°C
SOT (SOT-23) − DBV Reel of 3000 SN74AHC1G04QDBVRQ1 A04_
−40°C to 125°CSOT (SC-70) − DCK Reel of 3000 SN74AHC1G04QDCKRQ1 AC_
†For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
‡Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§The actual top-side marking has one additional character that designates the wafer fab / assembly site.
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H L
L H
logic diagram (positive logic)
AY
24
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
NC
A
GND
VCC
Y
NC − No internal connection
Copyright 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74AHC1G04-Q1
SINGLE INVERTER GATE
SCLS540A − AUGUST 2003 − REVISED APRIL 2008
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DBV package 206°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 252°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 3 V 2.1 V
VIH
High level
input
voltage
VCC = 5.5 V 3.85
V
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 3 V 0.9 V
VIL
Low level
input
voltage
VCC = 5.5 V 1.65
V
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 2 V −50 mA
IOH High-level output current VCC = 3.3 V ± 0.3 V −4
mA
IOH
High level
output
current
VCC = 5 V ±0.5 V −8 mA
VCC = 2 V 50 mA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4
mA
IOL
Low level
output
current
VCC = 5 V ±0.5 V 8mA
∆t/∆v
Input transition rise or fall rate
VCC = 3.3 V ± 0.3 V 100
ns/V
∆t/∆vInput transition rise or fall rate VCC = 5 V ±0.5 V 20 ns/V
TAOperating free-air temperature −40 125 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74AHC1G04-Q1
SINGLE INVERTER GATE
SCLS540A − AUGUST 2003 − REVISED APRIL 2008
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25°C
MIN
MAX
UNIT
PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX UNIT
2 V 1.9 2 1.9
IOH = −50 mA3 V 2.9 3 2.9
V
OH
IOH
50
mA
4.5 V 4.4 4.5 4.4 V
VOH
IOH = −4 mA 3 V 2.58 2.48
V
IOH = −8 mA 4.5 V 3.94 3.8
2 V 0.1 0.1
IOL = 50 mA3 V 0.1 0.1
V
OL
IOL
50
mA
4.5 V 0.1 0.1 V
VOL
IOL = 4 mA 3 V 0.36 0.5
V
IOL = 8 mA 4.5 V 0.36 0.5
IIVI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1mA
ICC VI = VCC or GND, IO = 0 5.5 V 1 20 mA
CiVI = VCC or GND 5 V 2 10 10 pF
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE MIN TYP MAX MIN MAX UNIT
tPLH
7.5 10.6 1 14.5
ns
tPHL
A Y CL = 50 pF 7.5 10.6 1 14.5 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE MIN TYP MAX MIN MAX UNIT
tPLH
5.3 7.5 1 10
ns
tPHL
A Y CL = 50 pF 5.3 7.5 1 10 ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 12 pF
SN74AHC1G04-Q1
SINGLE INVERTER GATE
SCLS540A − AUGUST 2003 − REVISED APRIL 2008
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 kΩ
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH − 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jul-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
1A1G04QDBVRG4Q1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
CAHC1G04QDCKRG4Q1 ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN74AHC1G04QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
SN74AHC1G04QDCKRQ1 ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHC1G04-Q1 :
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jul-2010
Addendum-Page 2
•Catalog: SN74AHC1G04
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
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