RFD14N05L, RFD14N05LSM, RFP14N05L Data Sheet November 2004 14A, 50V, 0.100 Ohm, Logic Level, N-Channel Power MOSFETs Features * 14A, 50V These are N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V-5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA09870. Ordering Information PART NUMBER PACKAGE * rDS(ON) = 0.100 * Temperature Compensating PSPICE(R) Model * Can be Driven Directly from CMOS, NMOS, and TTL Circuits * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol BRAND D RFD14N05L TO-251AA 14N05L RFD14N05LSM TO-252AA 14N05L RFP14N05L TO-220AB F14N05L G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05LSM9A. S Packaging JEDEC TO-251AA JEDEC TO-252AA SOURCE DRAIN GATE DRAIN (FLANGE) GATE DRAIN (FLANGE) SOURCE JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) (c)2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1 RFD14N05L, RFD14N05LSM, RFP14N05L Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD14N05L, RFD14N05LSM, RFP14N05L 50 50 10 14 Refer to Peak Current Curve Refer to UIS Curve 48 0.32 -55 to 175 Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg UNITS V V V A W W/oC oC oC oC 300 260 CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS ID = 250A, VGS = 0V, Figure 13 50 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250A, Figure12 1 - 2 V VDS = 40V, VGS = 0V - - 1 A Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) - - 50 A VGS = 10V - - 100 nA - - 0.100 VDD = 25V, ID = 7A, RL = 3.57, VGS = 5V, RGS = 0.6 - - 60 ns - 13 - ns - 24 - ns td(OFF) - 42 - ns tf - 16 - ns t(ON) Turn-On Delay Time td(ON) Rise Time tr Fall Time Turn-Off Time VDS = 40V, VGS = 0V, TC = 150oC ID = 14A, VGS = 5V, Figures 9, 11 rDS(ON) Turn-On Time Turn-Off Delay Time TEST CONDITIONS t(OFF) Total Gate Charge Gate Charge at 5V Threshold Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 40V, ID = 14A, RL = 2.86 Figures 20, 21 Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V VDS = 25V, VGS = 0V, f = 1MHz Figure 14 - - 100 ns - - 40 nC - - 25 nC - - 1.5 nC - 670 - pF - 185 - pF Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS - 50 - pF Thermal Resistance Junction to Case RJC - - 3.125 oC/W Thermal Resistance Junction to Ambient RJA TO-251 and TO-252 - - 100 oC/W RJA TO-220 - - 80 oC/W Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS MIN TYP MAX UNITS ISD = 14A - - 1.5 V ISD = 14A, dISD/dt = 100A/s - - 125 ns NOTES: 2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). (c)2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1 RFD14N05L, RFD14N05LSM, RFP14N05L Typical Performance Curves Unless Otherwise Specified 16 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 12 8 4 0.2 0 0 125 50 75 100 TC , CASE TEMPERATURE (oC) 25 150 0 175 25 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE 2 Z JC, NORMALIZED THERMAL IMPEDANCE 1 0.5 0.2 0.1 PDM 0.1 0.05 t1 t2 0.02 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x Z JC x R JC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE TC = 25oC TJ = MAX. RATED 100s 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 10ms 100ms DC 0.5 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA (c)2004 Fairchild Semiconductor Corporation 100 200 IDM, PEAK CURRENT CAPABILITY (A) ID, DRAIN CURRENT (A) 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150 VGS = 5V TC = 25oC 10 -5 10-4 10 VGS = 10V 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 FIGURE 5. PEAK CURRENT CAPABILITY RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1 RFD14N05L, RFD14N05LSM, RFP14N05L Typical Performance Curves Unless Otherwise Specified (Continued) 35 VGS = 10V VGS = 5V 30 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 50 STARTING TJ = 25oC 10 STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) 0.01 VGS = 4V 25 PULSE DURATION = 80s, TC = 25oC DUTY CYCLE = 0.5% MAX. 20 15 VGS = 3V 10 5 If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1] 1 VGS = 4.5V 0.1 1 tAV, TIME IN AVALANCHE (ms) 0 10 VGS = 2.5V 1.5 6.0 3.0 4.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 7.5 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 7. SATURATION CHARACTERISTICS 250 35 -55oC 30 ID = 7A 25oC rDS(ON) , DRAIN TO SOURCE ON RESISTANCE (m) IDS(ON), DRAIN TO SOURCE CURRENT (A) FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING 175oC 25 20 15 10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. VDD = 15V 5 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 50 NORMALIZED DRAIN TO SOURCE ON RESISTANCE td(OFF) 100 tr 80 tf 60 40 td(ON) 20 0 20 30 40 10 RGS , GATE TO SOURCE RESISTANCE () FIGURE 10. SWITCHING TIME vs GATE RESISTANCE (c)2004 Fairchild Semiconductor Corporation 3.0 3.5 4.0 4.5 VGS , GATE TO SOURCE VOLTAGE (V) 5.0 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 120 0 0 2.5 2.5 VDD = 25V, ID = 14A, RL = 3.57 ID = 3.5A 100 7.5 140 SWITCHING TIME (ns) 150 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. FIGURE 8. TRANSFER CHARACTERISTICS 160 ID = 28A 200 0 0 ID = 14A 50 2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. VGS = 10V, ID = 14A 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1 RFD14N05L, RFD14N05LSM, RFP14N05L Typical Performance Curves 2.0 VGS = VDS, ID = 250A ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) CISS C, CAPACITANCE (pF) 0.5 0 -80 600 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD COSS 200 CRSS 200 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 50 40 5 VDD = BVDSS VDD = BVDSS 4 30 3 20 2 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS RL = 3.57 IG(REF) = 0.4mA VGS = 5V 10 1 0 0 0 5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V) -40 FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VDS , DRAIN TO SOURCE VOLTAGE (V) 800 0 1.0 200 FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 400 1.5 I G ( REF ) 20 ------------------------I G ( ACT ) 25 VGS , GATE TO SOURCE VOLTAGE (V) NORMALIZED GATE THRESHOLD VOLTAGE 2.0 Unless Otherwise Specified (Continued) t, TIME (s) I G ( REF ) 80 ------------------------I G ( ACT ) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260, FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. TRANSCONDUCTANCE vs DRAIN CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0 0.01 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT (c)2004 Fairchild Semiconductor Corporation FIGURE 17. UNCLAMPED ENERGY WAVEFORMS RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1 RFD14N05L, RFD14N05LSM, RFP14N05L Test Circuits and Waveforms (Continued) tON tOFF td(ON) VDS td(OFF) tr VDS tf 90% 90% RL VGS + - DUT 10% 0 VDD 10% 90% RGS VGS VGS 0 50% 10% FIGURE 18. SWITCHING TIME TEST CIRCUIT 50% PULSE WIDTH FIGURE 19. RESISTIVE SWITCHING WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + VDD DUT IG(REF) VGS = 5V VGS - VGS = 1V 0 Qg(TH) IG(REF) 0 FIGURE 20. GATE CHARGE TEST CIRCUIT (c)2004 Fairchild Semiconductor Corporation FIGURE 21. GATE CHARGE WAVEFORMS RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1 RFD14N05L, RFD14N05LSM, RFP14N05L PSPICE Electrical Model .SUBCKT RFP14N05L 2 1 3 ; rev 9/15/94 CA 12 8 1.464e-9 CB 15 14 1.64e-9 CIN 6 8 6.17e-10 DPLCAP RSCL1 RSCL2 ESG + GATE 1 9 6 8 ESCL LGATE RGATE 11 RDRAIN 16 VTO + 21 EVTO 20 + 18 + DBODY EBREAK 17 18 MOS2 6 MOS1 8 RIN CIN 8 RSOURCE 7 LSOURCE 3 SOURCE S2A S1A 12 S1A S1B S2A S2B DBREAK 50 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 33.1e-3 RGATE 9 20 5.85 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 14.3e-3 RVTO 18 19 RVTOMOD 1 + 51 5 51 EBREAK 11 7 17 18 65.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 LDRAIN 2 5 1e-9 LGATE 1 9 5.68e-9 LSOURCE 3 7 5.35e-9 DRAIN 2 LDRAIN DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD IT 8 17 1 5 10 S1B RBREAK 15 14 13 13 8 17 18 S2B RVTO 13 CA CB + EGS 6 8 IT + 14 EDS 5 8 19 VBAT + 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.485 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))} .MODEL DBDMOD D (IS = 2.23e-13 RS = 1.15e-2 TRS1 = 1.64e-3 TRS2 = 7.89e-6 CJO = 6.83e-10 TT = 3.68e-8) .MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5) .MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6) .MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5) .MODEL RSCLMOD RES (TC1 = 2.8e-3 TC2 = 6.0e-6) .MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = -2.0e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= 2.45) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley. (c)2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FAST ActiveArrayTM FASTrTM BottomlessTM FPSTM CoolFETTM FRFETTM CROSSVOLTTM GlobalOptoisolatorTM DOMETM GTOTM EcoSPARKTM HiSeCTM E2CMOSTM I2CTM EnSignaTM i-LoTM FACTTM ImpliedDisconnectTM FACT Quiet SeriesTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC Across the board. Around the world.TM OPTOPLANARTM PACMANTM The Power Franchise POPTM Programmable Active DroopTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I13