©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14 N05L Rev. B1
RFD14N05L, RFD14N05LSM, RFP14N05L
14A, 50V, 0.100 Ohm, Logic Level,
N-Channel Power MOSFETs
These are N-channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and rela y drivers . This perf ormance is accomplished
through a special gate oxide design which provides full rated
conductance at gate bias in the 3V-5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.
Formerly developmental type TA09870.
Features
14A, 50V
•r
DS(ON) = 0.100
Temperature Compensating PSPICE® Model
Can be Driven Directly from CMOS, NMOS, and
TTL Circuits
Peak Current vs Pulse Width Curve
UIS Rating Curve
•175
oC Operating Temperature
Related Literature
- T B334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-251AA JEDEC TO-252AA
JEDEC TO-220AB
Ordering Information
PART NUMBER PACKAGE BRAND
RFD14N05L TO-251AA 14N05L
RFD14N05LSM TO-252AA 14N05L
RFP14N05L TO-220AB F14N05L
NO TE: When ordering, use the entire part number . Add the suffix 9A to
obtain the T O-252AA variant in the tape and reel, i.e., RFD14N05LSM9A.
G
D
S
SOURCE
DRAIN (FLANGE)
GATE
DRAIN GATE
SOURCE
DRAIN (FLANGE)
GATE
DRAIN (FLANGE)
SOURCE
DRAIN
Data Sheet November 2004
©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14 N05L Rev. B1
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD14N05L, RFD14N05LSM,
RFP14N05L UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 50 V
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 50 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±10 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 14
Refer to Peak Current Curve A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
0.32 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicat ed in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, Figure 13 50 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA, Figure12 1 - 2 V
Zero Gate Voltage Drain Current IDSS VDS = 40V, VGS = 0V - - 1 µA
VDS = 40V, VGS = 0V, TC = 150oC--50µA
Gate to Source Leakage Current IGSS VGS = ±10V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 14A, VGS = 5V, Figures 9, 11 - - 0.100
Turn-On Time t(ON) VDD = 25V, ID = 7A,
RL = 3.57, VGS = 5V,
RGS = 0.6
--60ns
Turn-On Delay Time td(ON) -13 - ns
Rise Time tr-24 - ns
Turn-Off Delay Time td(OFF) -42 - ns
Fall Time tf-16 - ns
Turn-Off Time t(OFF) - - 100 ns
Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 40V, ID = 14A,
RL = 2.86
Figures 20, 21
- - 40 nC
Gate Charge at 5V Qg(5) VGS = 0V to 5V - - 25 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 1V - - 1.5 nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz
Figure 14 - 670 - pF
Output Capacitance COSS - 185 - pF
Reverse Transfer Capacitance CRSS -50 - pF
Thermal Resistance Junction to Case RθJC - - 3.125 oC/W
Thermal Resistance Junction to Ambient RθJA TO-251 and TO-252 - - 100 oC/W
RθJA TO-220 - - 80 oC/W
Sour ce to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage (Note 2) VSD ISD = 14A - - 1.5 V
Diode Reverse Recovery Time trr ISD = 14A, dISD/dt = 100A/µs - - 125 ns
NOTES:
2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
RFD14N05L, RFD14N05LSM, RFP14N05L
©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14 N05L Rev. B1
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPA TION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
25 50 75 100 125 150 17
5
0
POWER DISSIPATION MULTIPLIER
0
0
0.2
0.4
0.6
0.8
1.0
1.2
8
4
025 50 75 100 125 150
12
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
16
17
5
t, RECTANGULAR PULSE DURATION (s)
10-3 10-2 10-1 100
0.01
0.1
1
10-5 101
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
0.5
10-4
2
THERMAL IMPEDANCE
ZθJC, NORMALIZED
VDS, DRAIN T O SOURCE VOLTAGE (V)
10 10
0
1
100
10
1
ID, DRAIN CURRENT (A)
DC
100µs
100ms
1ms
10ms
0.5
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
TC = 25oC
TJ = MAX. RATED
t, PULSE WIDTH (s)
10
10-5 10-4 10-3 10-2 10-1 100101
VGS = 10V
100
IDM, PEAK CURRENT CAPABILITY (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 5V
200
TC = 25oC
RFD14N05L, RFD14N05LSM, RFP14N05L
©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14 N05L Rev. B1
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARA CTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
0.1 1 1
0
10
0.01
50
1
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
0
5
10
15
01.5 3.0 4.5 7.
5
20
25
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 4V
VGS = 10V
30
35
6.0
VGS = 3V
VGS = 2.5V
VGS = 5V
VGS = 4.5V
PULSE DURATION = 80µs, TC = 25oC
DUTY CYCLE = 0.5% MAX.
03.04.56.07.
5
1.5
0
5
10
15
20
25 175oC
IDS(ON), DRAIN TO SOURCE CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
-55oC
30
35
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VDD = 15V
0
50
100
150
200
2.5 3.0 3.5 4.0 4.5
rDS(ON), DRAIN TO SOURCE
VGS, GATE TO SOURCE VOLTAGE (V) 5.
0
250
ID = 28A
ID = 7A
ID = 3.5A
ID = 14A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
ON RESISTANCE (m)
0
20
010
20 30 40
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE ()5
0
40
60
80
100
120
140
160 td(OFF)
tr
tf
td(ON)
VDD = 25V, ID = 14A, RL = 3.57
0
0.5
1.0
1.5
2.0
-80 -40 0 40 80 120 160
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC) 20
0
2.5 PULSE DURATION = 80µs
ON RESISTANCE
VGS = 10V, ID = 14A
DUTY CYCLE = 0.5% MAX.
RFD14N05L, RFD14N05LSM, RFP14N05L
©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14 N05L Rev. B1
FIGURE 12. NORMALIZED GA TE THRESHOLD V OL TAGE vs
JUNCTION TEMPERATURE FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDO WN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260,
FIGURE 15. TRANSCONDUCTANCE vs DRAIN CURRENT
Test Circuits and Waveforms
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
-80 -40 0 40 80 120 160
0
0.5
1.0
1.5
2.0
NORMALIZED GATE
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATURE (oC) 20
0
VGS = VDS, ID = 250µA2.0
1.5
1.0
0.5
0
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
20
0
ID = 250µA
800
200
00 5 10 15 20 2
5
C, CAPACITANCE (pF)
400
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS
COSS
CRSS
600
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
40
30
20
10
0
20IGREF()
IG ACT()
-------------------------t, TIME (µs) 80IGREF()
IGACT()
-------------------------
5
3
2
1
0
VDD = BVDSS VDD = BVDSS
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
RL = 3.57
IG(REF) = 0.4mA
VGS = 5V
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
50
4
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RFD14N05L, RFD14N05LSM, RFP14N05L
©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14 N05L Rev. B1
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms (Continued)
VGS
RL
RGS
DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10
V
VDS
VGS
I
G(REF)
0
0
RFD14N05L, RFD14N05LSM, RFP14N05L
©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14 N05L Rev. B1
PSPICE Electrical Model
.SUBCKT RFP14N05L 2 1 3 ; rev 9/15/94
CA 12 8 1.464e-9
CB 15 14 1.64e-9
CIN 6 8 6.17e-10
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 65.35
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 5.68e-9
LSOURCE 3 7 5.35e-9
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 33.1e-3
RGATE 9 20 5.85
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 14.3e-3
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.485
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))}
.MODEL DBDMOD D (IS = 2.23e-13 RS = 1.15e-2 TRS1 = 1.64e-3 TRS2 = 7.89e-6 CJO = 6.83e-10 TT = 3.68e-8)
.MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5)
.MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6)
.MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5)
.MODEL RSCLMOD RES (TC1 = 2.8e-3 TC2 = 6.0e-6)
.MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = - 2.0e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 V ON = -2.55 VOFF= 2.45)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; authored by William J. Hepp and C. Frank Wheatley.
1
GATE
LGATE RGATE
EVTO
18
8
+
12 13
814
13
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
RIN CIN
MOS1
MOS2
DBREAK
EBREAK DBODY
LDRAIN DRAIN
RSOURCE LSOURCE
SOURCE
RBREAK
RVTO
VBAT
IT
VTO
ESG
DPLCAP
6
6
8
10 5
16
21
11
17
18
8
14
5
8
6
8
73
17 18
19
2
++
+
+
+
+
20
RDRAIN
ESCL
RSCL1
RSCL2 51
50
5
51
+
9
RFD14N05L, RFD14N05LSM, RFP14N05L
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS P ATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF F AIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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