54ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ’ABT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
nClock enable for address and data synchronization
applications
nEight edge-triggered D flip-flops
nBuffered common clock
nSee ’ABT273 for master reset version
nSee ’ABT373 for transparent latch version
nSee ’ABT374 for TRI-STATE®version
nOutput sink capability of 48 mA, source capability of
24 mA
nGuaranteed latchup protection
nHigh impedance glitch free bus loading during entire
power up and power down cycle
nNon-destructive hot insertion capability
nDisable time less than enable time to avoid bus
contention
nStandard Microcircuit Drawing (SMD) 5962-9314801
Ordering Code:
Military Package Package Description
Number
54ABT377J-QML J20A 20-Lead Ceramic Dual-In-Line
54ABT377W-QML W20A 20-Lead Cerpack
54ABT377E-QML E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagram
Pin
Names Description
D
0
–D
7
Data Inputs
CE Clock Enable (Active LOW)
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
Pin Assignment for
DIP and Cerpack
DS100216-1
Pin Assignment for LCC
DS100216-11
July 1998
54ABT377 Octal D-Type Flip-Flop with Clock Enable
© 1998 National Semiconductor Corporation DS100216 www.national.com
Truth Table
Mode Select-Function Table
Operating Mode Inputs Output
CP CE D
n
Q
n
Load “1” I h H
Load “0” I I L
Hold h X No Change
(Do Nothing) X H X No Change
H=HIGH Voltage Level
h=HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
L=LOW Voltage Level
I=LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
X=Immaterial
=LOW-to-HIGH Clock Transition
Logic Diagram
DS100216-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias
Ceramic −55˚C to +175˚C
V
CC
Pin Potential to
Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State −0.5V to +4.75V
in the HIGH State −0.5V to V
CC
Current Applied to Output
in LOW State (Max) Twice the rated I
OL
(mA)
DC Latchup Source Current −500 mA
(Across Comm Operating Range)
Over Voltage Latchup V
CC
+ 4.5V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military −55˚C to +125˚C
Supply Voltage
Military +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)
Data Input 50 mV/ns
Enable Input 20 mV/ns
DC Electrical Characteristics
Symbol Parameter ABT377 Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min I
IN
=−18 mA
V
OH
Output HIGH Voltage 54ABT 2.5 V Min I
OH
=−3 mA
54ABT 2.0 I
OH
=−24 mA
V
OL
Output LOW Voltage 54ABT 0.55 V Min I
OL
=48 mA
I
IH
Input HIGH Current 5 µA Max V
IN
=2.7V (Note 4)
5V
IN
=V
CC
I
BVI
Input HIGH Current 7 µA Max V
IN
=7.0V
Breakdown Test
I
IL
Input LOW Current −5 µA Max V
IN
=0.5V (Note 4)
−5 V
IN
=0.0V
V
ID
Input Leakage Test 4.75 V 0.0 I
ID
=1.9 µA
All Other Pins Grounded
I
OS
Output Short-Circuit Current −100 −275 mA Max V
OUT
=0.0V
I
CEX
Output High Leakage Current 50 µA Max V
OUT
=V
CC
I
CCH
Power Supply Current 50 µA Max All Outputs HIGH
I
CCL
Power Supply Current 30 mA Max All Outputs LOW
I
CCT
Maximum I
CC
/Input Outputs Enabled V
I
=V
CC
− 2.1V
1.5 mA Max Data Input V
I
=V
CC
− 2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load 0.3 mA/ Max Outputs Open (Note 3)
MHz One bit Toggling, 50%Duty Cycle
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions
is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Note 3: For 8 bits toggling, ICCD <0.5 mA/MHz.
Note 4: Guaranteed but not tested.
3 www.national.com
AC Electrical Characteristics
Symbol Parameter 54ABT Units
T
A
=−55˚C to +125˚C
V
CC
=4.5V to 5.5V
C
L
=50 pF
Min Max
f
max
Max Clock 150 MHz
Frequency
t
PLH
Propagation Delay 2.2 6.0 ns
t
PHL
CP to O
n
2.8 6.8
AC Operating Requirements
54ABT
T
A
=−55˚C to +125˚C
Symbol Parameter V
CC
=4.5V to 5.5V Units
C
L
=50 pF
Min Max
t
s
(H) Setup Time, HIGH 2.0 ns
t
s
(L) or LOW D
n
to CP 2.0
t
h
(H) Hold Time, HIGH 1.8 ns
t
h
(L) or LOW D
n
to CP 1.8
t
s
(H) Setup Time, HIGH 3.0 ns
t
s
(L) or LOW CE to CP 3.0
t
h
(H) Hold Time, HIGH 1.0 ns
t
h
(L) or LOW CE to CP 1.0
t
w
(H) Pulse Width, CP, 3.3 ns
t
w
(L) HIGH or LOW 3.3
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 5 pF V
CC
=0V, T
A
=25˚C
C
OUT
(Note 5) Output Capacitance 9 pF V
CC
=5.0V
Note 5: COUT is measured at frequency f =1 MHz, per MIL-STD-883B, Method 3012.
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AC Loading
Input Pulse Requirements
DS100216-4
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100216-6
FIGURE 2. V
M
=1.5V
Amplitude Rep. Rate t
w
t
r
t
f
3.0V 1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100216-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100216-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100216-9
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Ceramic Chip Carrier
NS Package Number E20A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Dual-In-Line Package
NS Package Number J20A
20-Lead Ceramic Flatpack
NS Package Number W20A
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CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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54ABT377 Octal D-Type Flip-Flop with Clock Enable
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
