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08/10/06
HEXFET® Power MOSFET
Notes through are on page 12
PD - 94927A
lHigh frequency DC-DC converters
lLead-Free
Benefits
Applications
lLow Gate-to-Drain Charge to Reduce
Switching Losses
lFully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
lFully Characterized Avalanche Voltage
and Current
IRFB41N15DPbF
IRFIB41N15DPbF
IRFS41N15DPbF
IRFSL41N15DPbF
VDSS RDS(on) max ID
150V 0.045
:
41A
Absolute Maximum Ratings
Parameter Units
ID @ TC = 25 °C Cont inuous Drai n Curre nt, VGS @ 10V
ID @ TC = 10 0°C Cont inuous Drai n Curre nt, VGS @ 10V A
IDM Pu ls ed D r ai n C ur rent
c
PD @TA = 25 °C Power Diss i pati on , D2Pak W
PD @TC = 25°C Po wer Di s s ipat i on, TO - 2 20
PD @TC = 25°C Po wer Di s s ipat i on, Ful l pak
Linear Derating Factor, TO-220 W/°C
Linear Derating Factor, Fullpak
VGS Gate- to- Sour c e V o ltage V
dv/dt P eak Di ode R ecover y dv/dt
e
V/ns
TJ Ope r ati n g J unction and
TSTG Storage Temper ature Range °C
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw N•m (lbf•in)
Therm al R esistan ce
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.75 °C/W
RθJC Junction-to-Case, Fullpak ––– 3.14
Rθcs Case-to- Sink, Flat, Greased Surface
h
0.50 –––
RθJA Junction-to-Ambient, TO-220
h
––– 62
RθJA Junction-to-Ambient, D2Pak
i
––– 40
RθJA Junction-to-Ambient, Fullpak ––– 65
3.1
48
0.32
200
1.3
± 30
2.7
Max.
41
29
164
-55 to + 17 5
300 (1.6mm fro m case )
1.1(10)
D2Pak
IRFS41N15D
TO-220AB
IRFB41N15D TO-262
IRFSL41N15D
TO-220 FullPak
IRFIB41N15D
IRFB/IRFIB/IRFS/IRFSL41N15DPbF
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S
D
G
Static @ TJ = 25°C (unless otherwise specif ied)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS D r ai n- to- Sour c e B reak dow n Volta ge 150 ––– –– – V
V
GS
= 0V , I
D
= 250µA
∆
V
(BR)DSS
/
∆
T
J Breakdown Voltage Te m p. Coefficient ––– 0.17 ––– V/° C
D
= 1mA
R
DS(on) Static Dr ain- to- Sour c e O n- Res i s tance ––– –– – 0. 04 5 Ω
V
GS
= 10V , I
D
= 25A
f
V
GS(th) G ate Th r es hold V o ltage 3. 0 ––– 5.5 V
V
DS
= V
GS
, I
D
= 250µA
I
DSS Dr ai n- to- Sour c e Leaka ge Cu r rent ––– –– – 25 µ A
V
DS
= 150V, V
GS
= 0V
––– ––– 250
V
DS
= 120V, V
GS
= 0V , T
J
= 150°C
I
GSS Gate-to-Source Forward Leakage ––– ––– 100 nA
V
GS
= 30V
Gate- to- Sour c e R ev er s e Le akage –– – ––– -1 00
V
GS
= -30 V
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
gfs For ward Transco nductan c e 18 ––– ––– S
V
DS
= 50V, I
D
= 25A
Q
gTot a l G ate C ha r ge ––– 7 2 11 0
I
D
= 25A
Q
gs Gate- to- Sour c e C ha r ge ––– 2 1 31 nC
V
DS
= 120V
Q
gd Gate-to-Drain ("Miller") Charge ––– 35 52
V
GS
= 10V
f
t
d(on) Turn-On Delay Time ––– 16 –––
V
DD
= 75V
t
rRise Time –––63–––
I
D
= 25A
t
d(off) Turn-Off Delay Ti me ––– 2 5 ––– ns
R
G
= 2.5
Ω
t
fFall Time –––14–––
V
GS
= 10V
f
C
iss In pu t C apac it a nce ––– 25 20 –– –
V
GS
= 0V
C
oss Output Capacitance ––– 510 –––
V
DS
= 25V
C
rss Reverse Transfer Capacitance ––– 110 ––– pF ƒ = 1.0MHz
C
oss Out pu t Capac ita nc e ––– 30 90 –– –
V
GS
= 0V, V
DS
= 1.0V, ƒ = 1.0MHz
C
oss Output Capacitance ––– 230 –––
V
GS
= 0V, V
DS
= 120V, ƒ = 1.0MHz
C
oss
eff.
Effective Output Capacitance ––– 250 –––
V
GS
= 0V , V
DS
= 0V to 120V
g
Aval anche C haract eristi cs
Parameter Typ. Max. Units
E
AS Si ngle P ul se A v a l a nc he E n er g y
d
––– 470 mJ
I
AR Avalanche Current
c
––– 25 A
E
AR Repetiti ve Avalanche Energy
c
––– 20 mJ
Diode Charac teri stics
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current ––– ––– 41 MOSFET symbol
(Body Diode) A showi ng the
ISM Pulsed Source Current ––– ––– 164 integral reverse
(Body Diode)
c
p- n juncti o n diode.
VSD Diode Fo rward Voltage ––– – –– 1.3 V TJ = 25°C, IS = 25 A, VGS = 0V
f
trr Reverse Recovery Time ––– 170 260 ns TJ = 25°C, IF = 25A
Qrr Reverse Recovery Charge ––– 1.3 1.9 µ C di/dt = 100A/µs
f
ton For w ard Tur n - O n Ti m e Int ri n s ic t u r n-on t i m e is negligi b le (t ur n - on i s dom i nat e d by LS+LD
)
IRFB/IRFIB/IRFS/IRFSL41N15DPbF
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Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
1000
0.1 1 10 100
20µs PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
9.0V
8.0V
7.5V
7.0V
6.5V
6.0V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
6.0V
1
10
100
1000
0.1 1 10 100
20µs PU LSE WIDTH
T = 175 C
J°
TOP
BOTTOM
VGS
15V
10V
9.0V
8.0V
7.5V
7.0V
6.5V
6.0V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
6.0V
1
10
100
1000
6 7 8 9 10 11
V = 25V
20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 175 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Temperature ( C)
R , Drain -to -S o u rce On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
41A
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
020 40 60 80 100 120
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
25A
V = 30V
DS
V = 75V
DS
V = 120V
DS
110 100 1000
VDS, Drain-t o-Source Volt age (V)
10
100
1000
10000
100000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + C gd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0.1
1
10
100
1000
0.2 0.6 1.0 1.4 1.8
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 175 C
J°
1
10
100
1000
1 10 100 100
0
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 175 C
= 25 C
°°
J
C
V , Drain-to-Source Voltage (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
IRFB/IRFIB/IRFS/IRFSL41N15DPbF
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Fig 10a. Switching Time Test Circuit
V
DS
9
0%
1
0%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
VGS
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25 50 75 100 125 150 175
0
10
20
30
40
50
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Durati on (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
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QG
QGS QGD
V
G
Charge
D.U.T. V
D
S
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
VGS
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
ID
TOP 7.3A
13A
BOTTOM 18A
25 50 75 100 125 150 175
0
200
400
600
800
1000
1200
Star ting T , Junction Temperat ure( C)
E , Single P ulse Avalanche E nergy (m J)
J
AS
°
ID
TOP
BOTTOM
10A
21A
25A
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P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFET® Power MOSFETs
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
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LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
- B -
1.32 (.052)
1.22 (.048)
3X 0 .55 (. 022 )
0 .46 (. 018 )
2.92 (.115)
2.64 (.104)
4.69 (.185)
4.20 (.165)
3X 0.93 (.037)
0.69 (.027)
4 .06 (.160)
3 .55 (.140)
1.15 (.045)
MIN
6.47 (.255)
6.10 (.240)
3.78 (.149)
3.54 (.139)
- A -
1 0. 54 (. 415)
1 0. 29 (. 405)
2 .87 (. 113)
2 .62 (. 103)
15.24 (.600)
14.84 (.584)
14.09 (.555)
13.47 (.530)
3X 1.4 0 (. 055)
1.1 5 (. 045)
2.54 (.100)
2X
0.36 (.014) M B A M
4
1 2 3
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFO RMS TO JEDEC OUTLINE TO-220AB .
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NO T INCLUDE BURRS.
HEXFET
1- GAT E
2- DRAIN
3- SOU RCE
4- DRAIN
LEAD ASSIG NMEN TS
IGBTs, CoPAC
K
1- GAT E
2- CO LLECTO
R
3- EM ITTER
4- CO LLECTO
R
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
(;$03/(
,17+($66(0%/</,1(&
7+,6,6$1,5)
/27&2'(
$66(0%/('21:: 3$57180%(5
$66(0%/<
/27&2'(
'$7(&2'(
<( $5  
/,1(&
:((.
/2*2
5(&7,),(5
,17(51$7,21$/
Note: "P" in a s s emb ly lin e
position indicates "Lead-Free"
IRFB/IRFIB/IRFS/IRFSL41N15DPbF
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TO-220 Full-Pak Part Marking Information
:,7+$66(0%/<
(;$03/( 7+,6,6$1,5),*
/27&2'(
$66(0%/('21::
,17+($66(0%/</,1(.
3$57180%(5
/27&2'(
$66(0%/<
,17(51$7,21$/
5(&7,),(5
/2*2
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.
,5),*
'$7(&2'(
<( $ 5 
:((.
/,1(.
Note: "P" in asse mbly line
position indicate s "Lead-Free"
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
IRFB/IRFIB/IRFS/IRFSL41N15DPbF
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D2Pak Part Marking Information (Lead-Free)
D2Pak Package Outline
1R WH3 LQD VVHP EO\OLQH
SRVLWLRQLQGLFDWHV/HDG)UHH
)6
7+,6,6$1,5)6:,7+
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$66(0%/('21::
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$66(0%/<
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5(&7,),(5
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OR
)6
$ $66(0%/<6,7(&2' (
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5(&7,),(5
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/2*2
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3$57180%(5
IRFB/IRFIB/IRFS/IRFSL41N15DPbF
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TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
$66(0%/<
/27&2'(
5(&7,),(5
,17(51$7,21$/
$66(0%/('21::
1RWH3LQDVVHPEO\OLQH
SRVLWLRQLQGLFDWHV/HDG)UHH
,17+($66(0%/</,1(& /2*2
7+,6,6$1,5//
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OR
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Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 1.5mH, RG = 25Ω,
IAS = 25A.
ISD ≤ 25A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Notes:
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/2006
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
This is only applied to TO-220AB package.
This is applied to D2Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
TO-220AB & TO-220 FullPak packages are not recommended for Surface Mount Application.
D2Pak Tape & Reel Information
3
4
4
TRR
F
EED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
F
EED DIRECTION
10.90 (.429)
10.70 (.421) 16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957
)
23.90 (.941
)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941 )
60.00 (2.362
)
MIN.
30.40 (1 .197)
MAX.
26.40 (1 .039)
24.40 (.961)
NOT E S :
1. COMFORMS TO EIA-418.
2. CONTROL LING DIMENSION: MILLIMETE R.
3. DIMENSION ME A SUR ED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/