am 21 1S: motaic ] MEM832V/J-90/12/15 issue 2.1 : May 1993 Mosaic PRELIMINARY Semiconductor ne (Pin Definitions > 32,768 x 8 High Speed CMOS EEPROM Features A410 28 Very Fast Access Times of 90/120/150 ns. AN 2 = 7 A13 VIL and JLCC packages available. AB 40 125 As JEDEC Approved Byte-wide pinout Ss 5% Gz 24 Ag Operating Power 440 mW (max) Aa 7c SS So te Standby Power 16.5 mW (max TTL) A2 8c a6 21 A10 1.65 mW (max CMOS) Al 9CJ >F [20 S&S Hardware and Software Data Protection. a 0 S S 13 07 64 Byte Page Operation. D1 12 347 05 DATA Poiling/Toggle Bit for End of Write Detection. D2 13 CJ 316 04 10* Erase/Write cycles & 10 year Data Retention. GND 14 P4315 03 Completely Static Operation. : May be Screened in as MIL-STD-883 (suffix MB) VIL is a Trademark of Mosaic Semiconductor Inc. , Block Diagram AG AS AT as AS A2 as Al 10 AO a2 Ne Ai3 0 A14 DO oy Pin Functions = AO-A14 Address 00-7 Data VO We -_ CS = Chip Select +WE Write Enabie es r0 ss: Bu OE Output Enable NC No Connect Vee Power GND Ground 22eQ9ze S D \ Package Details Pin Count Description Package Type Material Pin Out 28 0.1" Vertical-in-Line (VIL) Vv Ceramic JEDEC 32 J-Leaded Chip Carrier (JLCC) J Ceramic JEDEC Package dimensions and outlines are displayed on page 9. \ VIL is a trademark of Mosaic Semiconductor, U.S. Patent number 0316251. /) |(SSUE 2.1: MAY 1993 , MEM632-90/12/15 Absolute Maximum Ratings Voltage on any pin relative to GND V, -0.6V to +6.25 Vv Voltage on OE and A9 relative to GND Voc, ~0-6V to +13.5 Vv Power Dissipation P, 1 Ww Storage Temperature Tag 65 to +150 C Temperature Under Bias Taras -55 to +125 C Notes: (1) Stresses above those fisted may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicatedin the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) V, can be -3.5V pulse of less than 20ns. Recommended Operating Conditions ; min typ max Supply Voltage Voc 45 0 5 Vv input High Voltage Vu 2.0 - Voet1.0 V Input Low Voltage VY -0.1 - 0.8 Vv Operating Temperature -T, 0 - 70 C Ta -40 - 85 C (MEM832I) Tan -55 - 125 C (MEM832M,MB) DC Electrical Characteristics Parameter Symbol Test Condition min max = Unit Input Leakage Current lia OVSV,SV,.+1V - 10 pA Output Leakage Current [,, CS=V,, V,9=GND to V,, - 10 pA Average Current loot f = 5 Mkz, |,,=OmA - 80 mA Standby Current TTL lg 2.0V<CS<V,+H1V - 3 mA Standby Current CMOS loss Voc0.3V s CS < V,.41V - 300 pA Output Voltage Vo 1, =6MA - 0.45 Vv Von log -4MA 2.4 - Vv Write Inhibit Voltage Vn 3.0 - V Capacitance (V,.=5V110%,T,=25C, f=1MHz) Parameter Symbol Test Condition typ max Unit Input Capacitance C,, V,,= OV 4 6 pF VO Capacitance Ci Vio = OV 8 12 pF Note: Capacitance calculated, not measured. AC Test Conditions Output Test Load Voc * Input pulse levels: 0.8V to 2.4V * Input rise and fall times: Sns 18kQ * Input and Output timing reference levels: 1.5V * Output load: 1 TTL gate + 100pF Output * Vop=5Vt10%MEM832-90/12/15 ISSUE 2.1 : MAY 1993 Electrical Characteristics and Recommended AC Operating Conditions Read Cycle -90 -12 -15 Parameter Symbol min max min max min max _ Unit Notes Read Cycle Time tec 90 - 120. - 150 - ns Address to Output Delay troe - 90 - 120 - 150 ns CS to Output Delay tes - 90 - 120 - 150 ns (1) OE to Output Delay toe 0 45 0 50 Oo 50 ns = (2) CS or OE to Output Float toe 0 45 0 ~~ =60 0 = 8650 ns (3,4) Output Hold from OE, CS or tou o 0 - o - ns Address, (whichever occured first) Notes: (1) CS may be delayed up to t,,.. - t., after the address transition without impact on t,.. - i i -t,, after (2) OF may be delayed up 10 a Fegan ine Faling edge of CS without impact on fy OF BY los be an (tn seca a cede meee Read Cycle Timing Waveform lac Address Address Valid cS OE OutputISSUE 2.1 : MAY 1993 , 7 MEM832-90/12/15 Write Cycle Parameter Symbol min typ max Unit Write Cycle Time twe - - 12 ms Address, OE Set-up Time tas: toes 0 - - ns Address Hold Time tay 50 - - ns Chip Select Set-up Time tes 0 - - ns Chip Select Hold Time ton 0 - - ns Write Pulse Width (WE or CS) twe 100 - - ns Data Set-up Time a 50 - - ns Data, OE Hold Time tow tocy 0 - - ns Note: (1) NR = No Restriction AC Write Waveform - WE Controlled AC Write Waveform - CS Controlled OE / a \ L_%s | al 8 Data in Q DATA VALID DMEM832-00/12/15 ISSUE 2.1 : MAY 1993 Page Mode Write Cycle Parameter Symbol min typ max Unit Write Cycle Time twe - - 12 ms Address Set-up Time bs 0 - - ns Address Hold Time tay 50 - - ns Data Set-up Time tos 50 - - ns Data Hold Time toa 0 - - ns Write Pulse Width twe 100 - - ns Byte Load Cycle Time tac 2 - 150 ps Write Pulse Width High teu 50 - - ns Page Mode Write Waveform * S ec _/ lit 4 ALD ; Sef RE x ; > < Valid ~Y 7 ~ Data ba OG, ; ee H+ Note: AG through A14 must specify the faye addres during each high to low transition of WE (or TS). OE must be high only when WE and TS are both low. Software Protected Write Waveform buf. f TT ass SOIR TOC] Note: AS through A16 must specify the page address during each high to low transition of WE (or TS) after the Software code has been entered. OE must be high only when WE and TS are both low.ISSUE 2.1: MAY 1993 MEM832-90/12/15 DATA Polling Characteristics (1) Parameter Symbol min typ max Unit Data Hold Time ton 0 - - ns WE High to Data Polling toe 500 - - ps OE to Output Delay toe - - 100 ns Write Recovery Time twa 0 - - ns Delay to Next Write tow 10 - - ps Note : (1) These parameters are sampled and not 100% tested. DATA Polling Waveform / Sf + \ Wey A cs L\S\SJ-\/S\_ top OE pee fog: D7 High Z pS XS XS A0-A14 An XX An Xn Hardware Chip Erase Waveform cS t, = t,, = Sys (min) t, = 10 ms (min) V,, = 12V + 0.5VMEM832-00/12/15 (ISSUE 2.1: MAY 1993 Toggle Bit Characteristics Parameter Symbol min typ max Unit Data Hold Time ton 10 - - ns Data Polling toe 500 - - us OE Hold Time tocn 10 - - ns OE to Output Delay toe - - 100 ns OE High Pulse tocx 150 - - ns Write Recovery Time twa 0 - - ns Delay to Next Write tow 10 - - ps Note : (1) These parameters are sampled and not 100% tested. Toggle Bit Waveform WE cs OE D6 AO-A14 Notes : (1) Toggling either OE or TS or both OE and TS will operate toggle bit. (2) Beginning and ending state of D6 may vary. (3) Any address location maybe used but the address should not vary.SSSUE 2.1: MAY 1993 MEM832-00/12/15 Device Operation Read The MEM83z2 is accessed in the same way as a static RAM. A read is accomplished when both OE and CS are low. The read is then cancelled by either CS or OE returning high. The data bus will be in a high impedance State when either OE or CS is high. Write A low pulse on WE with CS low or a low pulse on CS with WE low indicates a Write Cycle. The address is latched on the falling edge of CS or WE, and the data is latched on the first rising edge of CS or WE. Once a Byte Write has begun it will automatically time itself to completion. Page Mode Write This mode allows 1 to 64 bytes of data to be loaded into the EEPROM, which are then simultaneously written. Once the first byte has been written, each subsequent byte must have the high to low transition of WE (or TS) within 100s of the same transition of the previous byte. if this 1001s time is exceeded, the load period ends and internal programming starts. A6 to A14 specify the page address (which must be valid during the above transi- tions) and AO to A5 specify which bytes within the page are to be written. Note that the bytes may be loaded in any order and may be changed within the same load period. Hardware Chip Erase All of the memory locations on the MEM832 can be erased in 10 ms by placing 12.0V+0.5V onto OE and controtling WE and CS to follow the Chip Erase timing characteristics. This function will operate even if the device is in Software Data Protection Mode as ex- plaiaed later. DATA Polling inorder to detect the end of a Write Cycle, two methods are provided. During a Write operation (Byte or Page) an attempt to Read the device will result in the compie- ment of the written data appearing on D7. Once the Write Cycle is complete true data appears on the outputs and the next Write Cycle may begin. TOGGLE bit In addition to DATA polling, another method is provided to determine the end of a Write Cycle. During a write operation successive attempts to read data will result in D6 toggling between 1 and 0. Once a write is complete, this toggling will stop and valid data will be read. Operating Modes The table below shows the logic inputs required to control the operating modes of the MEM832. MODE cs | O | WE | ouTPUTS Read 0 0 1 Data Out Write (1) 0 1 0 | Datan Standby 1 x X | Floating Write Inhibit xX xX 1 x 0 x Output Disable x 1 X | Floating Chip Erase 0 Vu 0 Floating 1=V,, O=V, X=Don'tcare V, = 12.0V+40.5V Note: (1) Refer to AC Programming Waveforms Software Data Protection The MEM832 can be automatically protected during power-up and power-down without the need for exter- nal circuits by employing the software data protect feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the MEM832 is also protected against inadvertent and accidental writes in that, the software algorithm must be issued prior to writing additional data to the device.