Advance I]|CATALYST SEMICONODUCTOAR CAT28F020/CAT28F020I 2 Megabit CMOS FLASH MEMORY FEATURES m Fast Read Access Time: 120/150/200 ns m Low Power CMOS Dissipation: ~Active: 30 mA max (CMOS/TTL levels) -Standby: 1 mA max (TTL levels) ~Standby: 100 L.A max (CMOS levels) = High Speed Programming: ~-10 uS per byte 4 Sec Typ Chip Program m@ 12.0V + 5% Programming and Erase Voltage @ Stop Timer for Program/Erase On-Chip Address and Data Latches mg JEDEC Standard Pinouts: 32 pin DIP 32 pin PLCC 32 pin TSOP (8 x 14; 8 x 20) m 10,000 Program/Erase Cycles g 10 Year Data Retention m@ Electronic Signature DESCRIPTION The CAT28F020/CAT28F0201 is a high speed 256K x 8 bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-sys- tem or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 1 second. It is pin and Read timing compatible with standard EPROM and EPROM devices. Programming and Erase are performed through an operation and verify algo- rithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation. The CAT28F020/CAT28F0201 is manufactured using Catalysts advanced CMOS floating gate technology. It is designed to endure 10,000 progranverase cycles and has a data retention of 10 years. The device is available in JEDEC approved 32 pin plastic DIP, 32 pin PLCC or 32 pin TSOP packages. BLOCK DIAGRAM VOp-VOz VO BUFFERS | ERASE VOLTAGE 4 SWITCH WE >] | COMMAND PROGRAM VOLTAGE | | == = DATA | [ SENSE | REGISTER [ SWITCH CE, OE LOGIC |LaTCH] | AMP cE 4? OE 7 Hs >| Y-GATING & | Y-DECODER - 4d w A AG 2,097,152 BIT fons? tr MEMORY Q X-DECODER ARRAY << VOLTAGE VERIFY 5115 FHD Fo SWITCH 1992 by Catalyst Semiconductor, Inc. 8-73 | TD sis Characteristics subject to change without noticeCAT28F020/CAT28F0201 Advance PIN CONFIGURATION PIN FUNCTIONS DIP Package PLCC Package Pin Name Type Function Vpp Cet 32 1 Vcc Ao-A17 Input Address Inputs for AwO]2 31 [WE memory addressing Ais() S$ 30 FA At7 VOo-VO7 | WO | Data Input/Output Ayo] 4 29 1 Ai4 Az 1 Ai4 , A715 28 DA As Aig CE Input Chip Enable Ae 6 27 FAs As P] Ag OE Input Output Enable As(]7 26 [9 Ag Aa [1 Ag = AgU] 8 25 1 Ay Ag 7) Any E input Write Enable A30}9 24 [10E Ao [7 OF V V ce oltage Suppl A210 23 FI Ato Ay A Aro g pply A, 11 22 [CE Ao 7 CE Vss Ground ion q a0 Non Oo 1/07 Vpp Program/Erase of 13 20 F106 Voltage Supply 0, C14 19 [FD I/Os Oot) 15 18 (0 Og Vss] 16) 17 (103 5115 FHO Fot TSOP Package (Standard Pinout) Ay, O41 32 Ft OE Ag C2 31 Ao Ag 3 30 Fra CE Ay3 OO4 29 FI 1/07 Aig 5 28 [23 1/0g A17 Co6 27 FO l/s WE C7 26 FE 1/04 Voc [48 25 PC 1/03 Vpp [O49 24 FS Vss Aye (2H 10 23 F302 Aig C11 22 F35 1/0, Ajo (1412 21 7 1/09 A7 (413 20 EE Ag Ag 14 19 Ay As G15 18 FI Ag Ag 1116 17 Ag TSOP Package (Reverse Pinout) 6E coi 32 FS Ay} Aig G2 31 FT Ag cE cr3 30 FT Ag VO7 CO4 29> Aig Og Car 5 28 FI Ay O05 TT6 27 FO Ai7 O4q C7 26 FO WE O03 C148 25 FO Vcc Vss a9 24 FS Vpp Vp 10 233 Aig VO, D1 22 FO Ais VO9 C4412 21 FOS Ajo Ag 413 20 Fr Az Ay 4414 19 5 Ag Ap 1415 18 FOS As A3 (1116 17 Ag 5115 FHD F14 8-74Advance ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................0.... 55C to +95C Storage Temperature .....0..... ce 65C to +150C Voltage on Any Pin with Respect to Ground 00... -2.0V to +Vcc + 2.0V Voltage on Pin Ag with Respect to Ground ooo... -2,0V to +13.5V Vpp with Respect to Ground during ProgranVErase 0.0.0... ~2.0V to +14.0V Vec with Respect to Ground ooo... -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) .oosccceccccccsessseresseessene 1.0W Lead Soldering Temperature (10 secs) ............... 300C Output Short Circuit Current) oo 100 mA RELIABILITY CHARACTERISTICS CAT28F020/CAT28F0201 *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Symbol Parameter Min. Max. Units Test Method Nenp) Endurance 1K, 10K Cycles/Byte | MIL-STD-883, Test Method 1033 Tor) Data Retention 10 Years MIL-STD-883, Test Method 1008 Vzap) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH4) Latch-Up 100 mA JEDEC Standard 17 CAPACITANCE Ta = 25C, f = 1.0 MHz Limits Symbol Test Min Max. Units Conditions Cin) Input Pin Capacitance 6 pF Vin = OV Cour) Output Pin Capacitance 10 pF Vout = OV Cvpp@) Vpp Supply Capacitance 25 pF Vpp = OV Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is Voc +0.5V, which may overshoot to Vcc + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to Voc +1V.CAT28F020/CAT28F0201 D.C. OPERATING CHARACTERISTICS CAT28F020 Ta = 0C to +70C, Voc = +5V +10%, unless otherwise specified. CAT28F0201 Ta = 40C to +85C, Voc = +5V +10%, unless otherwise specified. Advance Limits Symbol Parameter Min. Max. Unit Test Conditions Iu Input Leakage Current +1.0 pA Vin = Vcc or Vss Voc = 5.5V, OE = Vin ILo Output Leakage Current +10 pA Vout = Vec or Vss, Vec = 5.5V, OE = Vin isBi Vcc Standby Current CMOS 100 pA CE = Vcc +0.5V, Voc =5.5V Isp2 Vcc Standby Current TTL 1.0 mA CE = Vin, Vcc = 5.5V leet Vcc Active Read Current 30 mA Vcc = 5.5V, CE = Vit, lout = OmA, f = 6 MHz icc) | Voc Programming Current 15 mA Voc = 5.5V, Programming in Progress lcca) | Voc Erase Current 15 mA Vec = 5.5V, Erasure in Progress Icca) | Voc Prog./Erase Verify Current 15 mA Vpp = VppH, Program or Erase Verify in Progress Ipps Vepp Standby Current +10 pA Vepp = Vpec lped Vep Read Current 200 pA Vep = VeprPH Ippo) | Vpp Programming Current 30 mA Vpp = VeppH, Programming in Progress Ipp3) Vpp Erase Current 30 mA Vec = 5.5V, Erasure in Progress Ipp43) | Vpp Prog./Erase Verify Current 5.0 mA Vpp = VpeH, Program or Erase Verify in Progress Vit Input Low Level TTL -0.5 0.8 Vv Vitc Input Low Level CMOS -0.5 0.8 Vv Vou Output Low Level 0.45 Vv lo. = 5.8mA, Vcc = 4.5V Vin Input High Level TTL 2.0 Vec+0.5 Vv Vine Input High Level CMOS 0.7 Vcc | Vcc+0.5 Vv Vou Output High Level TTL 2.4 Vv lon = -2.5mA, Vcc = 4.5V Vou Output High Level CMOS 0.85 Vcc Vv oH = 2.5mA, Vcc = 4.5V Von2 Output High Level CMOS Vcc-0.4 Vv lon = -400HA, Vcc = 4.5V Vip Ag Signature Voltage 11.4 13.0 Vv Ag = Vip lio Ag Signature Current 200 pA Ag = Vip Vio Vcc Erase/Prog. Lockout Voltage 2.5 Vv Note: (3) This parameter is tested initially and after a design or process change that affects the parameter. 8-76Advance CAT28F020/CAT28F020I SUPPLY CHARACTERISTICS Limits Symbol Parameter Min Max. Unit Vec Vcc Supply Voltage 4.5 5.5 Vv VePL Vpp During Read Operations 0 6.5 Vv VpPH Vpe During Read/Erase/Program 11.4 12.6 V A.C. CHARACTERISTICS, Read Operation CAT28F020 Ta = 0C to +70C, Voc = +5V +10%, unless otherwise specified. CAT28F020I Ta = ~40C to +85C, Voc = +5V +10%, unless otherwise specified. 28F020-12 28F020-15 28F020-20 28F020I-12 | 28F020I-15 | 28F0201-20 Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max.| Unit tre Read Cycle Time 120 150 200 ns tce CE Access Time 120 150 200 ns tacc Address Access Time 120 150 200 ns toe OE Access Time 50 55 60 ns tou Output Hold from Address OE/CE Change 0 ns to.z8X) | OE to Output in Low-Z ns t.z2)9) CE to Output in Low-Z 0 0 ns tor3)6) OE High to Output High-Z 30 35 40 ns teHazX8) | CE High to Output High-Z 55 55 55 ns twa.) Write Recovery Time Before Read 6 6 6 us Figure 1. A.C. Testing Input/Output Waveform(6)(7)(8) 24V 0.45 V INPUT PULSE LEVELS REFERENCE POINTS 5108 FHD Fo3. Figure 2. A.C. Testing Load Circuit (example) DEVICE UNDER TEST I 1.3V 1N914 OUT C= 100 pF C, INCLUDES JIG CAPACITANCE This parameter is tested initially and after a design or process change that affects the parameter. Output floating (High-Z) is defined as the state where the extemal data line is no longer driven by the output buffer. Input Rise and Fall Times (10% to 90%) < 10 ns. Input Pulse Levels = 0.45V and 2.4V. Input and Output Timing Reference = 0.8V and 2.0V. Low-Z is defined as the state where the extemal data may be driven by the output buffer but may not be valid. 5108 FHD Fos 8-77CAT28F020/CAT28F020I Advance A.C. CHARACTERISTICS, Program/Erase Operation CAT28F020 Ta = 0C to +70C, Voc = +5V +10%, unless otherwise specified. CAT28F0201 Ta = 40C to +85C, Voc = +5V +10%, unless otherwise specified. 28F020-12 28F020-15 28F020-20 28F020I-12 28F0201-15 28F020I-20 Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max. | Unit twc Write Cycle Time 120 150 200 ns tas Address Setup Time 0 0 0 ns taH Address Hold Time 60 60 75 ns tos Data Setup Time 50 50 50 ns {DH Data Hold Time 10 10 10 ns tes CE Setup Time 0 0 0 ns tou CE Hold Time 0 0 0 ns twp WE Pulse Width 60 60 60 ns tweH WE High Pulse Width 20 20 20 ns twewHi) Program Pulse Width 10 10 10 us twewHe""?) Erase Pulse Width 9.5 9.5 9.5 ms tweet Write Recovery Time Before Read 6 6 6 us tGHWL Read Recovery Time Before Write 0 0 0 us tVPEL Vpp Setup Time to CE 100 100 100 ns ERASE AND PROGRAMMING PERFORMANCE(9) 28F020-12 28F020-15 28F020-20 28F020I-12 28F0201-15 28F0201-20 Parameter Min. | Typ. | Max. | Min. | Typ. | Max. | Min. | Typ. | Max.) Unit Chip Erase Time(2)(14) 1.0 10 1.0 10 1.0 30 sec Chip Program Time(2)(13) 4 25 4 25 4 25 sec Note: (10) Please refer to Supply characteristics for the value of Vppy, and Vpp,. The Vpp supply can be either hardwired or switched. If Vpp is switched, Vpp_ can be ground, less than Vcc + 2.0V or a no connect with a resistor tied to ground. (11) Program and Erase operations are controlled by internal stop timers. (12) Typicals are not guaranteed, but based on characterization data. Data taken at 25C, 12.0V Vpp. (13) Minimum byte programming time (excluding system overhead) is 16 1s (10 kts program + 6 us write recovery), while maximum is 400 ps/ byte (16 j1s x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algonthm since most bytes program significantly faster than the worst case byte. (14) Excludes 00H Programming prior to Erasure. 8-78Advance CAT28F020/CAT28F020! FUNCTION TABLE('5) Pins Mode CE OE WE Vep vo Notes Read Vit Vit Vin VPPL Dout Output Disable Vit Vin Vin X High-Z Standby Vin X X VpPL High-Z Signature (MFG) VIL Vit Vin X 31H Ao = Vit, Ag = 12V Signature (Device) Vit Vit Vin X BDH Ao = Vit, Ag = 12V Program/Erase Vit Vin Vit VPPH Din See Command Table Write Cycle Vit Vin Vit VpPH Din During Write Cycle Read Cycle Vit Vi VIH VPPH Dout During Write Cycle WRITE COMMAND TABLE Commands are written into the command register in one or two write cycles. The command register can be altered only when Vpp is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch addresses and data required for programming and erase operations. Pins First Bus Cycle Second Bus Cycle Mode Operation Address Din Operation Address Din Dout Set Read Write X 00H Read Any Dout Read Sig. (MFG) Write 90H Read 00 31H Read Sig. (Device) Write X 90H Read 01 BDH Erase Write xX 20H Write X 20H Erase Verify Write X AOH Read Xx Dout Program Write X 40H Write AIN Din Program Verify Write Xx COH Read x Dout Reset Write X FFH Write X FFH Note: (15) Logic Levels: X = Logic Do not care (Vin, Vic, VepL, VepH) 8-79CAT28F020/CAT28F0201 READ OPERATIONS Read Mode A Read operation is performed with both CE and OE low and with WE high. Vpp can be either high or low, however, if Vpp is high, the Set READ command has to be sent before reading data (see Write Operations). The data retrieved from the I/O pins reflects the contents of the memory location corresponding to the state of the 18 address pins. The respective timing waveforms for the read operation are shown in Figure 3. Refer to the AC Read characteristics for specific timing parameters. Signature Mode The signature mode allows the user to identify the IC manufacturer and the type of device while the device resides in the target system. This mode can be activated in either of two ways; through the conventional method of applying a high voltage (12V) to address pin Ag or by sending an instruction to the command register (see Write Operations). Advance The conventional mode is entered as a regular READ mode by driving the CE and OE pins low (with WE high), and applying the required high voltage on address pin Ag while all other address lines are held at Vic. A Read cycle from address OOOOH retrieves the binary code for the IC manufacturer on outputs I/Oo to I/O7: CATALYST Code = 00110001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/Oo to 1/07. 28F020/28F 020! Code = 1011 1101 (BDH) Standby Mode With CE at a logic-high level, the CAT28F020/ CAT28F0201 is placed in a standby mode where most of the device circuitry is disabled, thereby substantially reducing power consumption. The outputs are placed in a high-impedance state. Figure 3. A.C. Timing for Read Operation POWER UP STANDBY DEVICE AND ADDRESS SELECTION ADDRESSES E (E) DATA (/O) tetax orz) (tz) tavav (acc) ADDRESS STABLE OUPUTS ENABLED DATA VALID STANDBY POWER DOWN tavav (Rc) 'gHaz (pF) 'eLav Moe) teLav (ce) HIGH-Z OUTPUT VALID 5108 FHD Fos 8-80Advance WRITE OPERATIONS The following operations are initiated by observing the sequence specified in the Write Command Table. Read Mode The device can be put into a standard READ mode by initiating a write cycle with OOH on the data bus. The subsequent read cycles will be performed similar to a standard EPROM or E?7PROM Read. CAT28F020/CAT28F0201 Signature Mode Analternative method for reading device signature (see Read Operations Signature Mode), is initiated by writing the code 90H into the command register while keeping Vep high. A read cycle from address 0000H with CE and OE low (and WE high) will output the device signature. CATALYST Code = 00110001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/OQp to I/O7. 28F020/28F020! Code = 1011 1101 (BDH) Figure 4. A.C. Timing for Erase Operation Voc POWER-UP & STANDBY SETUP ERASE COMMAND ERASE COMMAND ADDRESSES CE (E) DATA (I/O) Voc Vpp ERASING ERASE VERIFY COMMAND ERASE VERIFICATION Vocg POWER-DOWN/ STANDBY VALID DATA OUT 5108 FHD F11 8-81CAT28F020/CAT28F020I Advance Erase Mode During the first Write cycle, the command 20H is written into the command register. In order to commence the erase operation, the identical command of 20H has to be written again into the register. This two-step process ensures against accidental erasure of the memory con- tents. The final erase cycle will be stopped at the rising edge of WE, at which time the Erase Verify command (AOH) is sent to the command register. During this cycle, the address to be verified is sent to the address bus and latched when WE goes high. An integrated stop timer allows for automatic timing control over this operation, eliminating the need for a maximum erase timing speci- fication. Refer to AC Characteristics (Program/Erase) for specific timing parameters. TIMING PARAMETER SYMBOLS Standard JEDEC Standard JEDEC tas TAVWL tiz teLax taH twLax toe tatav tce tELav toLz taLax tcH tWHEH tre tavav {cs teLWL twe tavav tor taHaz twp {WLWH tbH tWHDX twPH tWHWL tos tovWH 8-82Advance CAT28F020/CAT28F020I Figure 5. Chip Erase Algorithm('6) BUS START ERASURE OPERATION| COMMAND COMMENTS APPLY Vopy Vpp RAMPS TO VppH (OR Vpp HARDWIRED) ! ALL BYTES SHALL BE PROGRAM ALL PROGRAMMED TO 00 BYTES TO 00H STANDBY BEFORE AN ERASE J OPERATION ADDRESS INITIALIZE ADDRESS INITIALIZE PLSCNT co PLSCNT = PULSE COUNT ACTUAL ERASE SETUP DOMIMAND WRITE ERASE NEEDS 10ms PULSE, | DATA = 20H MOMMA WRITE ERASE DATA = 20H TIME OUT toms WAIT WRITE ERASE WRITE ERASE ADDRESS jonah VERIFY VERIFY COMMAND VERIFY = 20h STOPS ERASE OPERATION TIME OUT 6us walt INCREMENT J ADDRESS READ DATA READ READ BYTE TO FROM DEVICE VERIFY ERASURE NO NO INC PLSCNT STANDBY COMPARE OUTPUT TO FF = 3000 ? INCREMENT PULSE COUNT YES YES le} LAST ADDRESS? YES DATA = 00H NO MMAND WRITE READ RESETS THE REGISTER 1 FOR READ OPERATION Vpp RAMPS TO Vpp. APPLY Vpp,_ APPLY Vpp,. STANDBY (OR Vp HAROWIRED) ERASURE ERASE COMPLETED ERROR Note: 5108 FHD F10 (16) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device. 8-83CAT28F020/CAT28F020! Advance Erase-Verify Mode The Erase-verify operation is performed on every byte after each erase pulse to verify that the bits have been erased. Programming Mode The programming operation is initiated using the pro- gramming algorithm of Figure 7. During the first write cycle, the command 40H is written into the command register. During the second write cycle, the address of the memory location to be programmed is latched on the falling edge of WE, while the data is latched on the rising edge of WE. The program operation terminates with the next rising edge of WE. An integrated stop timer allows for automatic timing control over this operation, eliminat- ing the need for a maximum program timing specifica- tion. Refer to AC Characteristics (Program/Erase) for specific timing parameters. Figure 6. A.C. Timing for Programming Operation Veco POWER-UP SETUP PROGRAM LATCH ADDRESS & STANDBY COMMAND & DATA PROGRAM VERIFY PROGRAM V, VERIFICATION POWER-DOWN/ STANDBY PROGRAMMING COMMAND ADDRESSES we DATA (iO) DATA IN Vec Vpp twe VALID DATA OUT 5108 FHD Fo7 8-84Advance CAT28F020/CAT28F020I Program-Verify Mode A Program-verify cycle is performed to ensure that all bits have been correctly programmed following each byte programming operation. The specific address is already latched from the write cycle just completed, and stays latched until the verify is completed. The Program- verify operation is initiated by writing COH into the command register. An internal reference generates the necessary high voltages so that the user does not need to modify Vcc. Refer to AC Characteristics (Program/ Erase) for specific timing parameters. TIMING PARAMETER SYMBOLS Standard JEDEC Standard JEDEC tas tAVWL tiz teLax {AH tWLAX toe teLav {ce fELaV toLz teLax tcH tWHEH tac tavav tcs tELWL twe tavav tor taHaz twp twLwH tbH tWHDX twPH tWHWL tos tbvwHconvert: error while loading shared libraries: libMagickCore-7.Q16HDRI.so.7: failed to map segment from shared object: Cannot allocate memoryAdvance CAT28F020/CAT28F0201 Abort/Reset An Abort/Reset command is available to allow the user reset operation can interrupt at any time in a program or to safely abort an erase or program sequence. Two erase operation and the device is reset to the Read consecutive program cycles with FFH on the data bus Mode. will abort an erase or a program operation. The abort/ Figure 8. Alternate A.C. Timing for Program Operation Voc POWER-UP SETUP PROGRAM LATCH ADDRESS PROGRAM PROGRAM = Vcc POWER-DOWN/ & STANDBY COMMAND & DATA VERIFY VERIFICATION STANDBY PROGRAMMING COMMAND VVVVVVSAERRR RN) appresses XXXXEXXXXXKKN XOXO RED }+ lwo <} we + two + 'ao 4 'AVEL 'ELAX | 'WLEL >| + 'EHWH t e WEL >| EHWH tEHWH >| WLEL be as } EG) taHEL ht tEHEH teHGL > ? cem ) A, & Ff - Y A teHaz r SENG Ky Ky 'ELEH > tet teen 'ELEH -> toe > hem| TEHDX eHDX r tEHDX 'DVEH +> be tOyEH toveH toLz> HIGH-Z DATA IN DATAIN DATA(WO) sf 2 40H po CDATAIN 4 ceoy VALID LZ Data OUT CE > OV Voc a7 YL OV be] typEL Vv Vpp YPPH } \ VPPL 5108 FHD Foo. 8-87CAT28F020/CAT28F020I Advance POWER UP/DOWN PROTECTION The CAT28F020/CAT28F020! offers protection against inadvertent programming during Vpp and Vcc power transitions. When powering up the device there is no power-on sequencing necessary. In other words, Vpp and Vcc may power up in any order. Additionally Vpp may be hardwired to Vppy independent of the state of Vcc and any power up/down cycling. The internal com- mand register of the CAT28F020/CAT28F0201 is reset to the Read Mode on power up. POWER SUPPLY DECOUPLING To reduce the effect of transient power supply voltage spikes, it is good practice to use a 0.1nF ceramic capacitor between Vcc and Vss and Vpp and Vss. These high-frequency capacitors should be placed as close as possible to the device for optimum decoupling. TIMING PARAMETER SYMBOLS Standard JEDEC twe tavav toLz taLax tz teLax tcE teLav toe teLav tor taHazAdvance CAT28F020/CAT28F020I ALTERNATE CE-CONTROLLED WRITES 28F020-12 28F020-15 28F020-20 28F020I-12 28F0201-15 28F020I-20 Symbol Parameter Min. | Max. | Min. ; Max. | Min. | Max. | Unit tavav Write Cycle Time 120 150 200 ns taVEL Address Setup Time 0 0 0 ns tELAX Address Hold Time 80 80 95 ns tDVEH Data Setup Time 50 50 50 ns tEHDX Data Hold Time 10 10 10 ns teHeL Write Recovery Time Before Read ps tGHEL Read Recovery Time Before Write HS tWLEL WE Setup Time Before CE 0 0 0 ns tEHWH Write Enable Hold Time 0 0 0 ns tELEH Write Pulse Width 70 70 80 ns tEHEL Write Pulse Width High 20 20 20 ns tvPEL Vpp Setup Time to CE Low 1.0 1.0 1.0 us 8-89