Datasheet 01/09/2012
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Viking Technology
COMPACT FLASH
Datasheet
Datasheet 01/09/2012
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Ordering Information: Viking Compact Flash
Viking High Performance Compact Flash Ordering Information
Part Number Raw
Capacity
Unformatted
Capacity
(bytes)
SLC Device
Density Form
Factor
VRFCF10128Dx6 128MB 127,401,984 1Gb Type 1
VRFCF10256Dx6 256MB 254,803,968 1Gb Type 1
VRFCF10512Dx9 512MB 531,062,784 2Gb Type 1
VRFCF11024Dx7 1GB 1,046,126,592 4Gb Type 1
VRFCF12048DxG 2GB 2,044,256,256 8Gb Type 1
VRFCF14096DxH 4GB 4,100,898,816 16Gb Type 1
VRFCF18192DxK 8GB 8,183,734,272 32Gb Type 1
VRFCF1016GDxK 16GB 16,438,173,700 32Gb Type 1
VRFCF1032GDxN 32GB 32,782,417,920 64Gb Type 1
Notes:
1. “x” is temperature: C = Commercial Temp, I = Industrial Temp
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Table of Contents
1 INTRODUCTION 6
1.1 Features 6
1.2 Performance 7
1.3 CHS Parameters 8
1.4 Block Diagram 8
1.5 Mechanical Information 9
1.6 Interface 10
1.6.1 Host Interface 10
2 CONNECTOR PINS 11
2.1 Connector Pin Assignments 11
2.2 Pin Function Description 11
3 PRODUCT SPECIFICATIONS 14
3.1 Absolute Maximum Ratings 14
3.2 DC Operating Conditions and Characteristics 15
3.3 Environmental Specifications 16
3.4 Reliability & Retention 16
3.5 Capacitance 16
3.6 AC Characteristics 16
3.6.1 Power-on Timing 16
3.6.2 Attribute Memory Read Timing 18
3.6.3 Attribute Memory Write Timing 18
3.6.4 Common Memory Read Timing 20
3.6.5 Common Memory Write Timing 21
3.6.6 I/O Mode Read Timing 22
3.6.7 I/O Mode Write Timing 23
3.6.8 True IDE Mode PIO Read/Write Timing 24
3.6.9 True IDE Multiword DMA Read/Write Timing 25
3.6.10 Ultra DMA AC Characteristics 26
3.6.11 Ultra DMA Data Burst Timing Descriptions 27
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3.6.12 CF-ATA Command Support 28
3.7 Capacity Information 29
3.7.1 True IDE Mode 29
3.7.2 PCMCIA Mode (I/O and Memory Modes) 30
3.8 Identify Drive Parameter 30
3.9 SMART Support 33
3.9.1 SMART Enable Operations 34
3.9.2 SMART Disable Operations 34
3.9.3 SMART Enable/Disable Attribute Autosave 34
3.9.4 SMART Read Data 36
3.9.5 SMART Read Attribute Thresholds 39
3.9.6 SMART Return Status 40
3.9.7 SMART Read Remap Data 41
3.9.8 SMART Read Wear Level Data 41
4 CERTIFICATIONS AND COMPLIANCE 43
5 REFERENCES 43
6 REVISION HISTORY 43
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Table of Tables
Table 1-1: CF Card Read/Write Performance________________________________________ 7
Table 1-2: CHS Parameters _____________________________________________________ 8
Table 2-1: Connector Pin Assignments____________________________________________ 11
Table 2-2: Pin Function Description ______________________________________________ 11
Table 3-1: Absolute Maximum Ratings ____________________________________________ 14
Table 3-2: DC Operating Condition s an d Characteristics ______________________________ 15
Table 3-3: Environmental Specification s___________________________________________ 16
Table 3-4: CF Card Reliability and Retention _______________________________________ 16
Table 3-5: Capacitance________________________________________________________ 16
Table 3-6: Power-on Timing ____________________________________________________ 16
Table 3-7: Attribute Memory Read Timi ng__________________________________________ 18
Table 3-8: Attribute Memory Write Timing__________________________________________ 18
Table 3-9: Common Memory Read Timing _________________________________________ 20
Table 3-10:Comm on Memory Write Timing_________________________________________ 21
Table 3-11: I/O Mode Read Timing_______________________________________________ 22
Table 3-12: I/O Mode Write Tim ing_______________________________________________ 23
Table 3-13: True IDE Mode PIO Read/Write Timing (Modes 0-6)________________________ 24
Table 3-14: True IDE Multiword DMA Read/Write Tim ing (Modes 0-4)____________________ 25
Table 3-15: Ultra DMA AC Characteristics _________________________________________ 26
Table 3-16: Ultra DMA Data Burst Timing De scriptions _______________________________ 27
Table 3-17: CF-ATA Command Support___________________________________________ 28
Table 3-18: True IDE Mode_____________________________________________________ 29
Table 3-19: PCMCIA Mode (I/O and Memory Modes) ________________________________ 30
Table 3-20: Identify Drive Parameter _____________________________________________ 30
Table 3-21: Identify Drive Parameter Table in PCMCIA mode showing word differences _____ 33
Table 3-22: Identify Drive Parameter Table in PCMCIA mode showing word differences _____ 33
Table 3-23: Supported SMART Commands determined by F eature Register value__________ 33
Table 4-1: Device Certificat ions _________________________________________________ 43
Table of Figures
Figure 1-1: Functional Block Diagram______________________________________________ 8
Figure 1-2: Dimensions_________________________________________________________ 9
Figure 3-1: Power On RESE T Timing _____________________________________________ 18
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1 Introduction
The Viking CompactFlash (CF) card is a multi-channel, high-performance
solution for a wide array of storage applications. Available in capacity ranges
from 128MB to 16GB with a standard CompactFlash interface, system designers
have an easy way to add small-form factor, reliable storage to any system at a
fraction of the size of a hard disk drive.
Viking’s rugged industrial designed SSD’s offer the highest flash storage
reliability and performance in harsh environments such as shock, vibration,
humidity, altitude, ESD, and extreme temperatures. Viking SSD’s meet JEDEC
JESD22 standards and pass numerous qualifications including MIL-STDs and
NEBS.
Viking can also provide specialized services to OEMs designing customized
hardware and systems by offering:
Locked BOM control with customer product change notification (PCN)
Pre-installed software, custom software imaging and ID strings
Custom packaging and labeling
Comprehensive supply-chain management
Customer specified testing
30K volt ESD protection
Conformal coating
Localized Field Application Engineering for complete pre and post sale
technical support
1.1 Features
The main features of Viking CompactFlash memory controller are:
Dual channel flash interface
Full support for SLC NAND flash memories
Built-in ATA / PC card / CompactFlash Interface
Host data transfer rate in PIO mode 6 or MDMA mode 4 up to 25
MByte/sec
Host data transfer rate in UDMA mode 4 up to 66 MByte/s
Supports True-IDE mode
Patented power fail management
Embedded Reed-Solomon ECC, 4 symbols in a 512B sector
Advanced global wear leveling
Automatic power-down mode and sleep mode
Industrial and commercial temperature
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ESD protection
1.2 Performance
Table 1-1: CF Card Read/Write Performance
Parameter Size Value
Sequential Read 256K up to 42 MB/s
Sequential Write 256K up to 42 MB/s
Random Read 4K up to 3098 IOPS
Random Write 4K up to 23 IOPS
Note: 1) Measured using IOMETER 2008.
2) Performance may vary under extreme temperatures.
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1.3 CHS Parameters
Table 1-2: CHS Parameters
Capacity
Logical
Block
Addresses
(LBA)
Cylinders (C)
(standard) Heads (H) Sectors/Track
(S)
128MB 248,832 486 16 63
256MB 497,664 972 16 63
512MB 1,037,232 1,029 16 63
1GB 2,043,216 2,027 16 63
2GB 3,992,688 3,961 16 63
4GB 8,009,568 7,946 16 63
8GB 15,983,856 15,857 16 63
16GB 32,105,808 *31,851 16 63
32GB 64,028,160 *63520 16 63
Note: The unformatted capacity of the card may be less than the perceived or stated capacity on the label. Please use the
LBA count in this table for reference.
*16,383 is the max Cylinder size for True IDE mode. Use total LBA to calculate size when using True IDE mode.
1.4 Block Diagram
Figure 1-1: Functional Block Diagram
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1.5 Mechanical Information
Figure 1-2: Dimensions
Note: All dimensions are in inches.
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Note: All dimensions are in millimeters.
1.6 Interface
1.6.1 Host Interface
PCMCIA 2.1, PC Card ATA, CF 3.0, CF 4.1 standard compatible
ATA-6 standard compatible in True-IDE mode
Memory mapped or I/O operation
Fast ATA host-to-buffer transfer rates supporting PIO mode 6, MDMA
mode 4, UDMA mode 4 in True-IDE mode
Automatic sensing of PCMCIA or True-IDE host interface mode
Four integrated 8 Kbyte Sector Buffers and 256 Byte PCMCIA Attribute
Memory
PCMCIA Configuration Option Register, Card Configuration and Status
Register and Pin Replacement Register support
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2 Connector Pins
2.1 Connector Pin Assignments
Table 2-1: Connector Pin Assignments
Pin Signal Name
Mem / IO / True IDE Pin Signal Name
Mem / IO / True IDE
1 GND 26 #CD1
2 D3 27 D11
3 D4 28 D12
4 D5 29 D13
5 D6 30 D14
6 D7 31 D15
7 #CE1/#CE1/#CS0 32 #CE2/#CE2/#CS1
8 A10 33 #VS1
9 #OE/#ATA SEL 34 #IORD
10 A9 35 #IOWR
11 A8 36 #WE
12 A7 37 RDY/DREQ/HINT
13 VCC 38 VCC
14 A6 39 CSEL
15 A5 40 VS2
16 A4 41 RESET/RESET/#RESET
17 A3 42 #WAIT/#WAIT/IORDY
18 A2 43 #INPACK
19 A1 44 #REG
20 A0 45 BVD2/#SPKR/#DASP
21 D0 46 BVD1/#STSCHG/#PDIAG
22 D1 47 D8
23 D2 48 D9
24 WP/#IOIS16/#IOCS16 49 D10
25 #CD2 50 GND
2.2 Pin Function Description
Table 2-2: Pin Function Description
Signal PIN
Numbers (Mode)
Function
Type
(Note
1) Description
A0 ~ A10 8, 10-12,
14-20
(All)
Address Input
In I/O and Memory modes, these are the
Host Address lines that select the I/O port
address registers or the memory mapped
port address registers, and the control and
status registers. In True IDE mode, only A0
~ A2 are used to select the control, status
and data register; A3 ~ A10 are not used.
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Signal PIN
Numbers (Mode)
Function
Type
(Note
1) Description
#ATA SEL 9 (IDE)
ATA Select Input Grounded by host to enable True IDE
Mode.
BVD1 ~
BVD2 45, 46
(Memory)
Battery
Voltage
Detect
Output Always asserted (high) since a battery is
not used in this card.
CD1 ~ CD2 25, 26 (All)
Card Detect Output
Internally grounded in card to signal host
that the card is fully inserted into the
socket.
CE1 ~ CE2 7, 32 (I/O, Memory)
Card Enable
Input
ST,PU
Selects the card and indicates to the
controller whether a byte or word operation
is being performed. #CE2 always accesses
the odd byte of the word; #CE1 accesses
the even or odd byte of the word
depending on the status of AO and #CE2.
CS0 ~ CS1 7, 32 (IDE)
Chip Select Input
#CS0 selects the ATA Command Block
Registers; #CS1 selects the ATA Control
Block Registers.
CSEL 39 (IDE)
Cable Select
Input
PU
Configures the drive as a Master or Slave.
If the signal is inactive (low), the drive is
configured as a Master. If the pin is open,
the drive is configured as a
slave.
D0 ~ D15
2-6, 21-
23, 27-
31, 47,
48
(All)
Host Data Bits
Input/
Output
These bi-directional signals carry the data,
commands, and status information
between the host and the controller.
DASP 45
(IDE)
Active/Slave
Present
Input
PU Device active / Slave Present signal.
DREQ 37 (IDE)
DMA Request Output DMA request
HINT 37
(IDE)
Interrupt
Request
Output Interrupt Request to the Host (active high).
INPACK 43
(I/O)
Input
Acknowledge
Output
Asserted when the card is selected and
can respond to an I/O cycle at the address
on the bus. This signal is used by the host
to control the enable of any input data
buffers between the card and host system
data bus.
IORDY 42
(IDE)
I/O Channel
Ready
Output
Active high I/O Channel Ready signal,
where a low signal indicates that the
controller is NOT ready and the host
should extend the cycle for the present
command.
IOCS16 24 (IDE)
16 bit I/O Output Indicates a 16-bit transfer is in progress on
the host bus. Open collector output.
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Signal PIN
Numbers (Mode)
Function
Type
(Note
1) Description
IOIS16 24 (I/O)
16 bit I/O Output
Selects the 16-bit port. A low signal
indicates that a 16-bit port is being
addressed or an odd-byte-only operation
can be performed at the addressed
port.
IORD 34
(I/O, IDE)
Input/Output
Read
Input
ST,PU
Clocks I/O data from the internal controller
to the card bus.
IOWR 35
(I/O, IDE)
Input/Output
Write
Input
ST,PU
Clocks I/O data from the card bus to the
internal controller.
OE 9
(I/O, Memory)
Output Enable
Input
ST,PU
This input signal is used to enable Memory
Read data from the memory card. In
Memory mode it is used to read data and
the CIS and Configuration registers. In I/O
mode, this signal is used to read the CIS
and Configuration registers only.
PDIAG 46
(IDE)
Passed
Diagnostics
Output
PU
Used between two drives to indicate that
the drive in Slave mode has passed
diagnostics.
REG 44
(All)
Register
Memory
Select
Input
ST,PU
In Memory mode, this input signal
distinguishes the register (attribute)
memory from the common memory. In I/O
mode, this signal must be asserted (low)
when the I/O address is on the bus. In True
IDE mode DMA Acknowledge is not used
in Compact Flash, and this signal should
be connected to VCC.
RESET 41
(I/O, Memory)
Reset
Input
PU
The controller is reset when this signal is
asserted (high), initializing the control and
status registers and aborting any command
in progress.
RESET 41 (IDE)
Reset
Input
PU
The controller is reset when this signal is
asserted (low), initializing the control and
status registers and aborting any command
in progress.
SPKR 45 (I/O)
Speaker Output Always low; speaker not supported by the
card.
STSCHG 46
(I/O)
Status
Changed
Input /
Output
Indicates a change in RDY/#BSY or Write
Protect states.
VS1 ~ VS2 33, 40
(All)
Voltage
Sense
Output
VS1 is grounded to indicate 3.3V read
capability. VS2 is not used and not
connected.
WAIT 42
(I/O, Memory)
Input/Output
Data Ready
Output
In Memory and I/O modes, this output is
driven by the controller to signal the host to
insert a delay before completing a memory
or I/O cycle.
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Signal PIN
Numbers (Mode)
Function
Type
(Note
1) Description
WE 36
(I/O, Memory)
Write Enable
Input
ST,PU
In Memory mode, strobes Memory Write
data into the card. In both Memory mode
and I/O mode, this signal is used for writing
the configuration register, in conjunction
with the #REG signal. Not used in IDE
mode, connect to VCC.
WP 24
(Memory)
Write Protect Output Indicates status of the card’s Write Protect
switch. Not used on this card.
VCC 38 Voltage
Supply Power These pins supply 3.3V or 5V to the
Compact Flash.
GND 50 Ground Gnd
These pins supply ground to the Compact
Flash.
Notes: 1. ST= Schmitt trigger input, PU= internal pullup, PD= internal pull down.
3 Product Specifications
3.1 Absolute Maximum Ratings
Table 3-1: Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply Voltage VCC -0.3 ~ 6.0 V
Input Voltage VIN GND - 0.5 ~ VCC + 0.5 V
Output Voltage VOUT GND - 0.5 ~ VCC + 0.5 V
Storage Temperature -40 to +85 °c
Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation
should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.
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3.2 DC Operating Conditions and Characteristics
Recommended operating conditions (Voltages referenced to GND, TA = 0 to
70°C)
Table 3-2: DC Operating Conditions and Characteristics
Parameter Symbol Min. Typical Max. Unit
VCC 3.135 3.3 3.465 V
Supply voltage VCC 4.5 5.0 5.5
Input high voltage VIH 2.0 V
Input low voltage VIL 0.8 V
Output high voltage VOH 2.4 V
Output low voltage VOH V
Output low voltage VOL 0.4 V
1 Flash
Device
0.5 + 0.05 mA
2 Flash
Devices
0.5 + 0.10 mA
@
3.3V,
25°C
4 Flash
Devices
0.5 + 0.20 mA
1 Flash
Device
0.5 + .05 mA
2 Flash
Devices
0.5 + 0.10 mA
Standby
Current @
5.0V,
25°C
4 Flash
Devices
ISTB
0.5 + 0.20 mA
1 Flash
Device
70 + 20 95 + 20 mA
2 Flash
Devices
70 + 40 95 + 40 mA
@
3.3V,
25°C
4 Flash
Devices
70 +
40.10
95 +
40.10
mA
1 Flash
Device
62.8 + 20 82.8 + 20 mA
2 Flash
Devices
62.8 + 40 82.8 + 40 mA
Operating
Current @
5.0V,
25°C
4 Flash
Devices
IOP
62.8 +
40.10
82.8 +
40.10
mA
Schmitt Trigger Input Low (3.3V/5V) VT- 0.8 1.2 V
Schmitt Trigger Input High (3.3V/5V) VT+ 1.4 1.6 2.0 V
Pull-up resistance Rpu 52.7 141 kohm
Pull-down resistance Rpd 47.5 172 kohm
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3.3 Environmental Specifications
Table 3-3: Environmental Specifications
Parameter Value
Operating Temperature (Commercial
Temp):
0 to 70c
Operating Temperature (Industrial
Temp):
-40 to 85c
Humidity (non-condensing): 5% to 95% non-condensing
Vibration (operating / non-operating) 20G peak, 20Hz-2000Hz, 4 cycles per direction (per
JEDEC JESD22 standard, method B103)
Shock (operating / non-operating) 1,500G peak, 0.5ms pulse duration, five (5) pulses per
each of six (6) directions (per JEDEC JESD22 standard,
method B110)
Altitude Up to 80,000 ft.
3.4 Reliability & Retention
Table 3-4: CF Card Reliability and Retention
Parameter Value
Data Reliability Bit Error rate 10E-15
Data Retention 10 Years
3.5 Capacitance
Table 3-5: Capacitance
Parameter Symbol Min. Max. Unit
Input capacitance Cin - 10 pF
Output capacitance Cout - 10 pF
3.6 AC Characteristics
Input rise and fall time requirements: Input rise and fall time should be 10ns or
less.
3.6.1 Power-on Timing
Table 3-6: Power-on Timing
Parameter Symbol Min. Max. Unit
Card Enable setup time tsu(VCC) - - ms
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VCC rise time 10% to 90% tpr 150 250 ms
Host RESET Hi-z hold time th(Hi-z
RESET)
- - ms
Host RESET width tw(RESET) - - us
Host RESET setup time tsu(RESET) - - ms
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Figure 3-1: Power On RESET Ti ming
3.6.2 Attribute Mem ory Read Timing
Table 3-7: Attribute Memory Read Timing
Parameter Symbol Min. Max. Unit
Read Cycle Time tc(R) 300 ns
Address Access Time ta(A) 300 ns
Card Enable Access Time ta(Cex) 300 ns
Output Enable Access Time ta(OE) 150 ns
Output Disable Time from Cex tdis(Cex) 100 ns
Output Disable Time from HOE tdis(OE) 100 ns
Address Setup Time tsu (A) 30 ns
Output Enable Time from Cex ten(Cex) 5 ns
Output Enable Time from OE ten(OE) 5 ns
Data Valid from Address Change tv(A) 0 ns
3.6.3 Attribute Mem ory Write Timing
Table 3-8: Attribute Memory Write Timing
Parameter Symbol Min. Max. Unit
Optional (requires bill of
material change)
tsu(VCC) = 25ms
tpr = N/A
th(Hi-z RESET) = 5ms
tw(RESET) = 10us
tsu(RESET)
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Write Cycle Time tc(W) 250 ns
Write Pulse Width tw(WE) 150 ns
Address Setup Time tsu(A) 30 ns
Data Setup Time (-WE) tsu(D-WEH) 80 ns
Data Hold Time th(D) 30 ns
Write Recovery Time trec(WE) 30 ns
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3.6.4 Comm on Memory Read Timing
Table 3-9: Common Memory Read Timing
Cycle Time Mode 250 ns 120ns 100ns 80ns
Parameter Symbol Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
Output Enable
Access Time
ta(OE) 125 60 50 45
Output Disable Time
from
tdis(OE) 100 60 50 45
Address Setup Time tsu(A) 30 15 10 10
Address Hold Time th(A) 20 15 15 10
CE Setup before OE tsu(CE) 0 0 0 0
CE Hold following
OE
th(CE) 20 15 15 10
Wait Delay Falling
from OE
tv(WT-
OE)
35 35 na1
Data Setup for Wait
Release
tv(WT) 0 0 na1
Wait Width Time2 tw(WT) 350 350 350 na1
Notes:
1. -WAIT is not supported in this mode
2. The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are
in nanoseconds. Dout signifies data provided by the CompactFlash Storage Card or CF+ Card to the system.
The -WAIT signal may be ignored if the -OE cycle to cycle time is greater than the Wait Width time. The Max
Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the
PCMCIA PC Card specification of 12μs but is intentionally less in this specification.
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3.6.5 Comm on Mem ory Write Timing
Table 3-10:Common Memory Write Timing
Cycle Time Mode 250 ns 120ns 100ns 80ns
Parameter Symbol Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
Data setup before
WE
tsu (D-
WEH)
80 50 40 30
Data hold following
WE
th(D) 30 15 10 10
WE pulse Width tw(WE) 150 70 60 55
Address setup Time tsu(A) 30 15 10 10
CE setup before
WE
tsu(CE) 0 0 0 0
Write recovery time trec(WE) 30 15 15 15
Address holdtime th(A) 20 15 15 15
CE Hold following
WE
Th(CE) 20 15 15 10
Wait delay falling from
WE
tv(WT-WE) na
1
WE high from wait
release
tv(WT) 0 0 0 na1
Wait Width Time2 tw(WT) 350 350 350 na1
Notes:
1. -WAIT is not supported in this mode
2. The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are
in nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card. The -WAIT
signal may be ignored if the -WE cycle to cycle time is greater than the Wait Width time. The Max Wait Width
time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA PC Card
specification of 12μs but is intentionally less in this specification.
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3.6.6 I/O Mode Read Tim i ng
Table 3-11: I/O Mode Read Timing
Cycle Time Mode 250ns 120ns 100ns 80ns
Parameter Symbol Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
Data delay after IORD td(IORD) 100 50 50 45
Data hold following
IORD
th(IORD) 0 5 5 5
IORD width time tw(IORD) 165 70 65 55
Address setup before
IORD
tsuA(IORD) 70 25 25 15
Address hold following
IORD
thA(IORD) 20 10 10 10
CE setup before IORD tsuCE(IORD) 5 5 5 5
CE hold following
IORD
thCE(IORD) 20 10 10 10
REG setup before
IORD
tsuREG(IORD) 5 5 5 5
REG hold following
IORD
thREG(IORD) 0 0 0 0
INPACK delay falling
from IORD
tdfINPACK(IOR
D)
0 45 0 na1 0 na1 0 na1
INPACK delay rising
from IORD
tdrINPACK(IOR
D)
45 na1 na
1 na1
IOIS16 delay falling
from address3
tdfIOIS16(ADR) 35 na1 na
1 na1
IOIS16 delay rising
from address3
tdrIOIS16(ADR) 35 na1 na
1 na1
WAIT delay falling
from IORD3
tdWT(IORD) 35 35 35 na2
Data delay from WAIT
rising3
td(WT) 0 0 0 na2
WAIT width time3 td(WT) 350 350 350 na2
Notes:
1. -IOIS16 and -INPACK are not supported in this mode.
2. -WAIT is not supported in this mode.
3. Maximum load on -WAIT, -INPACK and -IOIS16 is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total
load. All times are in nanoseconds. Minimum time from -WAIT high to -IORD high is 0 nsec, but minimum -
IORD width shall still be met. Dout signifies data provided by the CompactFlash Storage Card or CF+ Card to
the system. Wait Width time meets PCMCIA PC Card specification of 12μs but is intentionally less in this
specification.
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3.6.7 I/O Mode Write Tim ing
Table 3-12: I/O Mode Write Timing
Cycle Time Mode 250ns 120ns 100ns 80ns
Parameter Symbol Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
Data setup after
IOWR
tsu(IOWR) 60 20 20 15
Data hold following
IOWR
th(IOWR) 30 10 5 5
IOWR width time tw(IOWR) 165 70 65 55
Address setup
before IOWR
tsuA(IOWR) 70 25 25 15
Address hold
following IOWR
thA(IOWR) 20 20 10 10
CE setup before
IOWR
tsuCE(IOWR) 5 5 5 5
CE hold following
IOWR
thCE(IOWR) 20 20 10 10
REG setup before
IOWR
tsuREG(IOWR) 5 5 5 5
REG hold following
IOWR
thREG(IOWR) 0 0 0 0
IOIS16 delay falling
from address3
tdfIOIS16(ADR) 35 na1 na
1 na1
IOIS16 delay rising
from address3
tdrIOIS16(ADR) 35 na1 na
1 na1
WAIT delay falling
from IOWR3
tdWT(IOWR) 35 35 35 na2
IOWR high from
wait high3
tdrIOWR(WT) 0 0 0 na2
WAIT width time3 td(WT) 350 350 350 na2
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3.6.8 True IDE Mode PIO Read/Write Timing
Table 3-13: True IDE Mode PIO Read/Write Timing (Modes 0-6)
Parameter Mode
0 Mode
1 Mode
2 Mode
3 Mode
4 Mode
5 Mode
6 Notes
t0 Cycle Time (min) 600 383 240 180 120 100 80 1
t1 Address valid to -IORD/-
IOWR (min)
70 50 30 30 25 15 10
t2 -IORD/-IOWR (min) 165 125 100 80 70 65 55 1
t2 -IORD/-IOWR (min)
Register (8 bit)
29 290 290 80 70 65 55 1
t2i -IORD/-IOWR
recovery time (min)
- - - 70 25 25 20 1
t3 -IOWR data setup
(min)
60 45 30 30 20 20 15
t4 -IOWR data hold
(min)
30 20 15 10 10 5 5
t5 -IORD data setup
(min)
50 35 20 20 20 15 10
t6 -IORD data hold
(min)
5 5 5 5 5 5 5
T6
Z
-IORD data tristate
(max)
30 30 30 30 30 20 20 2
t7
Address valid to -
IOCS16 assertion
(max)
90 50 40 n/a n/a n/a n/a 4
t8
Address valid to -
IOCS16 released
(max)
60 45 30 n/a n/a n/a n/a 4
t9 -IORD/-IOWR to
address valid hold
20 15 10 10 10 10 10
tR
D
Read Data Valid to
IORDY active (min),
if IORDY initially low
after tA
0 0 0 0 0 0 0
tA IORDY Setup time 35 35 35 35 35 n/a5 n/a5 3
tB IORDY Pulse Width
(max) 1250 1250 1250 1250 1250 n/a5 n/a5
tC IORDY assertion to
release (max)
5 5 5 5 5 n/a5 n/a5
Notes: All timings are in ns.
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1. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command
recovery time or command inactive time. The actual cycle time equals the sum of the actual command active
time and the actual command inactive time. The three timing requirements of t0, t2, and t2i shall be met. The
minimum total cycle time requirement is greater than the sum of t2 and t2i. This means a host implementation
can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the
device’s identify device data. A CompactFlash Storage Card implementation shall support any legal host
implementation.
2. This parameter specifies the time from the negation edge of -IORD to the time that the data bus is no longer
driven by the CompactFlash Storage Card (tri-state).
3. The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is inactive
then the host shall wait until IORDY is active before the PIO cycle can be completed. If the CompactFlash
Storage Card is not driving IORDY negated at tA after the activation of -IORD or -IOWR, then t5 shall be met
and tRD is not applicable. If the CompactFlash Storage Card is driving IORDY negated at the time tA after the
activation of -IORD or -IOWR, then tRD shall be met and t5 is not applicable.
4. t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid.
5. IORDY is not supported in this mode.
3.6.9 True IDE Multi word DMA Read/Write Timing
Table 3-14: True IDE Multiword DMA Read/Write Timing (Modes 0-4)
Parameter Mode
0
(ns)
Mode
1
(ns)
Mode
2
(ns)
Mode
3
(ns)
Mode
4
(ns)
Note
tO Cycle time (ns) 480 150 120 100 80 1
tD -IORD / -IOWR asserted width
(min)
215 80 70 65 55 1
tE -IORD data access (max) 150 60 50 50 45
tF -IORD data hold (min) 5 5 5 5 5
tG -IORD / IOWR data setup (min) 100 30 20 15 10
tH -IOWR data hold (min) 20 15 10 5 5
tI DMACK to -IORD / -IOWR
setup (min)
0 0 0 0 0
tJ -IORD / -IOWR to –DMACK
hold (min)
20 5 5 5 5
tKR -IORD negated width (ns) 50 50 25 25 20
tKW -IOWR negated width (ns) 215 50 25 25 20 1
tLR -IORD to DMARQ delay (max) 120 40 35 35 35 1
tLW -IOWR to DMARQ delay (max) 40 40 35 35 35
tM CE(1:0) valid to IORD / IOWR 50 30 25 10 5
tN CE(1:0) hold 15 10 10 10 10
tZ -DMACK 20 25 25 25 25
Notes:
1. t0 is the minimum total cycle time and tD is the minimum command active time, while tKR and tKW are the
minimum command recovery time or command inactive time for input and output cycles respectively. The actual
cycle time equals the sum of the actual command active time and the actual command inactive time. The three
timing requirements of t0, tD, tKR, and tKW shall be met. The minimum total cycle time requirement is greater
than the sum of tD and tKR or tKW.for input and output cycles respectively. This means a host implementation
can lengthen either or both of tD and either of tKR, and tKW as needed to ensure that t0 is equal to or greater
than the value reported in the device’s identify device data. A CompactFlash Storage Card implementation shall
support any legal host implementation.
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3.6.10 Ultra DMA AC Characteristics
Table 3-15: Ultra DMA AC Characteristics
Symbol UDMA0
(ns) UDMA1
(ns) UDMA2
(ns) UDMA3
(ns) UDMA4
(ns) Measure
location
(see
Note2)
t2CYCTYP (min) 240 160 120 90 60 Sender
tCYC (min) 112 73 54 39 25 Note3
t2CYC (min) 230 153 115 86 57 Sender
tDS (min) 15.0 10.0 7.0 7.0 5.0 Recipient
tDH (min) 5.0 5.0 5.0 5.0 5.0 Recipient
tDVS (min) 70.0 48.0 31.0 20.0 6.7 Sender
tDVH (min) 6.2 6.2 6.2 6.2 6.2 Sender
tCS (min) 15.0 10.0 7.0 7.0 5.0 Device
tCH (min) 5.0 5.0 5.0 5.0 5.0 Device
tCVS (min) 70.0 48.0 31.0 20.0 6.7 Host
tCVH (min) 6.2 6.2 6.2 6.2 6.2 Host
tZFS (min) 0 0 0 0 0 Device
tDZFS (min) 70.0 48.0 31.0 20.0 6.7 Sender
tFS (max) 230 200 170 130 120 Device
tLI (min) 0 0 0 0 0 Note4
tLI (max) 150 150 150 100 100 Note4
tMLI (min) 20 20 20 20 20 Host
tUI (min) 0 0 0 0 0 Host
tAZ (max) 10 10 10 10 10 Note5
tZAH (min) 20 20 20 20 20 Host
tZAD (min) 0 0 0 0 0 Device
tENV (min) 20 20 20 20 20 Host
tENV (max) 70 70 70 55 55 Host
tRFS (max) 75 70 60 60 60 Sender
tRP (min) 160 125 100 100 100 Recip’nt
tIORDYZ (max) 20 20 20 20 20 Device
tZIORDY (min) 0 0 0 0 0 Device
tACK (min) 20 20 20 20 20 Host
tSS (min) 50 50 50 50 50 Sender
Notes:
1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
2) All signal transitions for a timing parameter shall be measured at the connector specified in the measurement
location column. For example, in the case of tRFS, both STROBE and -DMARDY transitions are measured at
the sender connector.
3) The parameter tCYC shall be measured at the recipient’s connector farthest from the sender.
4) The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an
incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing
response shall be measured at the same connector.
5) The parameter tAZ shall be measured at the connector of the sender or recipient that is driving the bus but
must release the bus to allow for a bus turnaround.
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3.6.11 Ultra DMA Data Burst Timing Descri ptions
Table 3-16: Ultra DMA Data Burst Timing Descriptions
Name Comment Notes
t2CYCTYP Typical sustained average two cycle time
tCYC Cycle time allowing for asymmetry and clock variations (from
STROBE edge to STROBE edge)
t2CYC
Two cycle time allowing for clock variations (from rising edge to
next rising edge or from falling edge to next falling edge of
STROBE)
tDS Data setup time at recipient (from data valid until STROBE
edge) 2, 5
tDH Data hold time at recipient (from STROBE edge until data may
become invalid) 2, 5
tDVS Data valid setup time at sender (from data valid until STROBE
edge) 3
tDVH Data valid hold time at sender (from STROB3E edge until data
may become invalid)3 3
tCS CRC word setup time at device 2
tCH CRC word hold time device 2
tCVS CRC word valid setup time at host (from CRC valid until -
DMACK negation) 3
tCVH CRC word valid hold time at sender (from -DMACK negation
until CRC may become invalid) 3
tZFS Time from STROBE output released-to-driving until the first
transition of critical timing.
tDZFS Time from data output released-to-driving until the first
transition of critical timing.
tFS First STROBE time (for device to first negate DSTROBE from
STOP during a data in burst)
tLI Limited interlock time 1
tMLI Interlock time with minimum 1
tUI Unlimited interlock time 1
tAZ Maximum time allowed for output drivers to release (from
asserted or negated)
tZAH Minimum delay time required for output
tZAD Drivers to assert or negate (from released)
tENV
Envelope time (from -DMACK to STOP and -HDMARDY during
data in burst initiation and from DMACK to STOP during data
out burst initiation)
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tRFS Ready-to-final-STROBE time (no STROBE edges shall be sent
this long after negation of -DMARDY)
tRP Ready-to-pause time (that recipient shall wait to pause after
negating -DMARDY)
tIORDYZ Maximum time before releasing IORDY 6
tZIORDY Minimum time before driving IORDY 4, 6
tACK Setup and hold times for -DMACK (before assertion or
negation)
tSS Time from STROBE edge to negation of DMARQ or assertion
of STOP (when sender terminates a burst)
Notes:
1. The parameters tUI, tMLI (in Figure 36: Ultra DMA Data-In Burst Device Termination Timing and Figure 37: Ultra
DMA Data-In Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-sender interlocks,
i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding.
tUI is an unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum.
tLI is a limited time-out that has a defined maximum.
2. 80-conductor cabling (see 4.3.8.4) shall be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times in
modes greater than 2.
3. Timing for tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF at the connector
where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these
timing measurements are not valid in a normally functioning system.
4. For all timing modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull-up on
IORDY- giving it a known state when released.
5. The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in a configuration
with a single device located at the end of the cable. This could result in the minimum values for tDS and tDH for mode
5 at the middle connector being 3.0 and 3.9 ns respectively.
6. This parameter applies to True IDE mode operation only.
3.6.12 CF-ATA Command Support
Table 3-17: CF-ATA Command Support
No. Command Code FR SC SN CY DR HD LBA
1 Check Power Mode E5h, 98h -- -- -- -- Y -- --
2 Erase Sector C0h -- Y Y Y Y Y Y
3 Execute Drive Diagnostic 90h -- -- -- -- -- -- --
4 Flush Cache E7h -- -- -- -- Y -- --
5 Format Track 50h -- Y -- Y Y Y Y
6 Identify Drive ECh -- -- -- -- Y -- --
7 Idle E3h, 97h -- Y -- -- Y -- --
8 Idle Immediate E1h, 95h -- -- -- -- Y -- --
9 Initialize Drive Parameters 91h -- Y -- -- Y Y --
10 Media Lock DEh -- -- -- -- Y -- --
11 Media Unlock DFh -- -- -- -- Y -- --
12 NOP 00h -- -- -- -- Y -- --
13 Read Buffer E4h -- -- -- -- Y -- --
14 Read DMA C8h, C9h -- Y Y Y Y Y Y
15 Read Multiple C4h -- Y Y Y Y Y Y
16 Read Long 22h, 23h -- -- Y Y Y Y Y
17 Read Native Max Address F8h -- -- -- -- Y -- --
18 Read Sector(s) 20h, 21h -- Y Y Y Y Y Y
19 Read Verify Sector(s) 40h, 41h -- Y Y Y Y Y Y
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No. Command Code FR SC SN CY DR HD LBA
20 Recalibrate 1Xh -- -- -- -- Y -- --
21 Request Sense 03h -- -- -- -- Y -- --
22 Security Disable Password F6h -- -- -- -- Y -- --
23 Security Erase Prepare F3h -- -- -- -- Y -- --
24 Security Erase Unit F4h -- -- -- -- Y -- --
25 Security Freeze Lock F5h -- -- -- -- Y -- --
26 Security Set Password F1h -- -- -- -- Y -- --
27 Security Unlock F2h -- -- -- -- Y -- --
28 Seek 7Xh Y -- -- -- Y -- --
29 Set Feature EFh -- Y Y Y Y Y Y
30 Set Max Address F9h -- Y Y Y Y Y Y
31 Set Multiple Mode C6h -- Y -- -- Y -- --
32 Set Sleep Mode E6h, 99h -- -- -- -- Y -- --
33 SMART B0h Y Y -- Y Y -- --
34 Standby E2h, 96h -- Y -- -- Y -- --
35 Standby Immediate E0h, 94h -- -- -- -- Y -- --
36 Translate Sector 87h -- Y Y Y Y Y Y
37 Write Buffer E8h -- -- -- -- Y -- --
38 Write DMA CAh, CBh -- Y Y Y Y Y Y
39 Write Long 32h, 33h -- -- Y Y Y Y Y
40 Write Multiple C5h -- Y Y Y Y Y Y
41 Write Multiple w/o Erase CDh -- Y Y Y Y Y Y
42 Write Sector(s) 30h, 31h -- Y Y Y Y Y Y
43 Write Sector(s) w/o Erase 38h -- Y Y Y Y Y Y
44 Write Verify 3Ch -- Y Y Y Y Y Y
Notes: Abbreviations in this table:
FR: Features Register
SC: Sector Count Register (00h – FFh; 00h means 256 sectors
SN: Sector Number Register
CY: Cylinder Low/ High Register
DR: Drive bit of Drive/Head Register
HD: Head Number (0-15) of Drive/ Head Register
LBA: Logic Block Address Mode Support
--: Not used for this command
Y: Used for this command
3.7 Capacity Information
3.7.1 True IDE Mode
Table 3-18: True IDE Mode
Card Size Cylinders
(Note 1) Head Sector Total Sectors
(Note 2, 3)
Usable
Capacity
(bytes)
128MB 486 16 32 248,832 127,401,984
256MB 972 16 32 497,664 254,803,968
512MB 1029 16 63 1,037,232 531,062,784
1GB 2027 16 63 2,043,216 1,046,126,592
2GB 3961 16 63 3,992,688 2,044,256,256
4GB 7946 16 63 8,009,568 4,100,898,816
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8GB 15857 16 63 15,983,856 8,183,734,272
16GB 16383 * 16 63 32,105,808 16,438,173,700
32GB 16383 * 16 63 64,028,160 32,782,417,920
Notes:
1. 16,383 is the max Cylinder size for True IDE mode. Use total sectors to calculate size.
2. Total sectors remaining after deducting firmware and spare block overhead.
3. Available data capacity is dependent on format and partition type.
3.7.2 PCMCIA Mode (I/O and Memory Modes)
Table 3-19: PCMCIA Mode (I/O and Memory Modes)
Card Size Cylinders
(Note 1) Head Sector Total Sectors
(Note 2, 3) Usable Capacity
(bytes)
128MB 486 16 32 248,832 127,401,984
256MB 972 16 32 497,664 254,803,968
512MB 1029 16 63 1,037,232 531,062,784
1GB 2027 16 63 2,043,216 1,046,126,592
2GB 3961 16 63 3,992,688 2,044,256,256
4GB 7946 16 63 8,009,568 4,100,898,816
8GB 15857 16 63 15,983,856 8,183,734,272
16GB 31851 16 63 32,105,808 16,438,173,700
32GB 63520 16 63 64,028,160 32,782,417,920
Notes:
1. Total sectors remaining after deducting firmware and spare block overhead.
2. Available data capacity is dependent on format and partition type.
3.8 Identify Drive Parameter
An example of the parameter information received from the CF Card when
invoking the Identify Drive command (ECh) is listed in table below:
Table 3-20: Identify Drive Parameter
Word
Address Default
Value Bytes Data Field Type Information
0 045AH 2 General configuration bit-significant information
1 XXXXH 2 Default number of cylinders
2 0000H 2 Reserved
3 00XXH 2 Default number of heads
4 0000H 2 Number of unformatted bytes per track
5 0200H 2 Number of unformatted bytes per sector
6 XXXXH 2 Default number of sectors per track
7 - 8 XXXXH 4 Number of sectors per CF Card
9 0000H 2 Reserved
10 - 19 XXXXH 20 Serial Number in ASCII (20 characters)
20 0002H 2 Buffer type (dual-ported multi-sector)
21 0001H 2 Buffer size in 512 byte increments
22 0004H 2 # of ECC bytes passed on Read/Write Long commands
23 - 26 XXXXH 8 Firmware revision (8 ASCII characters)
27 - 46 XXXXH 40 Model Number in ASCII (40 characters)
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Word
Address Default
Value Bytes Data Field Type Information
47 8001H 2 Maximum 1 sector on Read/Write Multiple command
48 0000H 2 Double Word not supported
49 0F00H 2 Capabilities: DMA, LBA, IORDY supported
50 4001H 2 Capabilities: device specific standby timer minimum
51 0200H 2 PIO data transfer cycle timing mode 2
52 0000H 2 DMA data transfer cycle timing mode not supported
53 0007H 2 Data Fields 54 – 58, 64 – 70, and 88 are valid
54 XXXXH 2 Number of Current Logical Cylinders
55 XXXXH 2 Number of Current Logical Heads
56 XXXXH 2 Number of Current Logical Sectors Per Track
57 - 58 XXXXH 4 Current Capacity in Sectors
59 010XH 2 Multiple sector setting is valid
60 - 61 XXXXH 4 Total number of sectors addressable in LBA Mode
62 0000H 2 Single word DMA transfer not implemented
63 0X0XH 2 Multiword DMA transfer mode
64 0003H 2 Advanced PIO modes supported (modes 3 and 4)
65 0078H 2 Minimum multiword DMA cycle time, 0 if no MDMA
66 0078H 2 Recommended multiword DMA cycle time, 0 if no MDMA
67 0078H 2 Minimum PIO cycle time without flow control
68 0078H 2 Minimum PIO cycle time with flow control
69 - 79 0000H 22 Reserved
80 0020H 2 Major version number, ATA-5 support
81 0000H 2 Minor version number, not reported
82 740BH 2
Command set: NOP, READ BUFFER, WRITE BUFFER, host
protected area, power management feature set, Security
Mode feature set, SMART feature set
83 5004H 2 Command set: FLUSH CACHE, CFA feature set
84 4000H 2 Command set/feature supported extension
85 740XH 2
Command set enabled: NOP, READ BUFFER, WRITE
BUFFER, host protected area, power management feature
set, Security Mode feature set enabled/disabled, SMART
feature set enabled/disabled
86 1004H 2 Command set enabled: FLUSH CACHE, CFA feature set
87 4000H 2 Command set/feature default
88 XXXXH 2 UDMA mode
89 0000H 2 Time for Security Erase Unit not specified
90 0000H 2 Time for Enhanced Security Erase Unit not specified
91 0000H 2 Reserved
92 XXXXH 2 Master Password Revision Code
93 XXXXH 2 Hardware Reset Result
94 – 127 0000H 72 Reserved
128 0XXXH 2 Security Status
129 XX00H 2
Write Protect Status. Bit 15 = permanent write protect, no
more spare blocks available
130 –
133 XXXXH 8
Firmware date string
134 848AH 2 General Configuration word for PCMCIA mode
135 045AH 2 General Configuration word for True-IDE mode
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Word
Address Default
Value Bytes Data Field Type Information
136 –
141 XXXXH 12
Firmware file name
142 –
147 XXXXH 12
Preformat file name
148 –
153 XXXXH 12
Anchor program file name
154 –
159 0000H 12
Reserved
160 A064H 2 CFA Power Mode: no power level 1, max 100mA
161 0000H 2 Reserved
162 0000H 2 Key Management Schemes: CPRM not supported
163 XXXXH 2 CFA advanced modes: supported and enabled bits
164 001BH 2 CFA advanced modes: 80ns I/O and Memory supported
165 –
254 0000H 180
Reserved
255 XXA5H 2 Integrity Word
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Table 3-21: Identify Drive Parameter Table in PCMCIA mode showing word
differences
Word
Address Default
Value Bytes Data Field Type Information
0 848AH 2 General configuration bit-significant information
49 0E00H 2 Capabilities: LBA, IORDY supported
63 0000H 2 Multi Word DMA transfer mode not supported
65 0000H 2 Minimum Multi Word DMA cycle time
66 0000H 2 Recommended Multi Word DMA cycle time
93 0000H 2 Hardware Reset Result not supported
163 -
164
0000H 4 CFA advanced modes: not supported
Table 3-22: Identify Drive Parameter Table in PCMCIA mode showing word
differences
Word
Address Default
Value Bytes Data Field Type Information
83 5000H 2 Command set: FLUSH CACHE
86 1000H 2 Command set enabled: FLUSH CACHE
160-164 0000H 10 Reserved
3.9 SMART Support
The Viking Firmware supports the following SMART commands, determined by
the Feature Register value.
Table 3-23: Supported SMART Commands determined by Feature Register
value
Value Command
D0h SMART Read Data
D1h SMART Read Attribute Thresholds
D2h SMART Enable/Disable Attribute Autosave
D8h SMART Enable Operations
D9h SMART Disable Operations
DAh SMART Return Status
E0h SMART Read Remap Data
E1h SMART Read Wear Level Data
SMART commands with Feature Register values not mentioned in the above
table are not
supported, and will be aborted.
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3.9.1 SMART Enable Operations
COMMAND CODE | B0h with a Feature Register value of D8h
PROTOCOL | Non-data.
INPUTS |
Register 7 6 5 4 3 2 1 0
Features D8h
Sector Count
Sector Number
Cylinder Low 4Fh
Cylinder High C2h
Device/Head 1 1 1 D
Command B0h
NORMAL OUTPUTS | None required.
ERROR OUTPUTS | Aborted if the signature in the Cylinder registers is invalid.
DESCRIPTION | This command enables access to the SMART capabilities of the
firmware. The state of SMART (enabled or disabled) is preserved across power
cycles.
3.9.2 SMART Disabl e Operations
COMMAND CODE | B0h with a Feature Register value of D9h
PROTOCOL | Non-data.
INPUTS |
Register 7 6 5 4 3 2 1 0
Features D9h
Sector Count
Sector Number
Cylinder Low 4Fh
Cylinder High C2h
Device/Head 1 1 1 D
Command B0h
NORMAL OUTPUTS | None required.
ERROR OUTPUTS | Aborted if either the signature in the Cylinder registers is
invalid, or if SMART is not enabled.
DESCRIPTION | This command disables access to the SMART capabilities of
the firmware. The state of SMART (enabled or disabled) is preserved across
power cycles.
3.9.3 SMART Enable/Disable Attribute Autosave
COMMAND CODE | B0h with a Feature Register value of D2h
PROTOCOL | Non-data.
INPUTS |
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Register 7 6 5 4 3 2 1 0
Features D2h
Sector Count 00h or F1h
Sector Number
Cylinder Low 4Fh
Cylinder High C2h
Device/Head 1 1 1 D
Command B0h
NORMAL OUTPUTS | None required.
ERROR OUTPUTS | Aborted if either the signature in the Cylinder registers is
invalid, or if SMART is not enabled.
DESCRIPTION | This command is effectively a no-operation as the data for the
SMART functionality is always available and kept current in the firmware.
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3.9.4 SMART Read Data
COMMAND CODE | B0h with a Feature Register value of D0h
PROTOCOL | PIO data in.
INPUTS |
Register 7 6 5 4 3 2 1 0
Features D0h
Sector Count
Sector Number
Cylinder Low 4Fh
Cylinder High C2h
Device/Head 1 1 1 D
Command B0h
NORMAL OUTPUTS | None required.
ERROR OUTPUTS | Aborted if either the signature in the Cylinder registers is
invalid, or if SMART is not enabled.
DESCRIPTION | This command returns one sector of SMART data. The data
structure returned is:
Offset Value Description
0..1 0004h SMART structure version
2..361 Attribute entries 1 to 30 (12 bytes each)
362 00h Off-line data collection status (no off-line data collection)
363 00h Self-test execution status byte (self-test completed)
364..365 0000h Total time to complete off-line data collection
366 00h
367 00h Off-line data collection capability (no off-line data collection)
368..369 0003h SMART capabilities
370 00h Error logging capability (no error logging)
371 00h
372 00h Short self-test routine recommended polling time
373 00h Extended self-test routine recommended polling time
374..385 00h Reserved
386..387 0002h SMART Version
388..391 Firmware “Commit” counter
392..395 Firmware Wear Level Threshold
396 Global Wear Leveling active
397 Global Bad Block Management active
398..510 00h
511 Data structure checksum
There are six attributes that are defined for the firmware. These return their data
in the attribute section of the SMART data, using a 12 byte data field.
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The field at offset 386 gives a version number for the contents of the SMART
data structure. For the controller, only version 2 is defined.
The byte at offset 396 is 0 if the wear leveling has not yet started its global
operation and 1 if the global wear leveling has started. This happens when the
most used chip has reached the erase count threshold defined in the Erase
Count Attribute.
The byte at offset 397 is 0 if the bad block management is still working chip local,
and 1 if the global bad block management has started. This happens when one
of the flash chips runs out of spare blocks, in this case spare blocks from
different flash chips are used.
3.9.4.1 Spare Block Count Attribute
This attribute gives information about the amount of available spare blocks.
Offset Value Description
0 196 Attribute ID – Reallocation Count
1..2 0003h Flags – Pre-fail type, attribute value is updated during normal operation
3 Attribute value. The value returned here is the percentage of remaining
spare blocks summed over all flash chips, i.e. (100 x current spare
blocks / initial spare blocks)
4..5 Initial number of spare blocks of the flash chip with the lowest current
number of spare blocks
6..7 Current number of spare blocks of the flash chip with the lowest current
number of spare blocks
8..9 Sum of the initial number of spare blocks for all flash chips
10..11 Sum of the current number of spare blocks for all flash chips
3.9.4.2 Erase Count Attribute
This attribute gives information about the amount of flash block erases that have
been performed.
Offset Value Description
0 229 Attribute ID – Erase Count Usage (vendor specific)
1..2 000Xh Flags – Pre-fail or Advisory type, attribute value is updated during
normal operation
3 Attribute value. The value returned here is an estimation of the
remaining card life, in percent, based on the number of flash block
erases compared to the target number of erase cycles per block.
4..11 Estimated total number of block erases
This attribute is used for the SMART Return Status command. If the attribute
value field is less than the erase count threshold, the SMART Return Status
command will indicate a threshold exceeded condition.
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3.9.4.3 Total ECC Errors Attribute
This attribute gives information about the total number of ECC errors that have
occurred on flash read commands. This attribute is not used for the SMART
Return Status command.
Offset Value Description
0 203 Attribute ID – Number of ECC errors
1..2 0002h Flags – Advisory type, attribute value is updated during normal
operation
3 64h Attribute value. This value is fixed at 100.
4..7 Total number of ECC errors (correctable and uncorrectable)
8..11
3.9.4.4 Correctable ECC Errors Attribute
This attribute gives information about the total number of correctable ECC errors
that have occurred on flash read commands. This attribute is not used for the
SMART Return Status command.
Offset Value Description
0 204 Attribute ID – Number of corrected ECC errors
1..2 0002h Flags – Advisory type, attribute value is updated during normal
operation
3 64h Attribute value. This value is fixed at 100.
4..7 Total number of ECC errors (correctable and uncorrectable)
8..11
3.9.4.5 Total Number of Reads Attribute
This attribute gives information about the total number of flash read commands.
This can be useful for the interpretation of the number of correctable or total ECC
errors. This attribute is not used for the SMART Return Status command.
Offset Value Description
0 232 Attribute ID – Number of Reads
1..2 0002h Flags – Advisory type, attribute value is updated during normal
operation
3 64h Attribute value. This value is fixed at 100.
4..11 Total number of flash read commands
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3.9.4.6 UDMA CRC Errors Attribute
This attribute gives information about the total number of UDMA CRC errors that
have occurred on flash read commands. This attribute is not used for the SMART
Return Status command.
Offset Value Description
0 199 Attribute ID – UDMA CRC error rate
1..2 0002h Flags – Advisory type, attribute value is updated during normal
operation
3 64h Attribute value. This value is fixed at 100.
4..7 Total number of UDMA CRC errors
8..11
3.9.5 SMART Read Attribute Thresholds
COMMAND CODE | B0h with a Feature Register value of D1h
PROTOCOL | PIO data in.
INPUTS |
Register 7 6 5 4 3 2 1 0
Features D1h
Sector Count
Sector Number
Cylinder Low 4Fh
Cylinder High C2h
Device/Head 1 1 1 D
Command B0h
NORMAL OUTPUTS | None required.
ERROR OUTPUTS | Aborted if either the signature in the Cylinder registers is
invalid, or if SMART is not enabled.
DESCRIPTION | This command returns one sector of SMART attribute
thresholds. The data structure returned is:
Offset Value Description
0..1 0004h SMART structure version
2..361 0002h Attribute threshold entries 1 to 30 (12 bytes each)
362..379 00h Reserved
380..510 00h
511 Data structure checksum
3.9.5.1 Spare Block Count Attribute Threshold
Offset Value Description
0 196 Attribute ID – Reallocation Count
1 Factory Programmed Spare Block Count Threshold
2..11 00h Reserved
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3.9.5.2 Erase Count Attribute Threshold
Offset Value Description
0 229 Attribute ID – Erase Count Usage
1 Factory Programmed Erase Count Threshold
2..11 00h Reserved
3.9.5.3 Total ECC Errors Attribute Threshold
Offset Value Description
0 203 Attribute ID – Number of ECC errors
1 00h No threshold for the Total ECC Errors Attribute
2..11 00h Reserved
3.9.5.4 Correctable ECC Errors Attribute
Offset Value Description
0 204 Attribute ID – Number of corrected ECC errors
1 00h No threshold for the Correctable ECC Errors Attribute
2..11 00h Reserved
3.9.5.5 Total Number of Reads Attribute
Offset Value Description
0 232 Attribute ID – Number of Reads
1 00h No threshold for the Total Number of Reads Attribute
2..11 00h Reserved
3.9.5.6 UDMA CRC Errors Attribute
Offset Value Description
0 199 Attribute ID – UDMA CRC error rate
1 00h No threshold for the UDMA CRC Errors Attribute
2..11 00h Reserved
3.9.6 SMART Return Stat us
COMMAND CODE | B0h with a Feature Register value of DAh
PROTOCOL | Non-data.
INPUTS |
Register 7 6 5 4 3 2 1 0
Features DAh
Sector Count
Sector Number
Cylinder Low 4Fh
Cylinder High C2h
Device/Head 1 1 1 D
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Command B0h
NORMAL OUTPUTS | Returns a status indication as described below.
ERROR OUTPUTS | Aborted if either the signature in the Cylinder registers is
invalid, or if SMART is not enabled.
DESCRIPTION | This command checks the device reliability status. If a threshold
exceeded condition exists for either the Spare Block Count attribute or the Erase
Count attribute, the device will set the Cylinder Low register to F4h and the
Cylinder High register to 2Ch. If no threshold exceeded condition exists, the
device will set the Cylinder Low register to 4Fh and the Cylinder High register to
C2h.
3.9.7 SMART Read Remap Data
COMMAND CODE | B0h with a Feature Register value of E0h
PROTOCOL | PIO data in.
INPUTS |
Register 7 6 5 4 3 2 1 0
Features E0h
Sector Count 01h
Sector Number
Cylinder Low 4Fh
Cylinder High C2h
Device/Head 1 1 1 D
Command B0h
NORMAL OUTPUTS | None required.
ERROR OUTPUTS | Aborted if either the signature in the Cylinder registers is
invalid, if the Sector Count is not 1, or if SMART is not enabled.
DESCRIPTION | This command returns one sector of spare block information.
The information is the initial number of blocks per flash chip available for bad
block remap, and the current number of blocks per flash chip available for bad
block remap. The layout of the returned sector is:
Offset Description
0..31 Initial number of replacement blocks for chips 0..15, 2 bytes per entry
32..63 Current number of replacement blocks for chips 0..15, 2 bytes per entry
64..511
3.9.8 SMART Read Wear Lev el Data
COMMAND CODE | B0h with a Feature Register value of E1h
PROTOCOL | PIO data in.
INPUTS |
Register 7 6 5 4 3 2 1 0
Features E1h
Sector Count 04h
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Sector Number
Cylinder Low 4Fh
Cylinder High C2h
Device/Head 1 1 1 D
Command B0h
NORMAL OUTPUTS | None required.
ERROR OUTPUTS | Aborted if either the signature in the Cylinder registers is
invalid, if the Sector Count is not 4, or if SMART is not enabled.
DESCRIPTION | This command will return four sectors of information regarding
the status of the wear leveling. The information returned is the distribution of the
blocks into the 1024 possible wear level classes. For each of the wear level
classes, the number of blocks that have this class is returned in the data sectors.
The layout of the returned sectors is, with n the sector number from 0 to 3:
Offset Description
0..1 Number of flash blocks that have wear level class 256*n+0
2..3 Number of flash blocks that have wear level class 256*n+1
… …
508..509 Number of flash blocks that have wear level class 256*n+254
510..511 Number of flash blocks that have wear level class 256*n+255
i.e. the first sector returns the information for wear level classes 0 to 255, the
second sector returns the information for wear level classes 256 to 511, and so
on.
A block moves from one wear level class into the next when it reaches the
number of erases that is specified as the factory programmed “Wear Level
Threshold”. A common threshold number is 4095, this means that blocks in wear
level class 0 have seen 0 to 4095 erases, blocks in wear level class 1 have seen
4096 to 8191 erases, and so on. Using this information, statements about the
wear of the card, and of the estimated remaining life can be made. The useful
range of wear level classes is 0 to 1022, class 1023 has blocks that are not
subject to wear leveling, like the Anchor block.
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4 Certifications and Compliance
Table 4-1: Device Certifications
Certification/Compliance Description
CE Compliant Indicates conformity with the essential health and safety requirements
set out in European Directives Low Voltage Directive and EMC
directive.
EN 55022:2006+A1:2007
EN 55024:1998+A1:2001+A2:2003
EN 61000-4-2:2009
EN 61000-4-3:2008
EN 61000-4-8:2001
RoHS Restriction of Hazardous Substance Directive
China RoHS Restriction of Hazardous Substance Directive, China
FCC ANSI C63.4-2002, Part 15, Subpart B – Class B
5 References
CF+ and CompactFlash Specification Revision 4.1
6 Revision History
Date Revision Description
2/11/10 A Initial Release
8/10/10 A1 Added 32GB capacity information
9/1/10 A2 Updated formatting, updated introduction section and footer
11/23/10 A3 Fixed miscellaneous omissions.
Updated Read/Write performance table for 40Mhz internal clock
1/11/12 A4 Add new logo and company name