LTC3882-1 Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management Description Features n n n n n n n n n n n PMBus/I2C Compliant Serial Interface - Monitor Voltage, Current, Temperature and Faults - Program Voltage, Soft-Start/Stop, Sequencing, Margining, AVP and UV/OV/OC Limits 3V VINSNS 38V, 0.5V VOUT 5.25V 0.5% Output Voltage Error Programmable PWM Frequency or External Clock Synchronization from 250kHz to 1.25MHz Accurate PolyPhase(R) Current Sharing Internal EEPROM with Fault Logging IC Supply Range: 3V to 13.2V Resistor or Inductor DCR Current Sensing Power Good Output Voltage Monitor Optional Resistor Programming for Key Parameters 40-Pin (6mm x 6mm) QFN Package Applications n n n High Current Distributed Power Systems Servers, Network and Storage Equipment Intelligent Energy Efficient Power Regulation The LTC(R)3882-1 is a dual, PolyPhase DC/DC synchronous step-down switching regulator controller with PMBus compliant serial interface. It uses a constant frequency, leading-edge modulation, voltage mode architecture for excellent transient response and output regulation. Each PWM channel can produce output voltages from 0.5V to 5.25V using a wide range of 3.3V compatible power stages, including power blocks, DrMOS or discrete FET drivers. Up to four LTC3882-1 devices can operate in parallel for 2-, 3-, 4-, 6- or 8-phase operation. System configuration and monitoring is supported by the LTpowerPlayTM software tool. The LTC3882-1 serial interface can read back input voltage, output voltage and current, temperature and fault status. Most operating parameters can be set via the digital interface or stored in internal EEPROM for use at power up. Switching frequency and phase, output voltage and device address can also be set using external configuration resistors. L, LT, LTC, LTM, Linear Technology,the Linear logo and PolyPhase are registered trademarks and LTpowerPlay is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245, 5859606, 6144194, 6937178, 7420359 and 7000125. Typical Application PWM ENABLE TG/BG HW WRITE OUTPUT CONTROL PROTECT LTC3882 + VCC VINSNS V SENSE0 FB0 SDA LTC3882-1 SCL ALERT * VOUT0 & VOUT1 VOUT0 Only * VIN VOUT 1V 70A SW Load Step Transient Current Sharing (Using FDMF5820DC DrMOS) GND PWM0 TSNS0 PGOOD1 FAULT1 SYNC SHARE_CLK IAVG0 IAVG_GND PWM DIFFERENTIAL VOUT SENSE COMP1 RUN0 RUN1 IAVG1 FDMF5820DC COMP0 PGOOD0 FAULT0 TO/FROM EXTERNAL DEVICES * LTC3882-1 VIN 7V TO 13.2V TO/FROM MCU * DEDICATED PGOOD OUTPUT ISENSE0+ ISENSE0- VSENSE1+ ISENSE1- ISENSE1+ PWM1 IOUT 10A/DIV FDMF5820DC PWM TSNS1 VSENSE0- - GND VSENSE1 VIN SW IL0, IL1 10A/DIV GND 50s/DIV INDUCTORS: COOPER FP1007R1-R22 SOME DETAILS OMITTED FOR CLARITY 38821 TA01b 38821 TA01a 38821f For more information www.linear.com/LTC3882-1 1 LTC3882-1 Table of Contents Features...................................................... 1 Applications................................................. 1 Typical Application ......................................... 1 Description.................................................. 1 Absolute Maximum Ratings............................... 4 Order Information........................................... 4 Pin Configuration........................................... 4 Electrical Characteristics.................................. 5 Typical Performance Characteristics.................... 9 Pin Functions............................................... 13 Block Diagram.............................................. 15 Test Circuit.................................................. 16 Timing Diagram............................................ 16 Operation................................................... 16 Overview............................................................. 16 Main Control Loop............................................... 17 Power-Up and Initialization.................................. 19 Soft-Start............................................................20 Time-Based Output Sequencing..........................20 Output Ramping Control......................................20 Voltage-Based Output Sequencing......................20 Minimum Output Disable Times.......................... 21 Output Short Cycle.............................................. 21 Light Load Current Operation.............................. 21 Switching Frequency and Phase.......................... 21 PolyPhase Load Sharing......................................22 Active Voltage Positioning...................................22 Input Supply Monitoring......................................22 Output Voltage Sensing and Monitoring..............22 Output Current Sensing and Monitoring..............22 External and Internal Temperature Sense............23 Resistor Configuration Pins.................................23 Internal EEPROM with CRC................................. 24 Fault Detection..................................................... 24 Input Supply Faults.............................................. 24 Hardwired PWM Response to VOUT Faults.......... 24 Power Good Indication (Master)..........................25 Power Good Indication (Slave)............................25 Hardwired PWM Response to IOUT Faults................ 25 Hardwired PWM Response to Temperature Faults... 25 Hardwired PWM Response to Timing Faults.......26 External Faults.....................................................26 Fault Handling......................................................26 Status Registers and ALERT Masking..................26 FAULT Pin I/O....................................................... 28 Fault Logging....................................................... 28 Factory Default Operation.................................... 31 Serial Interface.................................................... 32 Serial Bus Addressing......................................... 32 Serial Bus Timeout..............................................36 2 Serial Communication Errors..............................36 PMBus Command Summary............................. 37 PMBus Commands.............................................. 37 Data Formats....................................................... 37 Applications Information................................. 42 Efficiency Considerations.................................... 42 PWM Frequency and Inductor Selection.............. 42 Power MOSFET Selection....................................43 MOSFET Driver Selection....................................44 Using PWM Protocols.........................................44 CIN Selection........................................................44 COUT Selection.....................................................45 Feedback Loop Compensation.............................46 PCB Layout Considerations................................. 47 Output Current Sensing.......................................48 Output Voltage Sensing.......................................50 Soft-Start and Stop............................................. 51 Time-Based Output Sequencing and Ramping.... 51 Voltage-Based Output Sequencing...................... 52 Using Output Voltage Servo................................54 Using AVP...........................................................54 PWM Frequency Synchronization........................55 PolyPhase Operation and Load Sharing..............56 External Temperature Sense................................60 Resistor Configuration Pins.................................60 Internal Regulator Outputs..................................62 IC Junction Temperature.....................................62 Derating EEPROM Retention at Temperature.......63 Configuring Open-Drain Pins...............................63 PMBus Communication and Command Processing.64 Status and Fault Log Management......................65 LTpowerPlay - An Interactive Digital Power GUI.65 Interfacing to the DC1613....................................66 Design Example...................................................66 PMBus COMMAND DETAILS.............................. 70 Addressing and Write Protect.................................. 70 PAGE................................................................... 70 PAGE_PLUS_WRITE........................................... 70 PAGE_PLUS_READ............................................. 71 WRITE_PROTECT................................................ 71 MFR_ADDRESS..................................................72 MFR_RAIL_ADDRESS........................................72 General Device Configuration.................................. 72 PMBUS_REVISION..............................................72 CAPABILITY.........................................................72 MFR_CONFIG_ALL_LTC3882-1..........................73 On, Off and Margin Control......................................73 ON_OFF_CONFIG.................................................73 OPERATION......................................................... 74 MFR_RESET........................................................ 74 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Table of Contents PWM Configuration................................................. 75 FREQUENCY_SWITCH......................................... 75 MFR_PWM_CONFIG_LTC3882-1........................ 76 MFR_CHAN_CONFIG_LTC3882-1.......................77 MFR_PWM_MODE_LTC3882-1.......................... 78 Input Voltage and Limits.......................................... 79 VIN_ON............................................................... 79 VIN_OFF.............................................................. 79 VIN_OV_FAULT_LIMIT......................................... 79 VIN_UV_WARN_LIMIT........................................ 79 Output Voltage and Limits.......................................80 VOUT_MODE.......................................................80 VOUT_COMMAND...............................................80 MFR_VOUT_MAX................................................80 VOUT_MAX......................................................... 81 MFR_VOUT_AVP................................................. 81 VOUT_MARGIN_HIGH......................................... 81 VOUT_MARGIN_LOW......................................... 81 VOUT_OV_FAULT_LIMIT..................................... 81 VOUT_OV_WARN_LIMIT.....................................82 VOUT_UV_WARN_LIMIT.....................................82 VOUT_UV_FAULT_LIMIT.....................................82 Output Current and Limits.......................................83 IOUT_CAL_GAIN.................................................83 MFR_IOUT_CAL_GAIN_TC..................................83 IOUT_OC_FAULT_LIMIT......................................83 IOUT_OC_WARN_LIMIT......................................83 Output Timing, Delays, and Ramping......................84 MFR_RESTART_DELAY.......................................84 TON_DELAY........................................................84 TON_RISE...........................................................84 TON_MAX_FAULT_LIMIT....................................85 VOUT_TRANSITION_RATE..................................85 TOFF_DELAY.......................................................85 TOFF_FALL..........................................................85 TOFF_MAX_WARN_LIMIT...................................85 External Temperature and Limits.............................86 MFR_TEMP_1_GAIN............................................86 MFR_TEMP_1_OFFSET........................................86 OT_FAULT_LIMIT.................................................86 OT_WARN_LIMIT................................................86 UT_FAULT_LIMIT................................................. 87 Status Reporting...................................................... 87 STATUS_BYTE..................................................... 87 STATUS_WORD...................................................88 STATUS_VOUT....................................................88 STATUS_IOUT.....................................................89 STATUS_INPUT...................................................89 STATUS_TEMPERATURE.....................................89 STATUS_CML......................................................90 STATUS_MFR_SPECIFIC.....................................90 MFR_PADS_LTC3882-1...................................... 91 MFR_COMMON................................................... 91 CLEAR_FAULTS..................................................92 Telemetry.................................................................92 READ_VIN...........................................................92 MFR_VIN_PEAK..................................................93 READ_VOUT........................................................93 MFR_VOUT_PEAK...............................................93 READ_IOUT.........................................................93 MFR_IOUT_PEAK................................................93 READ_POUT........................................................93 READ_TEMPERATURE_1....................................94 MFR_TEMPERATURE_1_PEAK...........................94 READ_TEMPERATURE_2....................................94 MFR_TEMPERATURE_2_PEAK...........................94 READ_DUTY_CYCLE...........................................94 READ_FREQUENCY.............................................94 MFR_CLEAR_PEAKS..........................................94 Fault Response and Communication........................95 VIN_OV_FAULT_RESPONSE................................95 VOUT_OV_FAULT_RESPONSE.............................96 VOUT_UV_FAULT_RESPONSE.............................96 IOUT_OC_FAULT_RESPONSE.............................. 97 OT_FAULT_RESPONSE........................................98 UT_FAULT_RESPONSE........................................98 MFR_OT_FAULT_RESPONSE..............................98 TON_MAX_FAULT_RESPONSE...........................99 MFR_RETRY_DELAY...........................................99 SMBALERT_MASK............................................ 100 MFR_FAULT_PROPAGATE_LTC3882-1............. 101 MFR_FAULT_RESPONSE................................... 101 EEPROM User Access............................................ 102 MFR_FAULT_LOG.............................................. 102 MFR_FAULT_LOG_CLEAR................................. 102 STORE_USER_ALL........................................... 103 RESTORE_USER_ALL....................................... 103 MFR_COMPARE_USER_ALL............................ 103 MFR_FAULT_LOG_STORE................................ 103 MFR_EE_xxxx................................................... 103 USER_DATA_0x................................................ 103 Unit Identification.................................................. 104 MFR_ID............................................................. 104 MFR_MODEL..................................................... 104 MFR_SERIAL..................................................... 104 Typical Applications..................................... 105 Package Description.................................... 107 Typical Application...................................... 108 Related Parts............................................. 108 38821f For more information www.linear.com/LTC3882-1 3 LTC3882-1 Absolute Maximum Ratings Pin Configuration (Note 1) ISENSE1+ ISENSE1- VSENSE1+ VSENSE1- VSENSE0- VSENSE0+ ISENSE0- ISENSE0+ IAVG0 FB0 40 39 38 37 36 35 34 33 32 31 COMP0 1 30 IAVG1 TSNS0 2 29 FB1 TSNS1 3 28 COMP1 VINSNS 4 27 PGOOD1 41 GND IAVG_GND 5 PGOOD0 6 26 PWM1 25 VCC PWM0 7 24 VDD33 SYNC 8 23 SHARE_CLK SCL 9 22 VDD25 SDA 10 21 PHAS_CFG FREQ_CFG VOUT1_CFG ASEL1 ASEL0 RUN1 RUN0 FAULT1 ALERT 11 12 13 14 15 16 17 18 19 20 VOUT0_CFG *See Derating EEPROM Retention at Temperature in the Applications Information section for junction temperatures in excess of 125C. TOP VIEW FAULT0 VCC Supply Voltage..................................... -0.3V to 15V VINSNS Voltage.......................................... -0.3V to 40V VSENSEn -....................................................... -0.3V to 1V VSENSEn+, ISENSEn+, ISENSEn -......................... -0.3V to 6V FBn, COMPn, TSNSn, IAVG_GND, IAVGn....... -0.3V to 3.6V SYNC, FAULTn, PGOODn, SHARE_CLK.........-0.3V to 3.6V SCL, SDA, RUNn, ALERT............................ -0.3V to 5.5V ASELn, VOUTn_CFG, FREQ_CFG, PHAS_CFG............................................... -0.3V to 2.75V PWMn, VDD25................................................... (Note 13) VDD33................................................................ (Note 14) Operating Junction Temperature (Notes 2, 3)........................................... -40C to 125C* Storage Temperature Range................. -65C to 125C* UJ PACKAGE 40-LEAD (6mm x 6mm) PLASTIC QFN TJMAX = 125C, JA = 33C/W , JC = 2.5C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3882EUJ-1#PBF LTC3882EUJ-1#TRPBF LTC3882UJ-1 40-Lead (6mm x 6mm) Plastic QFN -40C to 125C LTC3882IUJ-1#PBF LTC3882IUJ-1#TRPBF LTC3882UJ-1 40-Lead (6mm x 6mm) Plastic QFN -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0- = VSENSE1- = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IC Supply VCC VCC Voltage Range VDD33 = Internal LDO VDD33_EXT VDD33 Voltage Range VCC = VDD33 (Note 6) l VUVLO Undervoltage Lockout Threshold VDD33 Rising Hysteresis l IQ IC Operating Current tINIT Controller Initialization Time 4.5 13.8 V 3 3.6 V 42 Delay from RESTORE_USER_ALL, MFR_RESET or VDD33 > VUVLO Until TON_DELAY Can Begin 3 V mV 32 mA 70 ms VDD33 Linear Regulator VDD33 VDD33 Regulator Output Voltage VCC 4.5V IDD33 VDD33 Current Limit VDD33 = 2.8V VDD33 = 0V 3.2 3.3 3.4 85 40 V mA mA VDD25 Linear Regulator VDD25 VDD25 Regulator Output Voltage IDD25 VDD25 Current Limit 2.25 2.5 2.75 95 V mA PWM Control Loops VINSNS VIN Sense Voltage Range RVINSNS VINSNS Input Resistance VOUT_R0 Range 0 Maximum VOUT Range 0 Set Point Error (Note 7) 3 0.6V VOUT 5V 0.6V VOUT 5V Range 0 Set Point Resolution VOUT_R1 Range 1 Maximum VOUT Range 1 Set Point Error (Note 7) 0.6V VOUT 2.5V 0.6V VOUT 2.5V Range 1 Set Point Resolution l l -0.5 -0.5 VSENSE+ = 5.5V VSENSE- = 0V IVSENSE VSENSE Input Current VLINEREG VCC Line Regulation, No Output Servo 4.5V VCC 13.2V (See Test Circuit) AVP AVP VOUT AVP = 10%, VOUT_COMMAND = 1.8V, ISENSE Differential Step 3mV to 12mV with IOUT_OC_WARN_LIMIT = 15mV 38 k 5.25 0.2 V % % mV 1.375 2.65 0.2 0.6875 0.5 0.5 235 -335 -0.02 l -118 V 278 -108 V % % mV A A 0.02 %/V -96 mV AV(OL) Error Amplifier Open-Loop Voltage Gain 87 dB SR Error Amplifier Slew Rate 9.5 V/s f0dB Error Amplifier Bandwidth (Note 12) 30 MHz ICOMP Error Amplifier Output Current Sourcing Sinking -2.6 34 mA mA RVSFB Resistance Between VSENSE+ and FB Range 0 Range 1 VISENSE ISENSE Differential Input Range ISENSE Input Current 0V VPIN 5.5V IAVG_VOS IAVG Current Sense Offset Referred to ISENSE Inputs fSYNC Slave Current Sharing Offset SYNC Frequency Error 52 37 67 49 -1 0.1 83 61 70 IISENSE VSIOS l l l -600 l -800 l -10 Referred to ISENSE Inputs 250kHz fSYNC 1.25MHz 175 300 k k mV 1 A 650 V V 700 V V 10 % 38821f For more information www.linear.com/LTC3882-1 5 LTC3882-1 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0- = VSENSE1- = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Voltage Supervisor VON_TOL Input ON/OFF Threshold Error NVON Input ON/OFF Threshold Resolution 15V VIN_ON 35V l -2 2 143 % mV Output Voltage Supervisors VUVOV_R0 Range 0 Maximum Threshold Range 0 Error Range 0 Threshold Resolution Range 0 Threshold Hysteresis VUVOV_R1 Range 1 Maximum Threshold Range 1 Error Range 1 Threshold Resolution Range 1 Threshold Hysteresis Output Current Supervisors Output Current Limit Tolerance VILIM_TOL ISENSE+ - ISENSE- 2V VOUT 5V (Falling for UV and Rising for OV) 1V VOUT 2.5V (Falling for UV and Rising for OV) 15mV < ISENSE+ - ISENSE- 30mV 30mV < ISENSE+ - ISENSE- 50mV 50mV < ISENSE+ - ISENSE- 70mV 1LSB l l l l l -1 -1 5.5 11 2.75 5.5 -1.7 -2.5 -5.2 ISENSE+ - ISENSE- Threshold Resolution NlLIM ADC Readback Telemetry (Note 8) VINSNS Readback Resolution (Note 9) NVIN VINSNS Total Unadjusted Readback Error 4.5V VINSNS 38V VIN_TUE PWM Duty Cycle Resolution PWM Duty Cycle Total Unadjusted Readback Error VOUT Readback Resolution VOUT Total Unadjusted Readback Error (Note 9) PWM Duty Cycle = 12.5% NISENSE IOUT Readback Resolution LSB Step Size (at ISENSE) ISENSE_TUE ISENSE_OS NTEMP TEXT_TUE IOUT Total Unadjusted Readback Error IOUT Zero-Code Offset Voltage Temperature Resolution External Temperature Total Unadjusted Readback Error (Note 9) 0mV |ISENSE+ - ISENSE-| < 16mV 16mV |ISENSE+ - ISENSE-| < 32mV 32mV |ISENSE+ - ISENSE-| < 63.9mV 63.9mV |ISENSE+ - ISENSE-| 70mV |ISENSE+ - ISENSE-| 6mV, 0V VOUT 5.5V NVOUT VOUT_TUE Internal Temperature Total Unadjusted Readback Error Update Rate tCONVERT Internal EEPROM (Notes 4, 6) Endurance Number of Write Operations Retention Stored Data Retention Mass Write Time STORE_USER_ALL Execution Duration 6 1 27 0.4 10 0.5 2 10 -2 0.6V VOUT 5.5V, Constant Load l TINT_TUE 54 1.7 2.5 5.2 l NDC DCTUE 1 -0.5 2 244 0.2 0.5 10 15.625 31.25 62.5 125 l -1 1 32 0.25 TSNS0, TSNS1 1.85V (Note 10) MFR_PWM_MODE_LTC3882-1[6] = 0 MFR_PWM_MODE_LTC3882-1[6] = 1 Internal Diode (Note 10) l l -3 -7 (Note 11) 0C TJ 85C During All Write Operations TJ 125C 0C TJ 85C During All Write Operations 3 7 V % mV mV V % mV mV mV mV mV mV Bits % % Bits % V % % Bits V V V V % V C 1 C C C 100 ms 0.2 Cycles Years s 10,000 10 2 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0- = VSENSE1- = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER CONDITIONS Digital Inputs (SCL, SDA, RUNn, FAULTn, SYNC, SHARE_CLOCK) Input High Voltage SCL, SDA, RUN0, RUN1, FAULT0, FAULT1 VIH SYNC, SHARE_CLK Input Low Voltage SCL, SDA, RUN0, RUN1, FAULT0, FAULT1 VIL SYNC, SHARE_CLK VHYST Input Hysteresis SCL, SDA CIN Input Capacitance SCL, SDA, RUN0, RUN1, FAULT0, FAULT1, SYNC, SHARE_CLK (Note 12) tFILT Input Digital Filter Delay FAULT0, FAULT1 RUN0, RUN1 MIN l l TYP MAX 2.0 1.8 1.4 0.6 l l 80 UNITS V V V V mV 10 3 10 pF s s Digital Outputs (SCL, SDA, RUNn, FAULTn, SYNC, SHARE_CLOCK, ALERT, PWMn, PGOODn) VOL Output Low Voltage ISINK = 3mA; SDA, SCL, RUN0, RUN1, FAULT0, FAULT1, SYNC, SHARE_CLK, ALERT, ISINK = 2mA; PWMn, PGOODn l l 0.2 l 0.4 V 0.3 V 1 5 A A 5 A VOH PWMn Output High Voltage ISOURCE = 2mA ILKG Output Leakage Current 0V PWM0, PWM1, PGOOD0, PGOOD1 VDD33 0V FAULT0, FAULT1, SYNC, SHARE_CLK 3.6V 0V RUN0, RUN1 5.5V 0V SCL, SDA, ALERT 5.5V tRO PWMn Output Rise Time CLOAD = 30pF, 10% to 90% 5 ns tFO PWMn Output Fall Time CLOAD = 30pF, 90% to 10% 4 ns 2.7 V -1 -5 l -5 Serial Bus Timing fSMB Serial Bus Operating Frequency l 10 tBUF Bus Free Time Between Stop and Start l 1.3 s tHD,STA Hold Time After (Repeated) Start Condition. After This Period, the First Clock Is Generated l 0.6 s tSU,STA Repeated Start Condition Setup Time l 0.6 s tSU,STO Stop Condition Setup Time l 0.6 s tHD,DAT Data Hold Time: Receiving Data Transmitting Data l l 0 0.3 tSU,DAT Input Data Setup Time l 100 tTIMEOUT Clock Low Timeout l 25 35 ms tLOW Serial Clock Low Period l 1.3 10000 s tHIGH Serial Clock High Period l 0.6 400 0.9 kHz ns s ns s 38821f For more information www.linear.com/LTC3882-1 7 LTC3882-1 Electrical Characteristics Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3882-1 is tested under pulsed load conditions such that TJ TA. The LTC3882-1E is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3882-1I is guaranteed over the full -40C to 125C operating junction temperature range. Junction temperature TJ is calculated in C from the ambient temperature TA and power dissipation PD according to the formula: TJ = TA + (PD * JA) where JA is the package thermal impedance. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Refer to the Applications Information section. Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 4: EEPROM endurance, retention and mass write times are guaranteed by design, characterization and correlation with statistical process controls. Minimum retention applies only for devices cycled less than the minimum endurance specification. EEPROM read commands (e.g. RESTORE_USER_ALL) are valid over the entire specified operating junction temperature range. 8 Note 5: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 6: Minimum EEPROM endurance, retention and mass write time specifications apply when writing data with 3.15V VDD33 3.45V. EEPROM read commands are valid over the entire specified VDD33 operating range. Note 7: Specified VOUT error with AVP = 0% requires servo mode to be set with MFR_PWM_MODE_LTC3882-1 command bit 6. Performance is guaranteed by testing the LTC3882-1 in a feedback loop that servos VOUT to a specified value. Note 8: ADC tested with PWMs disabled. Comparable capability demonstrated by in-circuit evaluations. Total Unadjusted Error includes all gain and linearity errors, as well as offsets. Note 9: Internal 32-bit calculations using 16-bit ADC results are limited to 10-bit resolution by PMBus Linear 11-bit data format. Note 10: Limits guaranteed by TSNS voltage and current measurements during test, including ADC readback. Note 11: Data conversion is done in round robin fashion. All inputs signals are continuously scanned in sequence resulting in a typical conversion latency of 100ms. Note 12: Guaranteed by design. Note 13: Do not apply a voltage or current source directly to these pins. They should only be connected to passive RC loads, otherwise permanent damage may occur. Note 14: Do not apply a voltage source to this pin unless shorted to VCC. See Electrical Characteristics for applicable limits beyond which permanent damage may occur. 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Typical Performance Characteristics LTC3882-1 1.0V Regulated Output vs Temperature Typical LTC3882-1 Output Voltage Distribution at 0C 1000 1.0 0.9995 1200 1094 UNITS 900 VOUT_COMMAND = 1.0V DIGITAL SERVO 800 ENGAGED 700 NUMBER OF CHANNELS VOUT (V) VIN = 12V VOUT_COMMAND = 1.0V DIGITAL SERVO ENGAGED 1.0005 I OUT = 6.5A 600 500 400 300 0.999 1078 UNITS VOUT_COMMAND = 1.0V DIGITAL SERVO ENGAGED 1000 NUMBER OF CHANNELS 1.001 Typical LTC3882-1 Output Voltage Distribution at 105C 800 600 400 200 200 100 0.9985 -5 15 35 55 TA (C) 75 38821 G01 38821 G01a Efficiency and Loss vs Load (2-Phase Using FDMF5820DC DRMOS) Efficiency vs Load Current (1-Phase Using D12S1R880A Power Block) 92 13 95 7 86 85 84 5 83 85 3.3V 2.5V 1.8V 1.5V 1.2V 1.0V 80 VIN = 12V VOUT = 1V SYNC = 500kHz 82 81 0 10 20 30 40 50 60 LOAD CURRENT (A) 70 3 80 1 75 0 10 4000 3500 1500 1000 1000 -400 -300-200-100 0 100 200 300 400 CH1 ISENSE OFFSET TO IDEAL (V) 38821 G06 0 30 50 20 40 LOAD CURRENT (A) 60 70 11783 UNITS FROM 3 LOTS TJ = 121C CHO MASTER 3000 2500 2000 1500 1000 500 500 10 Typical Distribution of Slave IOUT Offset (Not Including DCR Mismatch) 4500 2000 0 38821 G05 NUMBER OF ICs NUMBER OF ICs NUMBER OF ICs 80 8593 UNITS FROM 3 LOTS 3000 T = 38C J CHO MASTER 2500 1500 0 82 3500 2000 86 Typical Distribution of Slave IOUT Offset (Not Including DCR Mismatch) 9595 UNITS 3500 FROM 3 LOTS TA = -40C 3000 TJ = -22C CHO MASTER 2500 88 38821 G04 4000 38821 G02 84 40 20 30 LOAD CURRENT (A) 38821 G03 Typical Distribution of Slave IOUT Offset (Not Including DCR Mismatch) 2.5 90 EFFICIENCY (%) 87 POWERLOSS (W) 9 EFFICIENCY (%) 90 88 2 VIN = 12V VOUT = 1.5V 92 89 EFFICIENCY (%) 94 11 90 1.5 Efficiency vs Load Current (3-Phase Using D12S1R845A Power Block) VIN = 12V 91 80 0 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 VOUT ERROR (mV) 0 -1.25 -1 -0.75-0.5-0.25 0 0.25 0.5 0.75 1 1.25 VOUT ERROR (mV) 95 500 -400 -300-200-100 0 100 200 300 400 CH1 ISENSE OFFSET TO IDEAL (V) 38821 G07 0 -300 -200-100 0 100 200 300 400 500 CH1 ISENSE OFFSET TO IDEAL (V) 38821 G08 38821f For more information www.linear.com/LTC3882-1 9 LTC3882-1 Typical Performance Characteristics 3-Phase DC Output Current Sharing (Using D12S1R845A Power Block 20 Load Step Transient Current Sharing (Using FDMF6707B DrMOS) CHANNEL 1 CHANNEL 2 CHANNEL 3 18 16 IOUT 20A/DIV IOUT 20A/DIV 14 PHASE CURRENT (A) Load Dump Transient Current Sharing (Using FDMF6707B DrMOS) VOUT 20mV/DIV VOUT 20mV/DIV 12 IL1, IL2 10A/DIV 10 8 IL1, IL2 10A/DIV 6 4 VOUT = 1V VIN = 12V SYNC = 500kHz L = 320nH 2 0 0 10 20 30 40 50 60 TOTAL RAIL CURRENT (A) 80 70 38821 G10 5s/DIV VOUT = 1V VIN = 12V SYNC = 500kHz L = 320nH 38821 G11 5s/DIV 38821 G09 Efficiency and Power Loss vs Input Voltage (1-Phase Using LTC4449) 100 3.0 VO = 1.8V 98 EFFICIENCY (%) 2.0 92 90 1.5 88 1.0 86 84 10 15 20 VIN (V) IOUT (10A/DIV) VSW (10V/DIV) VOUT (10mV/DIV) 25mVP-P 0.5 POWER FET: BSC050N04LS G SYNC FET: BSC010N04LS 5 POWERLOSS (W) 94 80 VOUT (20mV/DIV) 2.5 96 82 25 30 100s/DIV 0 38821 G12 3+1 Channel Crosstalk (Using D12S1R845A Power Blocks) VOUT0 (1-PHASE) 20mV/DIV 25% LOAD STEP 100s/DIV 38821 G15 38821 G14 2s/DIV VOUT = 0.9V/90A VIN = 12V SYNC = 500kHz L = 210nH VOUT = 1V/25A VIN = 12V SYNC = 1MHz L = 210nH Load Step Transient Response Using AVP Line Step Transient Response (1-phase Using LTC4449) IO 10A/DIV IOUT1 10A/DIV IOUT (10A/DIV) 38821 G13 VIN 2V/DIV VOUT1 (3-PHASE) 20mV/DIV 10 1-Phase Single Cycle Response (Using D12S1R860A Power Block with COUT = 6 x 100F X5R 1210) 3-Phase Transient Response (Using D12S1R860A Power Block) 7V 1.8V VOUT 50mV/DIV VOUT 10mV/DIV 200s/DIV 38821 G16 200s/DIV 38821 G17 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Typical Performance Characteristics Soft-Start Ramp Start-Up Into a Prebiased Load VOUT 0.5V/DIV VOUT 0.5V/DIV 0V IL1, IL2 10A/DIV IL1, IL2 10A/DIV VIN = 12V 1ms/DIV 38821 G18 1.7995 RUN 2V/DIV VOUT 1V/DIV VIN = 12V Regulated Output vs Temperature 1.8000 Soft-Off Ramp 38821 G19 1ms/DIV VOUT_COMMAND INL VOUT_COMMAND DNL 1.5 VOUT_COMMAND = 1.8V DIGITAL SERVO OFF 1.0 0.8 1.0 0.6 0.4 1.7985 0.5 DNL (LSB) INL (LSB) VOUT (V) 1.7990 0 1.7980 0.2 0 -0.2 -0.4 -0.5 1.7975 -0.6 1.7970 -40 -20 0 20 40 60 80 TEMPERATURE (C) -1.0 0.3 100 120 1.1 1.9 38821 G01a Output Overvoltage Threshold Error vs Temperature 0 -0.05 -0.10 VOUT_OV_FAULT_LIMIT = 2V VOUT RANGE = 1 -0.15 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 38821 G21 -0.8 0.3 5.1 5.5 4.3 1.1 500.2 1.0 500.1 0.8 0.6 0.4 0.2 0 4.3 5.1 5.5 38821 G02 500.0 499.9 499.8 499.7 -0.2 499.6 -0.4 -40 -20 499.5 -40 -20 20 40 60 80 TEMPERATURE (C) 2.7 3.5 VOUT (V) PWM Frequency vs Temperature 1.2 0 1.9 38821 G01 PWM FREQUENCY (kHz) OUTPUT OC THRESHOLD ERROR (%) 0.05 2.7 3.5 VOUT (V) Output Overcurrent Threshold Error vs Temperature 0.10 VOUT OV THRESHOLD ERROR (%) 38821 G20 5ms/DIV TOFF_DELAY = 10ms TOFF_FALL = 5ms 100 120 38821 G22 FREQUENCY_SWITCH = 500kHz 0 20 40 60 80 TEMPERATURE (C) 100 120 38821 G23 38821f For more information www.linear.com/LTC3882-1 11 LTC3882-1 Typical Performance Characteristics VIN(SNS) ADC TUE 0.40 IOUT ADC TUE 8 0.30 MEASUREMENT ERROR (mV) MEASUREMENT ERROR (mV) -1 VOUT ADC TUE -2 -3 -4 -5 -6 -7 6 MEASUREMENT ERROR (mA) 0 0.20 0.10 0 -0.10 -0.20 -8 -0.30 -9 -0.40 0.5 0 5 10 15 20 25 VINSNS (V) 30 35 40 38821 G24 1.0 0 -2 -4 -6 1 1.5 2 2.5 3 3.5 VOUT (V) 4 4.5 5 -8 5.5 10 5 15 OUTPUT CURRENT (A) 0 38821 G25 20 38821 G26 IC Operating Current vs Temperature 31.0 110 0.8 VCC = 14V 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 ICC OPERATING CURRENT (mA) 30.8 SHARE_CLK FREQUENCY (kHz) MEASUREMENT ERROR (C) 2 SHARE_CLK Frequency vs Temperature Temperature ADC TUE 105 100 95 30.6 30.4 30.2 30.0 29.8 29.6 -0.8 -1.0 -45 -25 -5 15 35 55 75 95 115 ACTUAL TEMPERATURE (C) 38821 G27 12 4 90 -50 -30 -10 10 30 50 70 TEMPERATURE (C) 90 110 38821 G28 29.4 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 38821 G29 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Pin Functions COMP0/COMP1 (Pin 1/Pin 29): Error Amplifier Outputs. PWM duty cycle increases with this control voltage. These are true low impedance outputs and cannot be directly connected together when active. For PolyPhase operation, wiring FB to VDD33 will three-state the error amplifier output of that channel, making it a slave. PolyPhase control is then implemented in part by connecting all slave COMP pins together to one master error amplifier output. TSNS0/TSNS1 (Pin 2/Pin 3): External Temperature Sense Inputs. The LTC3882-1 supports two methods of calculation of external temperature based on forward-biased P/N junctions between these pins and GND. VINSNS (Pin 4): VIN Supply Sense. Connect to the VIN power supply to provide line feedforward compensation. A change in VIN immediately modulates the input to the PWM comparator and inversely changes the pulse width to provide excellent transient line regulation and fixed modulator voltage gain. An external lowpass filter can be added to this pin to prevent noisy signals from affecting the loop gain. IAVG_GND (Pin 5): IAVG Ground Reference. The same IAVG_GND should be shared between all channels of a PolyPhase rail and connected to system ground at a single point. IAVG_GND may be wired directly to GND on ICs that do not share phases with other chips. PGOOD/PGOOD1 (Pin 6/Pin 27): Power Good Indicator Open-Drain Outputs. These outputs are driven low through a 30s filter when the respective channel output is below its programmed UV fault limit or above its programmed OV fault limit. If used, a pull-up resistor is required in the application. Operating voltage range is GND to VDD33. PWM0/PWM1 (Pin 7/Pin 26): PWM Three-State Control Outputs. These pins provide single-wire PWM switching control for each channel to an external gate driver, DrMOS or power block. Operating voltage range is GND to VDD33. SYNC (Pin 8): External Clock Synchronization Input and Open-Drain Output. If desired, an external clock can be applied to this pin to synchronize the internal PWM channels. If the LTC3882-1 is configured as a clock master, this pin will also pull to ground at the selected PWM switching frequency with a 125ns pulse width. A pull-up resistor to 3.3V is required in the application if SYNC is driven by any LTC3882-1. Minimize the capacitance on this line to ensure its time constant is fast enough for the application. SCL (Pin 9): Serial Bus Clock Input. A pull-up resistor to 3.3V is required in the application. SDA (Pin 10): Serial Bus Data Input and Output. A pull-up resistor to 3.3V is required in the application. ALERT (Pin 11): Open-Drain Status Output. This pin may be connected to the system SMBALERT wire-AND interrupt signal and should be left open if not used. If used, a pull-up resistor is required in the application. Operating voltage range is GND to VDD33. FAULT0/FAULT1 (Pin 12/Pin 13): Programmable Digital Inputs and Open-Drain Outputs for Fault Sharing. Used for channel-to-channel fault communication and propagation. These pins should be left open if not used. If used, a pull-up resistor to 3.3V is required in the application. RUN0/RUN1 (Pin 14/Pin 15): Run Control Inputs and Open-Drain Outputs. A voltage above 2V is required on these pins to enable the respective PWM channel. The LTC3882-1 will drive these pins low under certain reset/ restart conditions regardless of any PMBus command settings. A pull-up resistor to 3.3V is required in the application. ASEL0/ASEL1 (Pin 16/Pin 17): Serial Bus Address Select Pins. Connect optional 1% resistor dividers between VDD25 and GND to these pins to select the serial bus interface address. Refer to the Applications Information section for more detail. VOUT0_CFG/VOUT1_CFG (Pin 18/Pin 19): Output Voltage Configuration Pins. Connect optional 1% resistor dividers between VDD25 and GND to these pins to select the output voltage for each channel. Refer to the Applications Information section for more detail. FREQ_CFG (Pin 20): Frequency Configuration Pin. Connect an optional 1% resistor divider between VDD25 and GND to this pin to configure PWM switching frequency. Refer to the Applications Information section for more detail. 38821f For more information www.linear.com/LTC3882-1 13 LTC3882-1 Pin Functions PHAS_CFG (Pin 21): Phase Configuration Pin. Connect an optional 1% resistor divider between VDD25 and GND to this pin to configure the phase of each PWM channel relative to SYNC. Refer to the Applications Information section for more detail. VDD25 (Pin 22): Internal 2.5V Regulator Output. Bypass this pin to GND with a low ESR 1F capacitor. Do not load this pin with external current beyond that required for local LTC3882-1 configuration pins, if any. SHARE_CLK (Pin 23): Share Clock Open-Drain Output (bussed). Share Clock, nominally 100kHz, is used to sequence multiple rails in a power system utilizing more than one LTC PSM controller. A pull-up resistor is required in the application. Minimize the capacitance on this line to ensure the time constant is fast enough for the application. Operating voltage range is GND to VDD33. VDD33 (Pin 24): Internal 3.3V Regulator Output. Bypass this pin to GND with a low ESR 2.2F capacitor. The LTC3882-1 may also be powered from an external 3.3V rail attached to this pin, if also shorted to VCC. Do not overload this pin with external system current. Local pull-up resistors for the LTC3882-1 itself may be powered from VDD33. Refer to the Applications Information section for more detail. VCC (Pin 25): 3.3V Regulator Input. Bypass this pin to GND with a capacitor (0.1F to 1F ceramic) in close proximity to the IC. -/V - VSENSE0 SENSE1 (Pin 35/Pin 34): Negative Output Voltage Sense Inputs. These pins must still be properly connected on slave channels for accurate output current telemetry. 14 VSENSE0+/VSENSE1+ (Pin 36/Pin 33): Positive Output Voltage Sense Inputs. These pins must still be properly connected on slave channels for accurate output current telemetry. ISENSE0-/ISENSE1- (Pin 37/Pin 32): Current Sense Amplifier Inputs. The (-) inputs to the amplifiers are normally connected to the low side of a DCR sensing network or output current sense resistor for each phase. ISENSE0+/ISENSE1+ (Pin 38/Pin 31): Current Sense Amplifier Inputs. The (+) inputs are normally connected to the high side of an output current sense resistor or the R-C midpoint of a parallel DCR sense circuit. IAVG0/IAVG1 (Pin 39/Pin 31): Average Current Control Pins. A capacitor connected between these pins and IAVG_GND stores a voltage proportional to the average output current of the master channel. PolyPhase control is then implemented in part by connecting all slave IAVG pins together to the master IAVG output. This pin should be left open on channels that control single-phase outputs. Operating voltage range is GND to 2.1V. FB0/FB1 (Pin 40/Pin 30): Error Amplifier Inverting Inputs. These pins provide an internally scaled version of the output voltage for use in loop compensation. Refer to the Applications Information section for additional details on compensating the output voltage control loop with external components. GND (Exposed Pad Pin 41): Ground and VSENSE1-. All small-signal and compensation components should connect to this pad, which also serves as the negative voltage sense input for channel 1. The exposed pad must be soldered to a suitable PCB copper ground plane for proper electrical operation and to obtain the specified package thermal resistance. 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Block Diagram ROM RAM EEPROM VINSNS R_CONFIG IAVG0 MCU AND CUSTOM LOGIC SHARE_CLK PMBus ISENSE0 2.5V REGULATOR 12-BIT DAC PWM0 VSENSE0 PGOOD0 SYNC PWM0 PLL VOLTAGE REFERENCE VREF IAVG_GND 3.3V REGULATOR VCC PWM1 VDD33 PGOOD1 BIAS AND HOUSEKEEPING VSENSE1 IAVG1 INTERNAL DATA BUS VSENSE0 16-BIT ADC ISENSE0 VSENSE1 PWM1 ISENSE1 VINSNS PWM0 TSNS0 PWM1 12-BIT DAC VINSNS ANALOG MUX INTERNAL TEMPERATURE ISENSE1 TSNS1 3882-1 BD 38821f For more information www.linear.com/LTC3882-1 15 LTC3882-1 Test Circuit (Channel 0 Example) LTC3882-1 1.024V VR 12-BIT D/A DIGITAL + EA - VSENSE0- VSENSE0+ 35 FB0 36 COMP0 40 1 + LTC1055 TARGET = VOUT_COMMAND - 1V 38821 TC Timing Diagram SDA tf tLOW tr tSU(DAT) tHD(SDA) tf tSP tr tBUF SCL tHD(STA) tHD(DAT) tHIGH tSU(STA) START CONDITION tSU(STO) 38821 TD REPEATED START CONDITION STOP CONDITION START CONDITION Operation Overview Major features include: The LTC3882-1 is a dual channel/dual phase, constant frequency analog voltage mode controller for DC/DC stepdown applications. It features a PMBus compliant digital interface for monitoring and control of important power system parameters. The chip operates from an IC power supply between 3V and 13.2V and is intended for conversion from VIN between 3V and 38V to output voltages between 0.5V and 5.25V. It is designed to be used in a switching architecture with external FET drivers, including higher level integrations such as non-isolated power blocks. * Digitally Programmable Output Voltage 16 * Digitally Programmable Output Current Limit * Digitally Programmable Input Voltage Supervisor * Digitally Programmable Output Voltage Supervisors * Digitally Programmable Switching Frequency * Digitally Programmable On and Off Delay Times * Digitally Programmable Soft-Start/Stop 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Operation * Operating Condition Telemetry Main Control Loop * Phase Locked Loop for Synchronous PolyPhase Operation (2, 3, 4, 6, or 8 phases) The LTC3882-1 utilizes constant frequency voltage mode control with leading-edge modulation. This provides improved response to a load step increase, especially at larger VIN/VOUT ratios found in the low voltage, high current solutions demanded by modern digital subsystems. The LTC3882-1 leading-edge modulation architecture does not have a minimum on-time requirement. Minimum duty cycle will be determined by performance limits of the external power stage. The IC is also capable of active voltage positioning (AVP) to afford the smallest output capacitors possible for a given output voltage accuracy over the anticipated full load range. The LTC3882-1 error amplifiers have high bandwidth, low offset and low output impedance, allowing the control loop compensation network to be optimized for very high crossover frequencies and excellent transient response. The controller also achieves outstanding line transient response by using input feedforward compensation to instantaneously adjust PWM duty cycle and significantly reduce output under/ overshoot during supply voltage changes. This also has the added advantage of making the DC loop gain independent of input voltage. * Fully Differential Load Sense * Non-Volatile Configuration Memory * Optional External Configuration Resistors for Key Operating Parameters * Optional Time-Base Interconnect for Synchronization Between Multiple Controllers * Fault Event Data Logging * Capable of Standalone Operation with Default Factory Configuration * PMBus Revision 1.2 Compliant Interface up to 400kHz The PMBus interface provides access to important power management data during system operation including: * Average Input Voltage * Average Output Voltages * Average Output Currents * Average PWM Duty Cycles * Internal LTC3882-1 Temperature * External Sensed Temperatures * Warning and Fault Status, Including Input and Output Undervoltage and Overvoltage The LTC3882-1 supports four serial bus addressing schemes to access the individual PWM channels separately or jointly. Fault communication, reporting and system response behavior are fully configurable. Two fault I/Os are provided (FAULT0, FAULT1) that can be controlled independently. A separate ALERT pin also provides for a maskable SMBALERT#. Fault responses for each channel may be individually programmed, depending on the fault type. PMBus status commands allow fault reporting over the serial bus to identify a specific fault event. The main PWM control loop used for each channel is illustrated in Figure 1. During normal operation the top MOSFET (power switch) driving choke L1 is commanded off when the clock for that channel resets the RS latch. The power switch is commanded back on when the main PWM comparator VC, sets the RS latch. The error amplifier EA output (COMP) controls the PWM duty cycle to match the FB voltage to the EA positive terminal voltage in steady state. A patented circuit adjusts this output for VINSNS line feedforward. The positive terminal of the EA is connected to the output of a 12-bit DAC with values ranging from 0V to 1.024V. The DAC value is determined by the resistor configuration pins detailed in application Table 8, by values retrieved from internal EEPROM, or by a combination of PMBus commands to synthesize the desired output voltage. Refer to the following PMBus Command Details section of this document for more information. The LTC3882-1 supports two output ranges. EA can regulate the output voltage to 5.5x the DAC output (Range 0) or 2.75x the DAC output (Range 1). 38821f For more information www.linear.com/LTC3882-1 17 LTC3882-1 Operation LTC3882 MODE OSCILLATOR CLOCK R Q PWM0 PWM LOGIC S VIN 7 GATE DRIVER 0V VOC0 8-BIT DAC IOUT_OC_FAULT_LIMIT ILIM RAMP VC VREV IREV 4 VINSNS FEED FORWARD + + CA - + S - SLAVE ENABLE ISENSE0+ ISENSE0- IAVG0 IAVG_GND SLAVE DETECT RS 38 L1 CS VOUT 37 39 COUT 5 MASTER ENABLE VOV0 9-BIT DAC VOUT_OV_FAULT_LIMIT 9-BIT DAC VOUT_UV_FAULT_LIMIT OV UV VUV0 VSENSE0+ 36 9R (RANGE 0) - EA VSP0 FB0 12-BIT DAC VOUT_COMMAND 2R VSENSE0- + COMP0 LOOP COMPENSATION NETWORK 40 35 1 38821 F01 Figure 1. LTC3882-1 PWM Control Loop Diagram 18 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Operation VC discriminates its positive input against an internally generated PWM voltage ramp. The positive input is a composite control based on COMP voltage with line feedforward compensation, and current sharing if the channel controls a slave phase. When the ramp falls below this voltage the comparator trips and sets the PWM latch. If load current increases, VSENSE+ and FB will droop slightly with respect to the 12-bit DAC output. This causes the COMP voltage to increase until the average inductor current matches the new load current and the desired output voltage is restored. Programmable comparators ILIM and IREV monitor peak instantaneous forward and reverse inductor current for pulse-by-pulse protection. The top power MOSFET is immediately commanded off if the programmed positive limit is reached, and the bottom MOSFET is immediately commanded off if the negative limit is reached. Repeated peak overcurrent events cause an overcurrent fault to be set. When the top MOSFET is commanded off, the bottom MOSFET is normally commanded on. In continuous conduction mode (CCM) the bottom MOSFET stays on until comparator VC turns the top MOSFET back on. Otherwise in discontinuous conduction mode (DCM, also known as diode emulation) the bottom MOSFET is commanded off if the IREV comparator detects that the inductor current has decayed to approximately 0A. In any case the next PWM cycle starts when the clock for that channel again clears the RS latch. Power-Up and Initialization The LTC3882-1 is designed to provide stand-alone supply sequencing with controlled turn-on and turn-off functions. It operates from a single IC input supply of 3V to 13.2V while two on-chip linear regulators generate internal 2.5V and 3.3V. If VCC is below 4.5V, the VCC and VDD33 pins must be shorted together and limited to a maximum operating voltage of 3.6V. Controller configuration is reset by the internal UVLO threshold, where VDD33 must be at or above 3V and the internal 2.5V supply must be within about 20% of its regulated value. At that point the internal microcontroller begins initialization. A PMBus RESTORE_USER_ALL or MFR_RESET command forces this same initialization. The LTC3882-1 features an internal RAM built-in self-test (BIST) that runs during initialization. Should RAM BIST fail, the following steps are taken. * Device responds only at device address 0x7C and global addresses 0x5A and 0x5B * A persistent Memory Fault Detected is indicated by STATUS_CML * Internal EEPROM is not accessed * RUNn and SHARE_CLK are driven low continuously Normal operation can be restored if the RAM BIST subsequently passes, for instance as the result of another MFR_RESET command issued to address 0x7C. During initialization all PWM outputs are disabled. The RUNn pins and SHARE_CLK are held low and FAULTn pins are high impedance. External configuration resistors are identified and the contents of the onboard EEPROM are read into the controller command memory space. The LTC3882-1 can determine key operating parameters from external configuration resistors according to application Table 8 through Table 11. See the following Resistor Configuration Pins section for more detail. The resistor configuration pins only determine some of the preset values of the controller. The remaining values, retrieved from internal EEPROM, are programmed at the factory or with PMBus commands. If the configuration resistor pins are all open, the LTC3882-1 will use only EEPROM contents to determine all operating parameters. If Ignore Resistor Configuration Pins is set (bit 6 of MFR_CONFIG_ALL_LTC3882-1), the LTC3882-1 will use only its EEPROM contents to determine all operating parameters except device address. Unless both ASEL pins are completely open, the LTC3882-1 will always determine some portion of its device address from the resistors on these pins. See Serial Bus Addressing later in this section. The internal microcontroller typically requires 70ms to complete initialization from VDD33 3V. At that point, an internal comparator monitors VINSNS, which must exceed the VIN_ON threshold before output power sequencing can begin (SHARE_CLK released, ready for TON_DELAY). Accurate readback telemetry can then require an additional 100ms for initial round-robin A/D conversions. 38821f For more information www.linear.com/LTC3882-1 19 LTC3882-1 Operation Soft-Start The RUN pins are released for external control after the part initializes and VINSNS is greater than the VIN_ON threshold. If multiple LTC3882-1 ICs are used in an application, shared RUN pins are held low until all units initialize and VINSNS exceeds the VIN_ON threshold for all devices. A common SHARE_CLK signal can also ensure all connected devices use the same time reference for initial start-up even if RUN pins cannot be shared due to other design requirements. SHARE_CLK is not released by each IC until the conditions for power sequencing have been fully satisfied. After a channel RUN pin rises above 2V and any specified turn on delay (TON_DELAY) has expired, the LTC3882-1 performs an initial monotonic soft-start ramp on that channel. This is carried out with a digitally controlled ramp of the regulated output voltage from 0V to the commanded voltage set point over the programmed TON_RISE period, allowing inrush current control. During the soft-start ramp, the LTC3882-1 does not initiate PWM operation until the commanded output exceeds the actual rail voltage. This allows the regulator to start up into a pre-biased load even when using gate drivers or power blocks that do not support discontinuous operation. The soft-start feature is disabled by setting the value of TON_RISE to any time less than 0.25ms. Time-Based Output Sequencing The LTC3882-1 supports time-based on and off output sequencing using a shared time reference (SHARE_CLK). Following a valid qualified command to turn on, each output is enabled after waiting its programmed TON_DELAY. This can be used to sequence outputs in a prescribed order that can be preprogrammed as needed without hardware modification. Channel off-sequencing is accomplished in a similar way with the TOFF_DELAY command. Output Ramping Control The LTC3882-1 supports synchronized output on and off ramping control using a shared time reference (SHARE_ CLK). Power rail on and off relationships similar to those of conventional analog tracking functions can be achieved by using programmed delays and TON_RISE and TOFF_FALL 20 times. However, with LTC3882-1 digital control, on and off ramping methods need not be the same, and ramping configurations can be reprogrammed as needed without hardware modification. Programmable fault responses and fault sharing can ensure that any desired time-based output sequencing and ramping control is properly accomplished each time the system powers up or down. Refer to the Applications Information section for various LTC3882-1 hardware and PMBus command configurations needed to fully support synchronization for time-based sequencing and output ramping when using multiple ICs. Voltage-Based Output Sequencing It is also possible to sequence outputs using cascaded voltage events. To do this, the PGOOD status output from one PWM channel can be used to control the RUN pin of a downstream channel. This keeps the downstream channel off unless acceptable output conditions exist on the controlling channel. Output Disable Both PWM channels are disabled any time VINSNS is below the VIN_OFF threshold. The power stages are immediately shut off to stop the transfer of energy to the load(s) as quickly as possible. A PWM channel may also be disabled in response to certain internal fault conditions, an external fault propagated into a FAULT pin, or loss of SHARE_CLK. In these cases the power stage is immediately shut off to stop the transfer of energy to the load as quickly as possible. Refer to the following Fault Detection and Handling section for additional details related to fault recovery. Each PWM channel can be disabled with a PMBus OPERATION command at any time if enabled by ON_OFF_CONFIG. This will force a controlled turn-off response with defined delay (TOFF_DELAY) and ramp down rate (TOFF_FALL). The controller will maintain the programmed mode of operation for TOFF_FALL. In DCM, the controller will not draw current from the load and fall time will be set by output capacitance and load current. 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Operation Finally, each PWM channel can be commanded off by pulling the associated RUN pin low. Pulling the RUN pin low can force the channel to perform a controlled turn off or immediately disable the power stage, depending on the programming of the ON_OFF_CONFIG command. Minimum Output Disable Times When a PMBus OPERATION command is used to turn off an LTC3882-1 channel, a minimum output disable time of 120ms is imposed regardless of how quickly the channel is commanded back on. If bit 4 of MFR_CHAN_CONFIG is clear, a PMBus command to turn the channel off also pulses the RUN pin low. Once the RUN pin is pulled low internally or externally, a minimum output disable time (RUN forced low) of TOFF_DELAY + TOFF_FALL + 136ms is enforced. If MFR_RESTART_DELAY is greater than this mandatory minimum, the larger value of MFR_RESTART_DELAY is used. In either case the LTC3882-1 holds its own RUN pin low during the entire disable period. These minimum off times allow a consistent channel restart with coherent monitor ADC values and make the LTC3882-1 highly compatible with other LTC PMBus digital power system management products. Output Short Cycle An output short cycle condition is created when a master channel is commanded back on while waiting for TOFF_DELAY or TOFF_FALL to expire. Any time this occurs, the LTC3882-1 asserts the Short Cycle bit in STATUS_MFR_SPECIFIC. Device response at that point is governed by bits in MFR_CHAN_CONFIG_LTC3882-1 and SMBALERT_MASK. Refer to the detailed descriptions of those commands for additional details. Generally, the LTC3882-1 should be controlled so that short cycle conditions are not created during normal operation. Light Load Current Operation The LTC3882-1 has two modes of PWM operation: discontinuous conduction mode (DCM) and forced continuous conduction mode (CCM). Mode selection is made with the MFR_PWM_MODE command. In DCM, the inductor current is not allowed to reverse. The reverse current comparator IREV disables the external bottom MOSFET (synchronous rectifier) when the induc- tor current reaches approximately 0A, preventing it from going substantially negative. The external gate driver or power block must have short delays to a high impedance output, relative to the PWM cycle, to support DCM. Efficiency at light loads in CCM is lower than in DCM. Continuous conduction mode exhibits less interference with audio circuitry but may result in reverse inductor current, for instance at light loads or under large transient conditions. Switching Frequency and Phase There is a high degree of flexibility for setting the PWM operating frequency of the LTC3882-1. The switching frequency of the PWM can be established with an internal oscillator or an external time base. The internal phase-locked loop (PLL) synchronizes PWM control to this timing reference with proper phase relation, whether the clock is provided internally or externally. The device can also be configured to provide the master clock to other ICs through PMBus command, EEPROM setting, or external configuration resistors as outlined in application Table 10. For PMbus or EEPROM configuration, the LTC3882-1 is designated as a clock master by clearing bit 4 of MFR_CONFIG_ALL_LTC3882-1. As clock master, the LTC3882-1 will drive its open-drain SYNC pin at the selected rate with a pulse width of 125ns. An external pull-up resistor between SYNC and VDD33 is required in this case. Only one device connected to SYNC should be designated to drive the pin. If more than one LTC3882-1 sharing SYNC is programmed as clock master, just one of the devices is automatically elected to provide the clock. The others disable their SYNC outputs and indicate this with bit 10 of MFR_PADS_LTC3882-1. The LTC3882-1 will automatically accept an external SYNC input, disabling is own SYNC drive if necessary, as long as the external clock frequency is greater than 1/2 of the programmed internal oscillator. Whether configured to drive SYNC or not, the LTC3882-1 can continue PWM operation at the selected frequency (FREQUENCY_SWITCH) using its own internal oscillator, if an external clock signal is subsequently lost. The MFR_PWM_CONFIG_LTC3882-1 command can be used to configure the phase of each channel. Desired phase 38821f For more information www.linear.com/LTC3882-1 21 LTC3882-1 Operation can also be set from EEPROM or external configuration resistors as outlined in Table 10. Phase designates the relationship between the falling edge of SYNC and the internal clock edge that resets the PWM latch. That reset turns off the top power switch, producing a PWM falling edge. Additional small propagation delays to the PWM control pins will apply. proportionally summed with the master error amplifier COMP output to adjust the duty cycle and balance the current contribution of that phase. Additional hardware configuration and digital programming requirements apply in PolyPhase systems. Refer to the Applications Information section for complete details on building PolyPhase rails with the LTC3882-1. The phase relationships and frequency are independent of each other, providing numerous application options. Multiple LTC3882-1 ICs can be synchronized to realize a PolyPhase array. In this case the phases should be separated by 360/n degrees, where n is the number of phases driving the output voltage rail. Active Voltage Positioning PolyPhase Load Sharing Multiple LTC3882-1 ICs can be combined to provide a balanced load-share solution by configuring the necessary pins. The SHARE_CLK and SYNC pins of all load-sharing channels should be bussed together. Connecting the SYNC pins synchronizes the PWM controllers with each other. Bussing the SHARE_CLK pins together allows the phases to start synchronously. Refer to the discussion in the previous Power-Up and Initialization section. The last device to see all start-up conditions satisfied controls the initiation of power sequencing for all phases. Due to the low output impedance of the LTC3882-1 error amplifiers, PolyPhase applications should use the error amplifier of only one phase as the master. The FB pins of each slave channel must be wired to VDD33, and the COMP pins of each slave phase must be connected to the master error amplifier COMP output. This disables the slave error amplifiers and provides a single point of voltage control and loop stabilization for the PolyPhase output rail. For PolyPhase load sharing the LTC3882-1 also incorporates an auxiliary current sharing loop. Referring back to Figure 1, the instantaneous current of each slave phase is sensed by current amplifier CA and compared to the IAVG pin. The IAVG and IAVG_GND pins of each phase are wired together, and a small capacitor (50pF to 200pF) between IAVG and IAVG_GND stores a voltage corresponding to the average master phase output current. The difference in this average and the instantaneous phase current is integrated. The output of integrator S of each slave phase is then 22 Load slope is programmable in the LTC3882-1 via the MFR_VOUT_AVP PMBus command. The inductor current measured at the ISENSE pins is converted to a voltage which is then subtracted from the voltage reference at the positive input of the error amplifier. The final load slope is defined by the inductor current sense element and the bits set in the MFR_VOUT_AVP PMBus command. Setting MFR_VOUT_AVP to a value greater than 0.0% automatically disables output servo mode for that channel. Input Supply Monitoring The input supply voltage is sensed by the LTC3882-1 at the VINSNS pin. Undervoltage, overvoltage, valid on and off levels can be programmed for VIN. Refer to the following PMBus Command Details section for more information on programming the input supply thresholds. In addition, the telemetry ADC monitors the VINSNS voltage relative to GND. Conversion results are returned by the READ_VIN PMBus command. Output Voltage Sensing and Monitoring Both PWM channels allow remote, differential sensing of the load voltage with VSENSE pins. The channel 1 output sense pin VSENSE1- is internally shorted to GND (the exposed pad). The telemetry ADC is fully differential and makes its measurements of the output voltages of channels 0 and 1 at VSENSE0 and VSENSE1, respectively. Conversion results are returned by the READ_VOUT PMBus command. Output Current Sensing and Monitoring Both channels allow differential sensing of the inductor current using either the inductor DCR or a resistor in series with the inductor across the ISENSE pins. When the ISENSE pins for a channel are multiplexed to the differential inputs 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Operation of the LTC3882-1 monitor ADC, they have an input range of approximately 128mV and a noise floor of 7VRMS. Peak-peak noise is approximately 46.5V. The internal ADC anti-aliasing filter and conversion rate produce an average reading of the ISENSE differential voltage. The resulting value is returned by the READ_IOUT PMBus command. Refer to the Applications Information section for details on sensing output current using inductor DCR or discrete resistors. External and Internal Temperature Sense External temperature can best be measured using a remote, diode-connected PNP transistor such as the MMBT3906. The emitter should be connected to a TSNS pin while the base and collector terminals of the PNP transistor must be shorted together and returned directly to the LTC3882-1 GND pin. Two different currents are applied to the diode (nominally 2A and 32A) and the temperature is calculated from a VBE measurement made with the internal 16-bit monitor ADC. The LTC3882-1 also supports direct VBE based external temperature measurements. In this case the diode or diode network is trimmed to a specific voltage at a specific current and temperature. In general this method does not yield as accurate a result as the VBE measurement. Refer to MFR_PWM_MODE_LTC3882-1 in the PMBus Command Details section for additional information on programming the LTC3882-1 for these two external temperature sense configurations. The calculated temperature is returned by the PMBus READ_TEMPERATURE_1 command. Refer to the Applications Information section for details on proper layout of external temperature sense elements and PMBus commands that can be used to improve the accuracy of calculated temperatures. ASEL1, VOUT0_CFG, VOUT1_CFG, FREQ_CFG, and PHAS_CFG. If any of these pins are left open the value stored in the corresponding EEPROM command is used. The resistor configuration pins are only measured during power-up and execution of RESTORE_USER_ALL or MFR_RESET commands. If bit 6 of the MFR_CONFIG_ALL_LTC3882-1 command is set in EEPROM, all resistor inputs except ASELn are ignored. Per the PMBus specification, all pinprogrammed parameters can be overridden at any time by commands from the digital interface. The ASELn pin settings are described in application Table 11. These pins can be used to select the entire LTC3882-1 device address. ASEL0 always programs the bottom four bits of the device address for the LTC3882-1 unless left open. ASEL1 can be used to program the three most-significant bits. Either portion of the address can also be retrieved from the MFR_ADDRESS value in EEPROM. If both pins are left open, the full 7-bit MFR_ADDRESS value stored in EEPROM is used to determine the device address. The LTC3882-1 always responds to 7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS should not be set to either of these values. The VOUTn_CFG pin settings are described in application Table 8. These pins select the output voltages for the related channel. The following parameters are also set as a percentage of the programmed VOUT if resistor configuration pins are used to determined output voltage: * VOUT_OV_FAULT_LIMIT: +10% * VOUT_OV_WARN_LIMIT: +7.5% * VOUT_MAX: +7.5% * VOUT_MARGIN_HIGH: +5% The READ_TEMPERATURE_2 command returns the internal junction temperature of the LTC3882-1 using an on-chip diode with a VBE measurement and calculation. * VOUT_MARGIN_LOW: -5% Resistor Configuration Pins The FREQ_CFG pin settings are described in application Table 9. This pin selects the switching frequency of the internal oscillator and enables the SYNC output if not left open, shorted to GND or ignored by EEPROM setting. Six input pins can be used to configure key operating parameters with selected 1% resistors arranged between VDD25 and GND as a divider to the pin(s). The pins are ASEL0, * VOUT_UV_WARN_LIMIT: -6.5% * VOUT_UV_FAULT_LIMIT: -7% 38821f For more information www.linear.com/LTC3882-1 23 LTC3882-1 Operation The PHAS_CFG pin settings are described in Table 10. This pin selects the phase relationships between the two channels and the selected clock source. Internal EEPROM with CRC The LTC3882-1 contains internal EEPROM to store user configuration settings and fault log information. EEPROM endurance and retention for user space and fault log pages are specified in the Absolute Maximum Ratings and Electrical Characteristics table. The LTC3882-1 EEPROM also contains a manufacturing section that has internal redundancy. The integrity of the entire onboard EEPROM is checked with a CRC calculation each time its data is to be read, such as after a power-on reset or execution of a RESTORE_USER_ ALL command. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC command is set, and the ALERT and RUN pins pulled low (PWM channels off). At that point the device will only respond at special address 0x7C, which is activated only after an invalid CRC has been detected. The chip will also respond at the global addresses 0x5A and 0x5B, but use of these addresses when attempting to recover from a CRC issue is not recommended. All power supply rails associated with either PWM channel of a device reporting an invalid CRC should remain disabled until the issue is resolved. LTC recommends that the EEPROM not be written when die temperature is greater than 85C. If internal die temperature exceeds 130C, all EEPROM operations except RESTORE_USER_ALL and MFR_RESET are disabled. Full EEPROM operation is not re-enabled until die temperature falls below 125C. Refer to the Applications Information section for equations to predict retention degradation due to elevated operating temperatures. See the Applications Information section or contact the factory for details on efficient in-system EEPROM programming, including bulk EEPROM programming, which the LTC3882-1 also supports. 24 Fault Detection A variety of fault and warning detection, reporting and handling mechanisms are provided by the LTC3882-1. Fault or warning detection capabilities include: * Input Under/Overvoltage * Output Under/Overvoltage * Output Overcurrent (Peak and Average) * Internal and External Overtemperature and External Undertemperature * CML Fault (Communication, Memory, or Logic) * External Fault Detection via Bidirectional FAULT Pins Reporting is covered in following sections on status commands (registers) and ALERT pin function. Fault handling mechanisms include hardwired, low-level PWM safety responses that always occur, and higher-level programmable event management. Both types are covered in the following sections. Input Supply Faults Input undervoltage and overvoltage limits are determined from multiplexed monitor ADC conversions. Therefore the input UV/OV response is naturally deglitched by the 100ms typical conversion cycle of the ADC. There is no hardwired low-level PWM response for any input supply fault. Hardwired PWM Response to VOUT Faults VOUT undervoltage (UV) and overvoltage (OV) faults are detected by supervisor comparators. The OV and UV fault limits can be set in three ways: * As a Percentage of VOUT if Using the Resistor Configuration Pins * From Stored EEPROM Values * By PMBus Command The output overvoltage comparator guards against transient overshoots as well as long term overvoltages at the output. When an output OV fault is detected the top MOSFET for that channel is commanded off and the bottom MOSFET is commanded on until the overvoltage condition is cleared 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Operation or for PWM control protocol 0, reverse overcurrent is detected. See IOUT faults below. UV faults and warnings are masked if the channel has been commanded off or until all of the following criteria are achieved. * TON_DELAY Has Expired * TON_RISE Ramp Has Completed * TON_MAX_FAULT_LIMIT Has Been Reached * IOUT_OC_FAULT_LIMIT Has Not Been Reached * TOFF_FALL Is Not in Progress Output UV warnings are determined from multiplexed monitor ADC conversions. The LTC3882-1 has no hardwired PWM response for output UV faults or warnings. Power Good Indication (Master) An LTC3882-1 master phase indicates Power Good on its PGOOD pin and in PMBus commands STATUS_WORD (paged) and MFR_PADS_LTC3882-1 based on programmed UV and OV fault limits. Power Good is indicated on a master phase as long as it is enabled to run and VOUT is between the UV and OV fault limits. If a master channel is off for any reason, its PGOOD pin is driven low and Power Not Good is indicated in the status commands. Power Good Indication (Slave) As long as they are enabled, slave phases indicate Power Good on PGOOD and in PMBus status commands, unless a master error amplifier (EA) fault is detected. An EA fault indicates the bussed COMP voltage appears to be too high. When a slave detects an EA fault, its output is immedidately disabled and OV is indicated (see Figure 2). Any valid higher-level OV fault response and propagation may be set for a slave channel to handle a detected EA fault. If the OV fault response is set to ignore, the slave output is re-enabled when the EA/COMP condition clears. A slave indicates Power Not Good with PMBus status commands during an EA fault, but its PGOOD pin remains high impedance. If a slave phase is off for any other reason, its PGOOD pin is also driven low. Hardwired PWM Response to IOUT Faults The LTC3882-1 measures average IOUT from the voltage across the ISENSE pins, taking into account the sense resistor or DCR value and its associated temperature coefficient. Both are provided by PMBus command or EEPROM values. An output overcurrent (OC) fault condition is detected by a supervisor comparator for each PWM output when the sensed instantaneous current for that channel reaches its maximum allowed value. Refer to the IOUT_OC_ FAULT_LIMIT PMBus command for details. When an OC fault is detected the controller immediately disables the top FET, and the bottom FET is normally commanded on for the remainder of that PWM cycle. If programmed to operate in CCM, the LTC3882-1 also uses the negative of IOUT_OC_FAULT_LIMIT to detect a reverse overcurrent (ROC) fault. When an ROC fault occurs the controller immediately disables both top and bottom FETs, unless PWM output protocol 1 is selected with MFR_PWM_MODE_LTC3882-1. OC and ROC faults are both handled according to the IOUT_OC_FAULT_RESPONSE for that channel. Either hardware response can result in current-limited operation using pulse truncation or skipping. Because the LTC3882-1 uses leading edge modulation, this will cause a shift in average phase toward 0 on the faulted channel and an increase in input ripple current Output OC warnings are determined from multiplexed monitor ADC conversions. The LTC3882-1 has no hardwired PWM response if an output OC warning occurs. Hardwired PWM Response to Temperature Faults An internal temperature sensor measured by the monitor ADC protects against EEPROM and other IC damage. When die temperature rises above 130C, the LTC3882-1 will NACK any EEPROM-related command except RESTORE_USER_ALL and MFR_RESET and issue a CML fault for Invalid/Unsupported Command. Normal EEPROM access is re-enabled when die temperature drops below 125C. Above 160C, the part shuts down all PWM outputs until die temperature is below 150C. Internal temperature fault limits cannot be adjusted. Writing to the EEPROM above a die temperature of 85C is strongly discouraged. 38821f For more information www.linear.com/LTC3882-1 25 LTC3882-1 Operation Refer to the Absolute Maximum Ratings for other important temperature limitations on internal EEPROM use. External temperature sensors may also be monitored by the onboard ADC. There is no hardwired PWM response for sensed external temperature faults or warnings. Hardwired PWM Response to Timing Faults There is no hardwired PWM response to any timing faults. TON_MAX_FAULT_LIMIT is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_LIMIT timer, which has a resolution of 10s, is started after TON_DELAY has been reached and a soft-start sequence is started. If the VOUT_UV_FAULT_LIMIT is not reached or an OC remains within the specified time, fault response is determined by the value of TON_MAX_FAULT_RESPONSE. An internal watchdog detects if SHARE_CLK remains low for more than 64s. The part then actively holds SHARE_CLK low for 120ms, ensuring all devices connected to this shared control observe a minimum RETRY_DELAY event.The LTC3882-1 sets the SHARE_CLK_LOW bit in MFR_COMMON to indicate this fault condition. The RUN pin must be released by any controlling external application circuits for that channel to restart from the latch off state. As the RUN pin for a given channel rises, associated internal fault indications are cleared automatically. The LTC3882-1 can also be programmed to clear faults for both outputs based solely on the RUN voltage of just one channel. See the MFR_CONFIG_ALL_LTC3882-1 command. The CLEAR_FAULTS PMBus command can also be used to clear all fault bits at any time, independent of PWM channel state. Handling of some internally generated faults can be digitally deglitched. See Table 12. External faults propagated into the chip using FAULTn pins are not deglitched. Refer to the following section on FAULT functions. Status Registers and ALERT Masking External Faults There are no hardware-level responses to any external faults propagated into the IC through the FAULTn pins. Fault Handling Higher-level input and output fault event handling (response) can be programmed as described in the following PMBus Command Details section. For most faults, the LTC3882-1 can manage response in one of three ways: ignore, autonomous recovery (hiccup), or latch off. The device takes no additional action beyond previously discussed hardwarelevel responses when programmed to ignore a fault. For autonomous recovery a new soft-start is attempted if the fault condition is not present after the MFR_RETRY_ DELAY interval has elapsed. MFR_RETRY_DELAY can be set from 120ms to 83 seconds in 1ms increments. If the fault persists, the controller will continue to retry with an interval specified by the MFR_RETRY_DELAY command. This avoids damage to external regulator components caused by repetitive, rapid power cycling. 26 No retry is attempted for a latch off fault response. In the latch off state the gate drivers for the external MOSFETs are immediately disabled to stop the transfer of energy to the load as quickly as possible. The output remains disabled until the channel is commanded off and then on, or IC supply power is cycled. Commanding a PWM channel off and on may require software and/or hardware intervention depending on its programmed configuration. Figure 2 summarizes the internal LTC3882-1 status registers accessible by PMBus command. These contain indication of various faults, warnings and other important operating conditions. As shown, the STATUS_BYTE and STATUS_WORD commands also summarize contents of other status registers. Refer to PMBus Command Details for specific information. NONE OF THE ABOVE in STATUS_BYTE indicates that one or more of the bits in the most-significant nibble of STATUS_WORD are also set. In general, any asserted bit in a STATUS_x register also pulls the ALERT pin low. Once set, ALERT will remain low until one of the following occurs. * A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_RESET Command Is Issued * The Related Status Bit Is Written to a One * The Faulted Channel Is Properly Commanded Off and Back On 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Operation STATUS_WORD STATUS_VOUT* 7 6 5 4 3 2 1 0 VOUT_OV Fault VOUT_OV Warning VOUT_UV Warning VOUT_UV Fault VOUT_MAX Warning TON_MAX Fault TOFF_MAX Warning (reads 0) 15 14 13 12 11 10 9 8 VOUT IOUT INPUT MFR_SPECIFIC POWER_GOOD# (reads 0) (reads 0) (reads 0) 7 6 5 4 3 2 1 0 BUSY OFF VOUT_OV IOUT_OC (reads 0) TEMPERATURE CML NONE OF THE ABOVE STATUS_BYTE (PAGED) STATUS_IOUT 7 6 5 4 3 2 1 0 IOUT_OC Fault (reads 0) IOUT_OC Warning (reads 0) (reads 0) (reads 0) (reads 0) (reads 0) MFR_COMMON 7 6 5 4 3 2 1 0 STATUS_TEMPERATURE OT Fault OT Warning (reads 0) UT Fault (reads 0) (reads 0) (reads 0) (reads 0) Chip Not Driving ALERT Low Chip Not Busy Internal Calculations Not Pending Output Not In Transition EEPROM Initialized (reads 0) SHARE_CLK_LOW (reads 0) DESCRIPTION General Fault or Warning Event Dynamic Status Derived from Other Bits MASKABLE GENERATES ALERT BIT CLEARABLE Yes No No Internal Temperature Fault Internal Temperature Warning EEPROM CRC Error Internal PLL Unlocked Fault Log Present (reads 0) VOUT Short Cycled FAULT Low MFR_PADS_LTC3882-1 STATUS_CML Invalid/Unsupported Command Invalid/Unsupported Data Packet Error Check Failed Memory Fault Detected Processor Fault Detected (reads 0) Other Communication Fault Other Memory or Logic Fault 7 6 5 4 3 2 1 0 (PAGED) (PAGED) 7 6 5 4 3 2 1 0 VIN_OV Fault (reads 0) VIN_UV Warning (reads 0) Unit Off for Insuffcient VIN (reads 0) (reads 0) (reads 0) STATUS_MFR_SPECIFIC (PAGED) (PAGED) 7 6 5 4 3 2 1 0 STATUS_INPUT 7 6 5 4 3 2 1 0 Yes No Not Directly Yes No No 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Channel 1 is Slave Channel 0 is Slave (reads 0) (reads 0) Invalid ADC Result(s) SYNC Output Disabled Externally Channel 1 is POWER_GOOD Channel 0 is POWER_GOOD LTC3882-1 Forcing RUN1 Low LTC3882-1 Forcing RUN0 Low RUN1 Pin State RUN0 Pin State LTC3882-1 Forcing FAULT1 Low LTC3882-1 Forcing FAULT0 Low FAULT1 Pin State FAULT0 Pin State *IF THE CHANNEL IS CONFIGURED AS A SLAVE AS INDICATED BY MFR_PADS_LTC3882-1[15:14], VOUT_OV FAULT INDICATES A DETECTED MASTER ERROR AMPLIFIER FAULT (COMP VOLTAGE TOO HIGH). NO OTHER BITS IN STATUS_VOUT ARE ACTIVE ON SLAVE CHANNELS 38821 F02 Figure 2. LTC3882-1 Status Register Summary * The LTC3882-1 Successfully Transmits Its Address During a PMBus Alert Response Address (ARA) * IC Supply Power Is Cycled With some exceptions, the SMBALERT_MASK command can be used to prevent the LTC3882-1 from asserting ALERT for bits in these registers on a bit-by-bit basis. These mask settings are promoted to STATUS_WORD and STATUS_BYTE in the same fashion as the status bits themselves. For example, if ALERT is masked for all bits in Channel 0 STATUS_VOUT, then ALERT is effectively masked for the VOUT bit in STATUS_WORD for PAGE 0. The BUSY bit in STATUS_BYTE also asserts ALERT low and cannot be masked. This bit can be set as a result of interaction between internal operation and PMBus com- For more information www.linear.com/LTC3882-1 38821f 27 LTC3882-1 Operation munication. This fault occurs when a command is received that cannot be safely executed with one or both channels enabled. As discussed in Application Information, BUSY faults can be avoided by polling MFR_COMMON before executing some commands. Status information contained in MFR_COMMON and MFR_PADS_LTC3882-1 can be used to clarify the contents of STATUS_BYTE or STATUS_WORD as shown, but the contents of these registers do not affect the state of the ALERT pin and may not directly influence bits in STATUS_BYTE or STATUS_WORD. FAULT Pin I/O The LTC3882-1 can map various fault indicators to their respective FAULT pin using the MFR_FAULT_PROPAGATE_LTC3882-1 command. Channel-to-channel fault dependencies and communication can be created by connecting FAULT pins together. In the event of an internal fault, one or more of the channels is configured to pull the bussed FAULT pins low. All channels are then configured to shut down when the bussed FAULT pins are pulled low (MFR_FAULT_RESPONSE set to 0xc0). If latch off is the programmed response on the faulted channel, the FAULT pin remains low until one of the following occurs: * A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_RESET Command Is Issued * The Related Status Bit Is Written to a One * The Faulted Channel Is Properly Commanded Off and Back On * IC Supply Power Is Cycled For autonomous group retry, the faulted channel is configured to release the FAULT pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. As noted above, FAULT pins may be configured as inputs to detect faults external to the controller that require an immediate response. External faults propagated into the chip using FAULT pins are not deglitched. Fault Logging The LTC3882-1 has fault logging capability. During normal operation log data is continuously updated in internal RAM. When a fault occurs that disables either PWM controller, recording to internal memory is halted, the fault log information is made available from RAM via the MFR_FAULT_LOG command, and the contents of the RAM log are copied into EEPROM. EEPROM fault logging is allowed above a die temperature of 85C, but 10 years of retention is not guaranteed. When die temperature exceeds 130C EEPROM fault logging is delayed until the temperature drops below 125C. Faults generating a log should be fully cleared before the log is erased to prevent generation of spurious fault logs. Faults propagated into the IC through FAULTn pins do not trigger a fault logging event. When the LTC3882-1 powers up it checks the EEPROM for a valid fault log. If one is found the Valid Fault Log bit in the STATUS_MFR_SPECIFIC PMBus command is set. Additional fault logging will be disabled until the LTC3882-1 receives a CLEAR_FAULTS command. If the Memory Fault Detected bit is also set in STATUS_CML, then the stored fault log is partial. Data in one or more event records may be incomplete or incorrect and MFR_CLEAR_FAULT_LOG should also be commanded after all faults are cleared in order to fully enable additional logging functions. The MFR_FAULT_LOG command uses a block read protocol with a fixed length of 147 bytes. The LTC3882-1 returns a block byte count of zero if a fault log is not present. Contents of a fault log are shown in Table 1 through Table 4. Refer to Table 6 for an explanation of data formats. Each event record represents one complete conversion cycle through all multiplexed monitor ADC inputs and related status. The six most recent event records are maintained in internal memory in reverse chronological order. When a fault log is created the present ADC input cycle is completed and the ADC input being converted at the time of the fault is noted in the log header record. Refer to the MFR_FAULT_PROPAGATE command for additional details. 28 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Operation Table 1. LTC3882-1 Fault Log Contents STARTING BYTE ENDING BYTE COMMENTS Header Information 0 26 See Table 2. Fault Event Record 27 46 Fault may have occurred anywhere during this event record. See byte 4 of Table 2 and all of Table 3 and Table 4. Event Record N-1 47 66 Last complete cyclical data read before the fault was detected. Event Record N-2 67 86 Older data records... Event Record N-3 87 106 Event Record N-4 107 126 Event Record N-5 127 146 RECORD TYPE Oldest recorded data. Table 2. Fault Log Header Information RECORD BITS FORMAT Fault Log Preface [7:0] ASC [7:0] [15:8] MFR_REAL_TIME MFR_VOUT_PEAK (PAGE 0) Reg Returns LTxx beginning at byte 0 if a partial or complete fault log exists. Word xx is a factory identifier that may vary part to part. 2 3 Reg 4 Refer to Table 3. [7:0] Reg 5 48 bit share-clock counter value when fault occurred (200s resolution). [15:8] 6 [23:16] 7 [31:24] 8 [39:32] 9 [47:40] 10 [15:8] L16 [15:8] MFR_IOUT_PEAK (PAGE 0) [15:8] MFR_IOUT_PEAK (PAGE 1) [15:8] MFR_VIN_PEAK [15:8] L16 L11 [15:8] L11 Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS command. 17 Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS command. 19 Peak READ_VIN since last power-on or CLEAR_PEAKS command. 21 External temperature sensor 0 during last event. 22 L11 [7:0] [7:0] 15 20 [7:0] READ_TEMPERATURE2 Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS command. 18 L11 [7:0] [15:8] 13 16 L11 [7:0] READ_TEMPERATURE1 (PAGE 1) Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS command. 14 [7:0] [15:8] 11 12 [7:0] READ_TEMPERATURE1 (PAGE 0) DETAILS [7:0] [7:0] MFR_VOUT_PEAK (PAGE 1) 0 1 [7:0] Fault Source BLOCK BYTE COUNT 23 External temperature sensor 1 during last event. 24 L11 25 Internal temperature sensor during last event. 26 38821f For more information www.linear.com/LTC3882-1 29 LTC3882-1 Operation Table 3. Fault Source Values FAULT SOURCE VALUE CAUSE OF FAULT LOG 0x00 TON_MAX 0x01 VOUT_OV 0x02 VOUT_UV 0x03 IOUT_OC 0x05 Over temperature 0x06 Under temperature CHANNEL 0 0x07 VIN_OV 0x0A Internal temperature 0x10 TON_MAX 0x11 VOUT_OV 0x12 VOUT_UV 0x13 IOUT_OC 0x15 Over temperature 0x16 Under temperature 0x17 VIN_OV 0x1A Internal temperature 0xFF MFR_FAULT_LOG_STORE 1 Table 4. Fault Log Event Record DATA BITS FORMAT RECORD BYTE INDEX READ_VOUT (PAGE 0) [15:8] L16 0 [7:0] READ_VOUT (PAGE 1) [15:8] READ_IOUT (PAGE 0) [15:8] READ_IOUT (PAGE 1) [15:8] 1 L16 2 L11 4 L11 6 [7:0] 3 [7:0] 5 [7:0] READ_VIN [15:8] 7 L11 [7:0] (Not used) [15:8] STATUS_VOUT (PAGE 0) [7:0] 8 9 L11 10 Reg 12 [7:0] 11 STATUS_VOUT (PAGE 1) [7:0] Reg 13 STATUS_WORD (PAGE 0) [15:8] Reg 14 [7:0] STATUS_WORD (PAGE 1) [15:8] 15 Reg [7:0] 16 17 STATUS_MFR_SPECIFIC (PAGE 0) [7:0] Reg 18 STATUS_MFR_SPECIFIC (PAGE 1) [7:0] Reg 19 30 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Operation Factory Default Operation The LTC3882-1 ships from the factory with a default configuration stored in its non-volatile memory, unless custom programming has been requested. These command values are loaded into volatile RAM when the chip is initialized. Prior to receiving any PMBus commands, a stock LTC3882-1 will operate in the factory default mode. If a STORE_USER_ ALL command is executed, the contents of the non-volatile memory are replaced with active command values from internal RAM, and that will permanently overwrite the factory defaults. Table 5 summarizes the default factory operation settings of the LTC3882-1 if all resistor configuration pins are left open. These defaults allow parameters listed in bold text in the table to be overridden with configuration resistor programming. Warning limits are given in Table 5 because exceeding them will cause the ALERT pin to be asserted even if the PMBus interface is not being utilized. Table 5. Factory Default Operation Summary PARAMETER* DEFAULT SETTING UNITS PMBus Address All writes enabled to Channel 0 at address 0x4F (no PEC). - Operation OPERATION enabled with RUN pin control and soft-off. - Input Voltage OFF Threshold 6.0 V Input Voltage UV Warning Limit 6.3 V Input Voltage ON Threshold 6.5 V Input Voltage OV Fault Limit 15.5 V Input Voltage OV Fault Response Latch off. Soft-Start Time 8 (with no delay). ms - Maximum Start-Up Time (TMAX) 10 ms TMAX Fault Response Retry every 350ms. - Output Voltage UV Fault/Warning Limits 0.900/0.925 V Output Voltage UV Fault Response Retry every 350ms. - Output Voltage 1.000 V Active Voltage Positioning Disabled. - Output Voltage OV Warning/Fault Limits 1.075/1.100 V Output Voltage OV Fault Response Retry every 350ms. - Shut Down 8ms soft-off. - Output Current Sense Element 0.63m with 3930ppm/C TC. - Output Current OC Warning/Fault Limits 20/29.75 A Output Current OC Fault Response Ignore - PWM Switching Mode Continuous inductor current only. - PWM Control Protocol Three-State PWM. - PWM Switching Frequency 500 Channel 0/1 Phase 0/180 kHz Degrees Internal Overtemperature Warning/Fault Limits 130/160 C Internal Overtemperature Responses Warning: EEPROM disabled; Fault: PWM disabled. - External Undertemperature Fault Limit -40 C External Undertemperature Fault Response Retry every 350ms. - External Overtemperature Warning/Fault Limits 85/100 C External Overtemperature Fault Response Retry every 350ms. - FAULT Asserts low for the following faults: VOUT UV or OV, VIN OV, external or internal OT, external UT, TON_MAX, or output short cycle. - ALERT Masking ALERTs are masked for loss of PLL lock and external FAULT inputs. - *bold entries can be changed with external configuration resistors 38821f For more information www.linear.com/LTC3882-1 31 LTC3882-1 Operation Serial Interface * Read Byte The LTC3882-1 has a PMBus compliant serial interface that can operate at any frequency between 10kHz and 400kHz. The LTC3882-1 is a bus slave device that communicates bidirectionally with a host (master) using standard PMBus protocols. The Timing Diagram found earlier in this document, along with related Electrical Characteristics table entries, define the timing relationships of the SDA and SCL bus signals. SDA and SCL must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. * Read Word PMBus, an incremental extension of the SMBus standard, offers more robust operation than a 2-wire I2C interface. In addition to adding a protocol layer to improve interoperability and facilitate reuse, PMBus supports bus timeout recovery for system reliability, optional packet error checking to ensure data integrity, and peripheral hardware alerts for system fault management. In general, a programmable device capable of functioning as an I2C bus master can be configured for PMBus management with little or no change to hardware. However, not all I2C controllers support repeat start (restart) required for PMBus reads. For a description of the minor extensions and exceptions PMBus makes to the SMBus standard, refer to PMBus Specification Part I Revision 1.2 Paragraph 5 on Transport. For a description of the differences between SMBus and I2C, refer to System Management Bus (SMBus) Specification Version 2.0 Appendix B on Differences Between SMBus and I2C. The user is encouraged to reference Part I of the latest PMBus Power System Management Protocol Specification to understand how to interface the LTC3882-1 to a PMBus system. This specification can be found at http:// www.pmbus.org/specs.html. * Block Read * Block Write - Block Read Process Call * Alert Response Address The LTC3882-1 does not require PEC for Quick Command under any circumstances. The LTC3882-1 also supports group command protocol (GCP) as required by PMBus specification Part I, section 5.2.3. GCP is used to send commands to more than one PMBus device in one continuous transmission. It should not be used with commands that require the receiving device to respond with data, such as a STATUS_BYTE command. Refer to Part I of the PMBus specification for additional details on using GCP. All LTC3882-1 message transmission types allow for packet error checking. The later section on Serial Communication Errors provides more detail on packet error checking. Figure 4 to Figure 20 illustrate these protocols. Figure 3 provides a key to the protocol diagrams. Not all protocol elements will be present in every data packet. For instance, not all packets are required to include the packet error code. A number shown above a field in these diagrams indicates the number of bits in that field. All data transfers are initiated by the present bus master regardless of how many times data direction flow may change during the subsequent transmission. The LTC3882-1 never functions as a bus master. This device includes handshaking features to ensure robust system communication. Please refer to the PMBus Communication and Command Processing section in Applications Information for more details. Serial Bus Addressing The LTC3882-1 uses the following standard serial interface protocols defined in the SMBus and PMBus specifications: The LTC3882-1 supports four types of serial bus addressing: * Quick Command * Global Bus Addressing * Send Byte * Power Rail Addressing * Write Byte * Individual Device Addressing * Write Word * Page+ Channel Addressing 32 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Operation Global addressing provides a means for the bus master to communicate with all LTC3882-1 devices on the bus simultaneously. The LTC3882-1 global addresses of 0x5A and 0x5B cannot be changed or disabled. Commands sent to address 0x5A are applied to both channels, as if the PAGE command were set to 0xFF. Global address 0x5B is paged, allowing channel-specific control of all LTC3882-1 devices on the bus. Other LTC device types may respond at one or both of these global addresses. Reading from global addresses is strongly discouraged. PolyPhase rail. Different voltage rails should not attempt to share a rail address. Reading from rail addresses is also strongly discouraged. Device addressing is the most common means used by a bus master to communicate with an LTC3882-1. The value of the device address is set by the combination of ASEL pin programming and the MFR_ADDRESS command. Refer to the previous section on Resistor Configuration Pins for details. Individual channel addressing allows the bus master to communicate directly with a specific LTC3882-1 PWM channel without first using a PAGE command. Refer to the PAGE_PLUS commands for additional details. Rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (PolyPhase). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ADDRESS command, allowing for any logical grouping of channels that might be required for reliable system control. Rail addresses should be unique for each single-phase or Use of any of the four types of addressing requires careful planning to avoid address-related bus conflicts. Communication to LTC3882-1 devices at global and rail addresses should be limited to command write operations. S START CONDITION Sr REPEATED START CONDITION Rd READ (BIT VALUE OF 1) Wr WRITE (BIT VALUE OF 0) A NA ACKNOWLEDGE (BIT SHOULD BE 0), OR NOT ACKNOWLEDGE (BIT SHOULD BE 1) P STOP CONDITION PEC PACKET ERROR CODE MASTER TO SLAVE SLAVE TO MASTER ... CONTINUATION OF PROTOCOL 38821 F03 Figure 3. PMBus Packet Protocol Diagram Element Key 1 7 S 1 1 SLAVE ADDRESS Rd/Wr A 1 P 38821 F04 Figure 4. Quick Command Protocol 1 S 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 7 1 1 8 P 38821 F05 Figure 5. Send Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 1 PEC A P 38821 F06 Figure 6. Send Byte Protocol with PEC 38821f For more information www.linear.com/LTC3882-1 33 LTC3882-1 Operation 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 1 DATA BYTE A P 38821 F07 Figure 7. Write Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE A PEC A P 38821 F08 Figure 8. Write Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE LOW A DATA BYTE HIGH A P 38821 F09 Figure 9. Write Word Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 8 1 1 DATA BYTE LOW A DATA BYTE HIGH A PEC A P 38821 F10 Figure 10. Write Word Protocol with PEC 1 S 7 1 1 8 1 1 7 1 1 8 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 1 DATA BYTE 1 NA P 38821 F11 Figure 11. Read Byte Protocol 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 8 1 1 DATA BYTE A PEC A P 38821 F12 Figure 12. Read Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 1 7 1 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 8 1 1 DATA BYTE HIGH NA P 38821 F13 Figure 13. Read Word Protocol 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 8 1 DATA BYTE HIGH A 8 1 1 PEC A P 38821 F14 Figure 14. Read Word Protocol with PEC 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 8 DATA BYTE 1 A DATA BYTE 2 1 ... A ... 8 DATA BYTE N 8 1 BYTE COUNT = N A 1 ... 1 NA P 38821 F15 Figure 15. Block Read Protocol 34 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Operation 1 S 7 1 1 8 1 1 7 1 1 8 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 8 DATA BYTE 1 A DATA BYTE 2 1 ... A ... 1 BYTE COUNT = N A 8 1 8 DATA BYTE N A PEC 1 ... 1 NA P 38821 F16 Figure 16. Block Read Protocol with PEC 1 S 7 1 1 8 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A 8 1 DATA BYTE 2 1 7 1 8 A ... 1 Sr SLAVE ADDRESS Rd A 1 8 A ... ... 1 BYTE COUNT = N A 8 DATA BYTE 2 1 A A ... DATA BYTE M 8 8 DATA BYTE 1 8 1 DATA BYTE 1 A 1 DATA BYTE N ... 1 NA P 38821 F17 Figure 17. Block Write - Block Read Process Call 1 S 7 1 1 8 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A 8 DATA BYTE 2 1 7 1 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE 2 1 ... A ... A ... 8 1 A ... 1 DATA BYTE M 8 8 DATA BYTE 1 A ... 1 BYTE COUNT = N A 8 DATA BYTE 1 8 1 8 DATA BYTE N A PEC A 1 ... 1 NA P 38821 F18 Figure 18. Block Write - Block Read Process Call with PEC 1 7 1 1 8 1 1 S ALERT RESPONSE Rd A DEVICE ADDRESS NA P ADDRESS 38821 F19 Figure 19. Alert Response Address Protocol 1 7 1 1 8 1 S ALERT RESPONSE Rd A DEVICE ADDRESS A ADDRESS 8 PEC 1 1 NA P 38821 F20 Figure 20. Alert Response Address Protocol with PEC 38821f For more information www.linear.com/LTC3882-1 35 LTC3882-1 Operation Serial Bus Timeout Serial Communication Errors The LTC3882-1 implements a timeout feature to avoid hanging the serial interface. The data packet timer begins running at the first START event before the SLAVE ADDRESS write byte and ends with the STOP bit. Packet transmission must be completed before the timer expires, or the LTC3882-1 will tri-state the bus and ignore all message data. The data packet includes the SLAVE ADDRESS byte, COMMAND CODE byte, repeated START and SLAVE ADDRESS byte (if a read operation), all ACKNOWLEDGE and flow control bits (R/W) and all data bytes. The LTC3882-1 supports the optional PMBus packet error checking protocol. This protocol appends a packet error code (PEC) to the end of applicable message transfers to improve communication reliability. The PEC is a CRC-8 error-checking byte calculated by the bus device sending the last data byte. Refer to SMBus specification 1.2 or higher for additional implementation details. All LTC3882-1 read operations will return a valid PEC if the bus master requests it. If bit 2 in the MFR_CONFIG_ALL_LTC3882-1 command is set, the IC will not act in response to a bus write operation unless a valid PEC is also received from the host. The packet timer is typically set to 30ms. If bit 3 of MFR_ CONFIG_ALL_LTC3882-1 is set, this period is extended to 255ms. The LTC3882-1 automatically allows a packet transmission time of 255ms for MFR_FAULT_LOG block reads regardless of the setting of this bit. In no circumstances will the timeout period be less than the tTIMEOUT specification (25ms minimum). The LTC3882-1 supports the full PMBus frequency range of 10kHz to 400kHz. 36 PEC errors on command writes, attempts to access unsupported commands, or writing invalid data to supported commands all cause the LTC3882-1 to generate a CML fault. The CML bit is then set in the STATUS_BYTE and STATUS_WORD commands, and the appropriate bit is set in the STATUS_CML command. 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus Command Summary PMBus Commands Table 7 lists supported PMBus commands and manufacturer specific commands. Additional information about these commands can be found in Revision 1.2 of Part II of the PMBus Power System Management Protocol Specification that can be found at http://www.pmbus.org/specs.html. Users are encouraged to reference that manual. Exceptions or manufacturer-specific implementations are detailed in the tables below. All standard PMBus commands from 0x00 through 0xCF not listed in this table are implicitly not supported by the LTC3882-1. All commands from 0xD0 through 0xFF not listed in this table are implicitly reserved by the manufacturer. The LTC3882-1 may execute additional commands not listed in this table, and these can change without notice. Reading these unlisted commands is harmless to the operation of the IC. Writes to any unsupported or reserved command should be avoided, as they may result in a CML fault and/or undesired operation of the part. If PMBus commands are received faster than they are being processed, the part may become too busy to handle new commands. In these cases the LTC3882-1 follows the protocols defined in the PMBus Specification V1.2, Part II, Section 10.8.7, to communicate that it is busy. This device includes handshaking features to eliminate busy responses, simplify error handling software and ensure robust communication and system behavior. Please refer to PMBus Communication and Command Processing in the Applications Information section for further details. LTC has made an effort to establish PMBus command compatibility and functional uniformity among its family of parts. However, differences may occur due to specific product requirements. Compatibility of PMBus commands among any ICs should not be assumed based simply on command name. Always refer to the manufacturer's data sheet of each device for a complete definition of a command function. Data Formats PMBus supports specific floating point number formats and allows for a wide range of other data formats. Table 6 describes the data formats used by the LTC3882-1. Abbreviations of these formats appear throughout this document. Table 6. Abbreviations of Supported Data Formats PMBus TERMINOLOGY SPECIFICATION LTC REFERENCE TERMINOLOGY DEFINITION L11 Linear Part II 7.1 Linear_5s_11s L16 Linear VOUT_MODE Part II 8.2 Linear_16u CF DIRECT Part II 7.2 varies Reg register bits Part II 10.3 Reg ASC text characters Part II 22.2.1 ASCII Floating point 16-bit data: value = Y * 2N, where N = b[15:11] and Y = b[10:0], both two's compliment binary integers. EXAMPLE b[15:0] = 0x9807 = 10011_000_0000_0111 value = 7 * 2-13 = 854E-6 Floating point 16-bit data: value = Y * 2-12, b[15:0] = 0x4C00 = 0100_1100_0000_0000 where Y = b[15:0], an unsigned integer. value = 19456 * 2-12 = 4.75 16-bit data with a custom format defined in the detailed PMBus command description. Often an unsigned or two's compliment integer. Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command. command description. ISO/IEC 8859-1 [A05] LTC (0x4C5443) 38821f For more information www.linear.com/LTC3882-1 37 LTC3882-1 PMBus Command Summary Table 7. PMBus Command Summary COMMAND NAME CMD CODE DESCRIPTION PAGE 0x00 Channel (page) presently selected for any paged command. R/W Byte N Reg OPERATION 0x01 On, off and margin control. R/W Byte Y Reg ON_OFF_CONFIG 0x02 RUN pin and PMBus on/off command configuration. R/W Byte Y Reg CLEAR_FAULTS 0x03 Clear all set fault bits. Send Byte N 92 PAGE_PLUS_WRITE 0x05 Write a command directly to a specified page. W Block N 70 PAGE_PLUS_READ 0x06 Read a command directly from a specified page. Block R/W Process N 71 WRITE_PROTECT 0x10 Protect the device against unintended PMBus modifications. R/W Byte N STORE_USER_ALL 0x15 Store entire operating memory in EEPROM. Send Byte N 103 RESTORE_USER_ALL 0x16 Restore entire operating memory from EEPROM. Send Byte N 103 CAPABILITY 0x19 Summary of supported optional PMBus features. R Byte N Reg SMBALERT_MASK 0x1B Mask ALERT activity Block R/W Y Reg VOUT_MODE 0x20 Voltage-related format (Linear) and exponent. R Byte Y Reg VOUT_COMMAND 0x21 Nominal VOUT value. R/W Word Y L16 V VOUT_MAX 0x24 Maximum VOUT that can be set by any command, including margin. R/W Word Y L16 VOUT_MARGIN_HIGH 0x25 VOUT at high margin, must be greater than VOUT_COMMAND. R/W Word Y VOUT_MARGIN_LOW 0x26 VOUT at low margin, must be less than VOUT_COMMAND. R/W Word VOUT_TRANSITION_RATE 0x27 VOUT slew rate for programmed output changes. FREQUENCY_SWITCH 0x33 VIN_ON TYPE DATA PAGED FORMAT DEFAULT VALUE SEE PAGE 0x00 70 l 0x80 74 l 0x1E 73 UNITS NVM Reg l 0x00 71 0xB0 72 see CMD details 100 0x14 2-12 80 l 1.0V 0x1000 80 V l 5.5V 0x5800 81 L16 V l 1.05V 0x10CD 81 Y L16 V l 0.95V 0x0F33 81 R/W Word Y L11 V/ms l 0.25 0xAA00 85 PWM frequency control. R/W Word N L11 kHz l 500kHz 0xFBE8 75 0x35 Minimum input voltage to begin power conversion. R/W Word N L11 V l 6.5V 0xCB40 79 VIN_OFF 0x36 Decreasing input voltage at which power R/W Word conversion stops. N L11 V l 6.0V 0xCB00 79 IOUT_CAL_GAIN 0x38 Ratio of ISENSE voltage to sensed current. R/W Word Y L11 m l 0.63m 0xB285 83 VOUT_OV_FAULT_LIMIT 0x40 VOUT overvoltage fault limit. R/W Word Y L16 V l 1.1V 0x119A 81 VOUT_OV_FAULT_RESPONSE 0x41 VOUT overvoltage fault response. R/W Byte Y Reg VOUT_OV_WARN_LIMIT 0x42 VOUT overvoltage warning limit. R/W Word Y L16 38 l V l 0xB8 96 l 1.075V 0x1133 82 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus Command Summary Table 7. PMBus Command Summary COMMAND NAME CMD CODE DESCRIPTION DEFAULT VALUE SEE PAGE VOUT_UV_WARN_LIMIT 0x43 VOUT undervoltage warning limit. R/W Word Y L16 V l 0.925V 0x0ECD 82 VOUT_UV_FAULT_LIMIT 0x44 VOUT undervoltage fault limit. R/W Word Y L16 V l 0.9V 0x0E66 82 VOUT_UV_FAULT_RESPONSE 0x45 VOUT undervoltage fault response. R/W Byte Y Reg l 0xB8 96 IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 l 29.75A 0xDBB8 83 IOUT_OC_FAULT_RESPONSE 0x47 Output overcurrent fault response. R/W Byte Y Reg l 0x00 97 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A l 20.0A 0xDA80 83 OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C l 100.0C 0xEB20 86 OT_FAULT_RESPONSE 0x50 External overtemperature fault response. R/W Byte Y Reg l 0xB8 98 C l OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 85.0C 0xEAA8 86 UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C l -40.0C 0xE580 87 UT_FAULT_RESPONSE 0x54 External undertemperature fault response. R/W Byte Y Reg l 0xB8 98 VIN_OV_FAULT_LIMIT 0x55 VIN overvoltage fault limit. R/W Word N L11 l 15.5V 0xD3E0 79 VIN_OV_FAULT_RESPONSE 0x56 VIN overvoltage fault response. R/W Byte Y Reg l 0x80 95 VIN_UV_WARN_LIMIT 0x58 VIN undervoltage warning limit. R/W Word N L11 V l 6.3V 0xCB26 79 TON_DELAY 0x60 Delay from RUN pin or OPERATION ON command to TON_RISE ramp start. R/W Word Y L11 ms l 0.0ms 0x8000 84 TON_RISE 0x61 Time for VOUT to rise from 0.0V to VOUT_COMMAND after TON_DELAY. R/W Word Y L11 ms l 8.0ms 0xD200 84 TON_MAX_FAULT_LIMIT 0x62 Maximum time for VOUT to rise above VOUT_UV_FAULT_LIMIT after TON_DELAY. R/W Word Y L11 ms l 10.0ms 0xD280 85 TON_MAX_FAULT_RESPONSE 0x63 Fault response when TON_MAX_FAULT_ LIMIT is exceeded. R/W Byte Y Reg l 0xB8 99 TOFF_DELAY 0x64 Delay from RUN pin or OPERATION OFF command to TOFF_FALL ramp start. R/W Word Y L11 ms l 0.0ms 0x8000 85 TOFF_FALL 0x65 Time for VOUT to fall to 0.0V from VOUT_COMMAND after TOFF_DELAY. R/W Word Y L11 ms l 8.0ms 0xD200 85 TOFF_MAX_WARN_ LIMIT 0x66 Maximum time for VOUT to decay below 12.5% of VOUT_COMMAND after TOFF_FALL completes. R/W Word Y L11 ms l 150ms 0xF258 85 STATUS_BYTE 0x78 One-byte channel status summary. R/W Byte Y Reg 87 STATUS_WORD 0x79 Two-byte channel status summary. R/W Word Y Reg 88 STATUS_VOUT 0x7A VOUT fault and warning status. R/W Byte Y Reg 88 STATUS_IOUT 0x7B IOUT fault and warning status. R/W Byte Y Reg 89 STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg 89 TYPE DATA PAGED FORMAT UNITS NVM A V 38821f For more information www.linear.com/LTC3882-1 39 LTC3882-1 PMBus Command Summary Table 7. PMBus Command Summary COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE SEE PAGE STATUS_TEMPERATURE 0x7D External temperature fault and warning status. R/W Byte Y Reg 89 STATUS_CML 0x7E Communication, memory and logic fault and warning status. R/W Byte N Reg 90 STATUS_MFR_ SPECIFIC 0x80 LTC3882-1-specific status. R/W Byte Y Reg 90 READ_VIN 0x88 Measured VIN. R Word N L11 READ_VOUT 0x8B Measured VOUT. R Word Y READ_IOUT R Word Y READ_TEMPERATURE_1 0x8C Measured IOUT. 0x8D Measured external temperature. R Word Y READ_TEMPERATURE_2 0x8E Measured internal temperature. R Word N READ_DUTY_CYCLE 0x94 Measured commanded PWM duty cycle. R Word READ_FREQUENCY 0x95 Measured PWM input clock frequency. READ_POUT 0x96 Calculated output power. PMBUS_REVISION 0x98 MFR_ID 0x99 MFR_MODEL MFR_SERIAL V 92 L16 V 93 L11 A 93 L11 C 94 L11 C 94 Y L11 % 94 R Word Y L11 kHz 94 R Word Y L11 W 93 Supported PMBus version. R Byte N Reg 0x22 V1.2 72 Manufacturer identification. R String N ASC LTC 104 0x9A LTC model number. R String N ASC LTC3882-1 104 0x9E R Block N ASC R Word Y L16 Device serial number. 104 LTC3882-1 Custom Commands MFR_VOUT_MAX 0xA5 Maximum value of any VOUT related command. V 5.6V 0x599A 80 USER_DATA_00 0xB0 EEPROM word reserved for LTpowerPlay. R/W Word N Reg l 103 USER_DATA_01 0xB1 EEPROM word reserved for LTpowerPlay. R/W Word Y Reg l 103 USER_DATA_02 0xB2 EEPROM word reserved for OEM use. R/W Word N Reg l USER_DATA_03 0xB3 EEPROM word available for general data storage. R/W Word Y Reg l 0x0000 103 USER_DATA_04 0xB4 EEPROM word available for general data storage. R/W Word N Reg l 0x0000 103 103 MFR_EE_UNLOCK 0xBD (contact the factory) 103 MFR_EE_ERASE 0xBE (contact the factory) 103 MFR_EE_DATA 0xBF MFR_CHAN_CONFIG_ LTC3882-1 0xD0 LTC3882-1 channel-specific configuration. (contact the factory) 103 R/W Byte Y Reg l 0x1D 77 R/W Byte N Reg l 0x01 73 MFR_FAULT_PROPAGATE_ LTC3882-1 0xD2 Configure LTC3882-1 status propagation R/W Word via FAULTn pins. Y Reg l 0x6993 101 MFR_VOUT_AVP 0xD3 Specify VOUT load line. R/W Word Y L11 l 0% 0x8000 81 MFR_PWM_MODE_LTC3882-1 0xD4 LTC3882-1 channel-specific PWM mode control. R/W Byte Y Reg l 0xC8 78 MFR_FAULT_RESPONSE 0xD5 PWM response when FAULTn pin is low. R/W Byte Y Reg l 0xC0 101 MFR_CONFIG_ALL_LTC3882-1 0xD1 LTC3882-1 device-level configuration. 40 % 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus Command Summary Table 7. PMBus Command Summary COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT MFR_OT_FAULT_RESPONSE 0xD6 Internal overtemperature fault response. R Byte N Reg MFR_IOUT_PEAK 0xD7 Maximum IOUT measurement since last MFR_CLEAR_PEAKS. R Word Y L11 A MFR_RETRY_DELAY 0xDB Minimum time before retry after a fault. R/W Word Y L11 ms l 350ms 0xFABC 99 MFR_RESTART_DELAY 0xDC Minimum time RUN pin is held low by the LTC3882-1. R/W Word Y L11 ms l 500ms 0xFBE8 84 MFR_VOUT_PEAK 0xDD Maximum VOUT measurement since last MFR_CLEAR_PEAKS. R Word Y L16 V 93 MFR_VIN_PEAK 0xDE Maximum VIN measurement since last MFR_CLEAR_PEAKS. R Word N L11 V 93 MFR_TEMPERATURE_1_PEAK 0xDF Maximum external temperature measurement since last MFR_CLEAR_ PEAKS. R Word Y L11 C 94 MFR_CLEAR_PEAKS 0xE3 Clear all peak values. Send Byte N MFR_PADS_LTC3882-1 0xE5 State of selected LTC3882-1 pads. R Word N Reg MFR_ADDRESS 0xE6 Specify right-justified 7-bit device address. R/W Byte N Reg MFR_FAULT_LOG_STORE 0xEA Force transfer of fault log from operating Send Byte memory to EEPROM. N 103 MFR_FAULT_LOG_CLEAR 0xEC Clear existing EEPROM fault log. Send Byte N 102 MFR_FAULT_LOG 0xEE Read fault log data. R Block N Reg MFR_COMMON 0xEF LTC-generic device status reporting. Reg MFR_COMPARE_USER_ALL 0xF0 Compare operating memory with EEPROM contents. MFR_TEMPERATURE_2_PEAK 0xF4 Maximum internal temperature measurement since last MFR_CLEAR_PEAKS. MFR_PWM_CONFIG_LTC3882-1 0xF5 MFR_IOUT_CAL_GAIN_TC UNITS NVM DEFAULT VALUE SEE PAGE 0xC0 98 93 94 R Byte N Send Byte N R Word N L11 LTC3882-1 PWM configuration common to both channels. R/W Byte N Reg 0xF6 Output current sense element temperature coefficient. R/W Word Y CF MFR_TEMP_1_GAIN 0xF8 Slope for external temperature calculations. R/W Word Y CF MFR_TEMP_1_OFFSET 0xF9 Offset addend for external temperature calculations. R/W Word Y L11 MFR_RAIL_ADDRESS 0xFA Specify unique right-justified 7-bit address for channels comprising a PolyPhase output. R/W Byte Y Reg MFR_RESET 0xFD Force full reset without removing power. Send Byte N 91 l 0x4F 72 102 91 103 C ppm/C C or V 94 l 0x14 76 l 3900ppm/C 0x0F3C 83 l 1.0 0x4000 86 l 0.0 0x8000 86 l 0x80 72 74 NVM l Indicates a command value stored to internal EEPROM using STORE_USER_ALL or restored to RAM from internal EEPROM at power-up or execution of RESTORE_USER_ALL or MFR_RESET. 38821f For more information www.linear.com/LTC3882-1 41 LTC3882-1 Applications Information Efficiency Considerations Normally, one of the primary goals of any LTC3882-1 application will be to obtain the highest practical conversion efficiency. The efficiency of a switching regulator is equal to the output power divided by the input power. It is often useful to analyze individual losses to determine what is limiting the efficiency and to ascertain which change would produce the most improvement. Balancing or limiting these individual losses plays a dominant role in the component selection process outlined over the next few sections. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, et al, are the individual losses as a percentage of input power: 100 * PLn /PIN. Although all dissipative elements in the system produce losses, four main sources usually account for most of the losses in LTC3882-1 applications: IC supply current, I2R losses, topside power MOSFET transition losses and total gate drive current. 1. The LTC3882-1 IC supply current is a DC value given in the Electrical Characteristics table. The absolute loss created by the IC itself is approximately this current times the VCC supply voltage. IC supply current typically results in a small loss (<0.1%). 2. I2R losses occur mainly in the DC resistances of the MOSFET, inductor, PCB routing, and input and output capacitor ESR. Since each MOSFET is only on for part of the cycle, its on-resistance is effectively multiplied by the percentage of the cycle it is on. Therefore the bottom MOSFET should have a much lower on-resistance RDS(ON) than the top MOSFET in high step-down ratio applications. It is crucial that careful attention is paid to the layout of the power path on the PCB to minimize its resistance. In a 2-phase 1.2V system, 1m of PCB resistance at the output costs 5% in efficiency with the output running at 60A. 3. Transition losses apply only to the topside MOSFET and become significant when operating at high input voltages (typically above 12V). This loss can be minimized by 42 choosing a driver with very low drive resistance and a MOSFET with low gate charge QG, gate resistance RG and Miller capacitance CMILLER. Absolute transition loss can be estimated by: PTRANS = (1.7) * VIN2 * IOUT * CMILLER * fPWM 4. Gate drive current is equal to the sum of the top and bottom MOSFET gate charges multiplied by the frequency of operation. These charges are based on the gate voltage applied by the FET driver and can be determined from manufacturer curves like the one shown in Figure 21. Many driver ICs employ asymmetrical gate voltages for top and bottom FETs. Other sources of loss include body or Schottky diode conduction during the driver dependent non-overlap time and inductor core losses. These latter categories generally account for less than 2% total additional loss. PWM Frequency and Inductor Selection The selection of the PWM switching frequency is a trade-off between efficiency, transient response and component size. High frequency operation reduces the size of the inductor and output capacitor as well as increasing the maximum practical control loop bandwidth. However, efficiency is generally lower due to increased transition and switching losses. The inductor value is related to the switching frequency fPWM and step-down ratio. It should be selected to meet choke ripple current requirements. The inductor value can be calculated using the following equation: VOUT VOUT L= * 1- VIN f PWM * IL Allowing a larger value of choke ripple current (IL) leads to smaller L, but results in greater core loss and higher output voltage ripple for a given output capacitance and/ or ESR. A reasonable starting point for setting the ripple current is 30% of the maximum output current. The inductor saturation current rating needs to be higher than the peak inductor current during transient conditions. If IOUT is the maximum rated load current, then the maximum transient current IMAX would normally be chosen to be some factor greater than IOUT (e.g., 1.6 * IOUT). 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information The minimum saturation current rating should be chosen to allow margin due to manufacturing and temperature variation in the sense resistor or inductor DCR. A reasonable ISAT value would be 2.2 * IOUT. The programmed current limit IOUT_OC_FAULT_LIMIT must be low enough to ensure that the inductor never saturates and high enough to allow increased current during transient conditions with margin for DCR variation. For example, if ISAT = 2.2 * IOUT, and IMAX = 1.6 * IOUT a reasonable output current limit would be is normally less important for overall efficiency than its input capacitance. MOSFET manufacturers have designed special purpose devices that provide reasonably low onresistance with significantly reduced input capacitance for the main switch application in switching regulators. Selection criteria for the power MOSFETs include onresistance, gate charge, Miller capacitance, breakdown voltage and maximum output current. For maximum efficiency, RDS(ON) and QG should be minimized. Low RDS(ON) minimizes conduction losses and low QG minimizes switching and transition losses. MOSFET gate charge can be taken from the typical gate charge curve included on most data sheets (Figure 21). IOUT_OC_FAULT_LIMIT = 1.8 * IOUT Once the value of L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core losses found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Also, core losses decrease as inductance increases. Unfortunately, increased inductance requires more turns of wire, larger inductance and larger copper losses. Ferrite designs have very low core loss and are preferred at high switching frequencies. However, these core materials exhibit hard saturation, causing an abrupt reduction in the inductance when the peak current capability is exceeded. Do not allow the core to saturate! Power MOSFET Selection The LTC3882-1 requires at least two external N-channel power MOSFETs per channel, one for the top (main) switch and one or more for the bottom (synchronous) switch. The number, type and on-resistance of the MOSFETs selected should take into account the voltage step-down ratio and the FET circuit position (main or synchronous switch). A much smaller and lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than one-third of the input voltage. At operating frequencies above 300kHz and where VIN >> VOUT, the top MOSFET on-resistance MILLER EFFECT VGS QA QB QIN CMILLER = (QB - QA)/VDS 38821 F21 Figure 21. Typical MOSFET Gate Charge Curve CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CMILLER is equal to the increase in gate charge along the horizontal axis of Figure 21 while the curve is approximately flat, divided by the specified change in VDS. This result is then multiplied by the ratio of the actual application VDS to the VDS specified on the gate charge curve. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN Synchronous Switch Duty Cycle = VIN - VOUT VIN 38821f For more information www.linear.com/LTC3882-1 43 LTC3882-1 Applications Information The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: PMAIN = VOUT 2 IMAX ) (1+ )RDS(ON) + ( VIN MOSFET Driver Selection I VIN 2 MAX (RDR ) (CMILLER ) * 2 1 1 + ( fPWM ) VGG - VTH(IL) VTH(IL) V -V 2 PSYNC = IN OUT (IMAX ) (1+ )RDS(ON) VIN where is the temperature dependency of RDS(ON), RDR is the effective top driver resistance, VIN is the drain potential and the change in drain potential in the particular application. VGG is the applied gate voltage, VTH(IL) is the typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current, and CMILLER is the capacitance calculated using the technique previously described. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) versus temperature curve. Typical values for range from 0.005/C to 0.01/C depending on the particular MOSFET used. Both MOSFETs have I2R losses while the topside N-channel losses also include transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. Multiple MOSFETs can be used in parallel to lower RDS(ON) and meet the current and thermal requirements if desired. If using discrete drivers and MOSFETs, check the stress on the MOSFETs by independently measuring the drainto-source voltages directly across the device terminals. Beware of inductive ringing that could exceed the maximum 44 voltage rating of the MOSFET. If this ringing cannot be avoided and exceeds the maximum rating of the device, choose a higher voltage rated MOSFET. Gate driver ICs, DrMOS devices and power blocks with an interface compatible with the LTC3882-1 3.3V three-state PWM control output(s) can be used. An external resistor divider may be needed to set three-state control voltage outputs to mid-rail while in the high impedance state, depending on the driver selected. These external driver/power circuits do not typically present a heavy capacitive load to the LTC3882-1 PWM outputs. Suitable drivers such as the LTC4449 are capable of driving large gate capacitances at high transition rates. In fact, when driving MOSFETs with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (5 or less) to reduce noise and EMI caused by fast transitions. Using PWM Protocols For successful utilization of the driver selected, the appropriate LT3882-1 PWM control protocol must be programmed. The LTC3882-1 supports two three-state PWM control protocols. See bit[1] of the MFR_PWM_ MODE_LTC3882-1 PMBus command. The first of these protocols (bit[1]=0) is for drivers controlled by a single 3-state input that have sufficiently short delay to the diode emulation state (both top and bottom power MOSFETs disabled in a fraction of a PWM cycle), such as the LTC4449. The second protocol (bit[1]=1) handles all other 3.3V compatible drivers with a single 3-state control input. CIN Selection The input bypass capacitance for an LTC3882-1 circuit needs to have ESR low enough to keep the supply drop low as the top MOSFETs turn on, RMS current capability adequate to withstand the ripple current at the input, and a capacitance value large enough to maintain the input voltage until the input supply can make up the difference. Generally, a capacitor that meets the first two requirements (particularly a non-ceramic type) will have far more 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information capacitance than is required to keep capacitance-based droop under control. The input capacitance voltage rating should be at least 1.4 times the maximum input voltage. Power loss due to ESR occurs as I2R dissipation in the capacitor itself. The input capacitor RMS current and its impact on any preceding input network is reduced by PolyPhase architecture. It can be shown that the worst case RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product should be used to determine the maximum RMS current requirement. Increasing the output current drawn from the other out-of-phase controller will decrease the input RMS ripple current from this maximum value. Two channel out-of-phase operation typically reduces the input capacitor RMS ripple current by a factor of 30% to 70%. In continuous inductor conduction mode, the source current of the top power MOSFET is approximately a square wave of duty cycle VOUT/VIN. The maximum RMS capacitor current in this case is given by: IRMS IOUT(MAX) from higher inductance, larger case size and limited surface mount applicability; and electrolytic capacitors have higher ESR and can dry out. Sanyo OS-CON SVP(D) series, Sanyo POSCAP TQC series, or Panasonic EE-FT series aluminum electrolytic capacitors can be used in parallel with a couple of high performance ceramic capacitors as an effective means of achieving low ESR and high bulk capacitance. In addition to PWM bulk input capacitance, a small (0.01F to 1F) bypass capacitor between the chip VINSNS pin and ground, placed close to the LTC3882-1, is also suggested. A small resistor placed between the bulk CIN and the VINSNS pin provides further isolation between the two channels. However, if the time constant of any such R-C network on the VINSNS pin exceeds 30ns, dynamic line transient response can be adversely affected. COUT Selection The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple VOUT is approximately bounded by: 1 VOUT IL ESR+ 8 * f PWM *COUT VOUT ( VIN - VOUT ) VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2 This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that manufacturer ripple current ratings for capacitors are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. Ceramic, tantalum, semiconductor electrolyte (OS-CON), hybrid conductive polymer (SUNCON) and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks. Ceramics have high voltage coefficients of capacitance and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer where IL is the inductor ripple current. IL = VOUT VOUT 1- L * f PWM VIN Since IL increases with input voltage, the output ripple voltage is highest at maximum input voltage. Typically once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Manufacturers such as Sanyo, Panasonic and Cornell Dubilier should be considered for high performance throughhole capacitors. The OS-CON semiconductor electrolyte capacitor available from Sanyo has a good (ESR)(size) product. An additional ceramic capacitor in parallel with polarized capacitors is recommended to offset the effect of lead inductance. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or transient current 38821f For more information www.linear.com/LTC3882-1 45 LTC3882-1 Applications Information The LTC3882-1 is a voltage mode controller with a second, dedicated current sharing loop to provide excellent phaseto-phase current sharing in PolyPhase applications. The current sharing loop is internally compensated. While Type 2 compensation for the voltage control loop may be adequate in some applications (such as with the use of high ESR bulk capacitors), Type 3 compensation and ceramic capacitors are recommended for optimum transient response. Figure 22 shows a simplified view of the error amplifier EA for one LTC3882-1 channel. The positive input of the error amplifier is connected to the output of an internal 12-bit DAC fed by a 1.024V reference, while the negative input is connected to the FB pin and other internal circuits (not all shown). R1 is internal to the IC with a value range given by the RVSFB parameter in the Electrical Characteristics table. The output is connected to COMP, from which the PWM controller derives the required output duty cycle. To speed up overshoot recovery time, the maximum potential at the COMP pin is internally clamped. Unlike many regulators that use a transconductance (gm) amplifier, the LTC3882-1 is designed to use an inverting summing amplifier topology with the FB pin configured as a virtual ground. This allows feedback gain to be tightly controlled by external components, which is not possible with a simple gm amplifier. The voltage feedback amplifier also provides flexibility in choosing pole and zero locations. In particular, it allows the use of Type 3 compensa- 46 C2 VOUT C3 R1 R3 - FB INTERNAL C1 R2 + VDAC EA COMP 3882 F22 Figure 22. Type 3 Compensation Circuit 0 -1 GAIN +1 -1 PHASE (DEG) Feedback Loop Compensation tion to provide phase boost at the LC pole frequency for significantly improving the control loop phase margin, as shown in Figure 23. GAIN (dB) handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent output capacitor choices include the Sanyo POSCAP TPD/E/F series, the Kemet T520, T530 and A700 series, NEC/Tokin NeoCapacitors and Panasonic SP series. Other suitable capacitor types include Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. FREQ -90 PHASE -180 BOOST -270 -380 38821 F23 Figure 23. Type 3 Compensation Frequency Response In a typical LTC3882-1 circuit, the feedback loop closed around this control amplifier and compensation network consists of the line feedforward circuit, the modulator, the external inductor and the output capacitor. All these components affect loop behavior and need to be accounted for in the frequency compensation. The modulator consists of the PWM generator, the output MOSFET drivers and the external MOSFETs themselves. Step-down modulator gain varies linearly with the input voltage. The line feedforward circuit compensates for this change in gain, and provides a constant gain AMOD of 4V/V from the error amplifier output COMP to the inductor input (average DC voltage) regardless of VIN. The combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from COMP to the inductor input with a fairly benign AC behavior at typical loop compensation frequencies. Significant phase shift will not begin to occur in this transfer function until half the switching frequency. 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information The external inductor/output capacitor combination makes a more significant contribution to loop behavior. These components cause a 2nd order amplitude roll-off that filters the PWM waveform, resulting in the desired DC output voltage. But the additional 180 phase shift produced by this filter causes stability issues in the feedback loop and must be frequency compensated. At higher frequencies, the reactance of the output capacitor will approach its ESR, and the roll-off due to the capacitor will stop, leaving -20dB/decade and 90 of phase shift. The transfer function of the Type 3 circuit shown in Figure 22 is given by the following equation: VCOMP -(1+ sC1R2)[1+ s(R1+R3)C3] = VOUT sR1(C1+C2)[1+ s(C1//C2)R2](1+ sC3R3) The RC network across the error amplifier and the feedforward components R3 and C3 introduce two pole-zero pairs to obtain a phase boost at the system unity-gain (crossover) frequency, fC. In theory, the zeros and poles are placed symmetrically around fC, and the spread between the zeros and the poles is adjusted to give the desired phase boost at fC. However, in practice, if the crossover frequency is much higher than the LC double-pole frequency, this method of frequency compensation normally generates a phase dip within the unity bandwidth and creates some concern regarding conditional stability. If conditional stability is a concern, move the error amplifier zero to a lower frequency to avoid excessive phase dip. The following equations can be used to compute the feedback compensation component values: 1 fLC = 2 LCOUT fESR = choose: 1 2RESRCOUT fC =crossover frequency = fPWM 10 1 2R2C1 f 1 fZ2(RES) = C = 5 2(R1+R3)C3 1 fP1(ERR) = fESR = 2R2(C1//C2) 1 fP2(RES) =5fC = 2R3C3 fZ1(ERR) = fLC = Required error amplifier gain at frequency fC is: 2 2 f f 40log 1+ C - 20log 1+ C - 15.56 fLC fESR Once the value of resistor R1 (function of selected VOUT range) and pole/zero locations have been decided, the value of R2, C1, C2, R3 and C3 can be obtained from the previous equations. Compensating a switching power supply feedback loop is a complex task. The applications shown in this data sheet provide typical values, optimized for the power components shown. Though similar power components should suffice, substantially changing even one major power component may degrade performance significantly. Stability also may depend on circuit board layout. To verify the calculated component values, all new circuit designs should be prototyped and tested for stability. The LTPowerCAD software tool can be used as a guide through the entire power supply design process, including optimization of circuit component values according to system requirements. PCB Layout Considerations To prevent magnetic and electrical field radiation or high frequency resonant problems and to ensure correct IC operation, proper layout of the components connected to the LTC3882-1 is essential. Refer to Figure 24, which also illustrates current waveforms typically present in the circuit branches. RSENSE will be replaced with a dead short if DCR sensing is used. For maximum efficiency, the switch 38821f For more information www.linear.com/LTC3882-1 47 LTC3882-1 Applications Information node rise and fall times should be minimized. The following PCB design priority list will help ensure proper topology. sensing is used, place the top resistor (R1, Figure 25) close to the switch node. 1. Place a ground or DC voltage layer between a power layer and a small-signal layer. Generally, power planes should be placed on the top layer (4-layer PCB), or top and bottom layer if more than 4 layers are used. Use wide/short copper traces for power components and avoid improper use of thermal relief around power plane vias to minimize resistance and inductance. 6. Place low ESR output capacitors adjacent to the sense resistor output and ground. Output capacitor ground connections must feed into the same copper that connects to the input capacitor ground before connecting back to system ground. 2. Low ESR input capacitors should be placed as close as possible to switching FET supply and ground connections with the shortest copper traces possible. The switching FETs must be on the same layer of copper as the input capacitors with a common topside drain connection at CIN. Do not attempt to split the input decoupling for the two channels, as a large resonant loop can result. Vias should not be used to make these connections. Avoid blocking forced air flow to the switching FETs with large size passive components. 3. If using a discrete FET driver, place that IC close to the switching FET gate terminals, keeping the connecting traces short to produce clean drive signals. This rule also applies to driver IC supply and ground pins that connect to the switching FET source pins. The driver IC can be placed on the opposite side of the PCB from the switching FETs. 4. Place the inductor input as close as possible to the switching FETs. Minimize the surface area of the switch node. Make the trace width the minimum needed to support the maximum output current. Avoid copper fills or pours. Avoid running the connection on multiple copper layers in parallel. Minimize capacitance from the switch node to any other trace or plane. 5. Place the output current sense resistor (if used) immediately adjacent to the inductor output. PCB traces for remote voltage and current sense should be run together back to the LTC3882-1 in pairs with the smallest spacing possible on any given layer on which they are routed. Avoid high frequency switching signals and ideally shield with ground planes. Locate any filter component on these traces next to the LTC3882-1, and not at the Kelvin sense location. However, if DCR 48 7. Connection of switching ground to system ground, small-signal analog ground or any internal ground plane should be single-point. If the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. This cluster should be located directly beneath the IC GND paddle, which serves as both analog signal ground and the negative sense for VOUT1. A useful CAD technique is to make separate ground nets and use a 0 resistor to connect them to system ground. 8. Place all small-signal components away from high frequency switching nodes. Place decoupling capacitors for the LTC3882-1 immediately adjacent to the IC. 9. A good rule of thumb for via count in a given high current path is to use 0.5A per via. Be consistent when applying this rule. 10. Copper fills or pours are good for all power connections except as noted above in rule 3. Copper planes on multiple layers can also be used in parallel. This helps with thermal management and lowers trace inductance, which further improves EMI performance. Output Current Sensing The ISENSE+ and ISENSE- pins are high impedance inputs to internal current comparators, the current-sharing loop and telemetry ADC. The common mode range of the current sense inputs is approximately 0V to 5.5V. Continuous linear operation is provided throughout this range. Maximum differential current sense input (ISENSE+ - ISENSE-) is 70mV, including any variation over temperature. These inputs must be properly connected in the application at all times. To maximize efficiency at full load the LTC3882-1 is designed to sense current through the inductor's DCR, as shown in Figure 25. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information SW1 L1 D1 RSENSE1 VOUT1 COUT1 RL1 VIN RIN CIN SW0 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. D0 L0 RSENSE0 VOUT0 COUT0 RL0 38821 F24 Figure 24. High Frequency Paths and Branch Current Waveforms for most inductors suitable to LTC3882-1 applications, is between 0.3m and 1m. If the filter RC time constant is chosen to be exactly equal to the L/DCR time constant of the inductor, the voltage drop across the external capacitor is equal to the voltage drop across the inductor DCR. Check the manufacturer's data sheet for specifications regarding the inductor DCR in order to properly dimension the external filter components. The DCR of the inductor can also be measured using a good RLC meter. Use the nominal or measured value of DCR to program IOUT_CAL_GAIN (in m). The temperature coefficient of the inductor's DCR is typically high, like copper. Again, consult the manufacturer's data sheet. The LTC3882-1 can adjust for this non-ideality if the correct MFR_IOUT_CAL_ GAIN_TC value is programmed. Typically this coefficient is around 3900ppm/C. Resistor R1 should be placed close to the switch node, to prevent noise from coupling into sensitive small-signal nodes. Capacitor C1 should be placed close to the IC pins. An example of discrete resistor sensing of output current is shown in Figure 26. Previously, the parasitic inductance of the sense resistor could represent a relatively small error. New high current density solutions may utilize low sense resistor values producing sense voltages less than 20mV. In addition, inductor ripple currents greater than 50% with operation up to 1MHz are becoming more common. Under these conditions, the voltage drop across the sense resistor's parasitic inductance is no longer negligible. An RC filter can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. For example, Figure 27 illustrates the voltage 38821f For more information www.linear.com/LTC3882-1 49 LTC3882-1 Applications Information waveform across a 2m resistor with a 2010 footprint. The waveform is the superposition of a purely resistive component and a purely inductive component. If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the resultant waveform looks resistive, as shown in Figure 28. If low value (<5m) sense resistors are used, verify that the signal across CF resembles the current through the inductor, and reduce RF to eliminate any large step associated with the turn-on of the primary switch. For applications using low maximum sense voltages, check the sense resistor manufacturer's data sheet for information about parasitic inductance. In the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the ESL step and the following equation to determine the ESL: Accurate Kelvin sensing techniques should be used to connect the output voltage differentially back to the LTC3882-1 VSENSE pins of the master channel for the best output voltage regulation at the point of load. These pins also provide the ADC inputs for output voltage telemetry. ESL = Output Voltage Sensing VESL(STEP) tON * tOFF * IL tON + tOFF VIN 12V VINSNS 5V LTC3882-1 VCC VDD33 PWM VCC BOOST INDUCTOR VLOGIC TG LTC4449 IN TS - + GND ISENSE ISENSE GND L DCR VOUT BG R1* C1* 38821 F25 R1 * C1 = L *PLACE R1 NEAR INDUCTOR DCR PLACE C1 NEAR I + - SENSE , ISENSE PINS Figure 25. Inductor DCR Output Current Sense VIN 12V VINSNS LTC3882-1 5V VCC VCC VDD33 VLOGIC TG LTC4449 IN TS PWM - + GND ISENSE ISENSE CF SENSE RESISTOR PLUS PARASITIC INDUCTANCE BOOST GND BG L RS ESL VOUT CF * 2RF ESL/RS POLE-ZERO CANCELLATION RF RF 38821 F26 FILTER COMPONENTS PLACED NEAR SENSE PINS Figure 26. Discrete Resistor Output Current Sense 50 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information While these considerations may or may not be important for slave channels, VOUT must be connected back to the slave channel VSENSE pin(s) in order for the IOUT telemetry of those phases to be accurate. So in general, sound Kelvin VOUT sensing techniques for all LTC3882-1 channels is recommended. VRSENSE 20mV/DIV VESL(STEP) 500ns/DIV 38821 F27 Figure 27. Voltage Measured Directly Across RSENSE VISENSE 20mV/DIV 500ns/DIV 38821 F28 Figure 28. Voltage Measured at ISENSE Pins Soft-Start and Stop The LTC3882-1 uses digital ramp control to create both soft-start and soft-stop. The LTC3882-1 must enter the run state prior to soft-start. The RUN pins are released after the part initializes and VINSNS is determined to be greater than the VIN_ON threshold. Once in the run state, soft-start is performed after any additional prescribed delay (next section) by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set point. Rise time of the voltage ramp can be programmed using the TON_RISE command to minimize inrush currents associated with start-up voltage ramp. The maximum rate at which the LTC3882-1 can move the output in this fashion is 100s/ step. Soft-start is disabled by setting TON_ RISE to any value less than 0.250ms. The LTC3882-1 will perform the necessary math internally to assure the voltage ramp is controlled to the desired slope. However, the voltage slope cannot be any faster than the fundamental limits of the power stage. The smaller TON_RISE becomes, the more noticeable an output voltage stair-step may become. The LTC3882-1 also supports soft turn off in the same manner it controls turn on. TOFF_FALL is processed when the RUN pin goes low or if the part is commanded off. If the part faults off or FAULT is pulled low and the part is programmed to respond to this, the PWM instantly commands the output off. The output will then decay as a function of load current. The LTC3882-1 can produce a controlled ramp off as long as the power stage is configured to run in CCM and the TOFF_FALL time is sufficiently slow that the power stage can achieve the desired slope. The TOFF_FALL time can only be met if the power stage can sink sufficient current under closed loop control to assure the output is at 0V by the end of the fall time. If TOFF_FALL is shorter than the time required to discharge the load capacitance, the output will not reach 0V. In this case, the power stage will still be commanded off at the end of TOFF_FALL and VOUT will decay at a rate determined by the load. If the controller is set to run DCM, the controller will not pull negative current and the output will only be pulled low by the load, not the power stage. The maximum fall time is limited to 1.3 seconds. The smaller TOFF_FALL becomes, the more noticeable an output voltage stair-step may become. Time-Based Output Sequencing and Ramping The LTC3882-1 TON_DELAY and TOFF_DELAY commands can be used in combination with the rise and fall time commands covered in the previous section to implement a wide range of versatile sequencing and ramping schemes. The key to time-based sequencing and ramping is the ability of LTC3882-1 master phases to move their outputs up and down according to PMBus command values as shown in Figure 29 and Figure 30. 38821f For more information www.linear.com/LTC3882-1 51 LTC3882-1 Applications Information As shown in Figure 29, it is important to remember that the hysteresis given in the Electrical Characteristics (EC) table applies above VOUT_UV_FAULT_LIMIT, which specifies the UV limit when the output is falling out of regulation. For turn-on, the output must rise above this programmed limit plus the hysteresis to avoid exceeding TON_MAX_FAULT_ LIMIT. PGOOD is indicated at that point. For this reason, VOUT_UV_FAULT_LIMIT should be more than 27mV below the programmed output voltage in low range and more than 54mV below VOUT in high range. There is a fixed delay and other timing uncertainty associated with all changes in output voltage controlled by the LTC3882-1. A nominal fixed timing delay of 270s exists to process any change in output voltage, including soft start/stop, margining and general changes in VOUT_COMMAND value. The start of all time-based output operations occur with an uncertainty of 50s and have a nominal step resolution of 100s. This means the minimum TON_DELAY or TOFF_DELAY that the LTC3882-1 can produce will range from 220s to 320s, not including basic oscillator tolerances. For softwarebased output changes (e.g., margining), this algorithmic delay begins when the STOP bit is received on the serial bus. An example of this minimum turn on/off delay and step-wise output control can be seen in Figure 31, where TON_DELAY = 0s and TON_RISE = 1ms. To effectively implement sequencing and synchronized ramping between rails controlled by LTC digital power products, two signals should be shared between all controlling ICs: SHARE_CLK and RUN (CONTROL pin on LTC297x products). This facilitates synchronized rail sequencing on or off based on shared input supply state (VIN_ON threshold), external hardware control (RUN pin), or PMBus commands (possibly using global addressing). Figure 32 shows an example of output supply sequencing using TON_DELAY. Using this scheme, conventional coincident and ratiometric tracking can also be emulated by setting equivalent turnon/off delays and appropriate rise and fall times as shown in Figure 33 and Figure 34. In addition, these schemes can easily be mixed and matched to create any necessary ramping controls, some of which might prove difficult to implement with conventional analog-only controllers. These programmable features 52 RUN PGOOD TON_MAX_FAULT_LIMIT DIGITAL SERVO MODE ENABLED FINAL OUTPUT VOLTAGE REACHED VOUT_UV_FAULT_LIMIT DAC VOLTAGE ERROR (NOT TO SCALE) VOUT TIME DELAY OF <1S, TYPICAL HYSTERESIS (NOT TO SCALE) TON_DELAY TON_RISE TIME 38821 F29 Figure 29. Time-Based VOUT Turn-On RUN VOUT TOFF_DELAY TOFF_FALL TIME 38821 F30 Figure 30. Time-Based VOUT Turn-Off greatly simplify actual system development because rails can be re-sequenced without a hardware change as final product requirements evolve. The LTpowerPlay GUI and LTC3882-1 onboard EEPROM can be used for this task, avoiding the need for firmware development to modify turn on/off relationships between rails. Entire power systems can then easily be scaled up or down, facilitating reuse of proven hardware macro designs. Voltage-Based Output Sequencing The LTC3882-1 is capable of voltage-based output sequencing. For concatenated events between members of the LTC388x family, it is possible to control one RUN pin from a PGOOD pin of a different controller as shown in 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information VOUT (1V/DIV) RUN (5V/DIV) 38821 F31 200s/DIV Figure 31. Example of 1ms TON_RISE 1V/DIV VOUT4 Figure 35. This configuration hardware disables the next downstream controller anytime the output is not within the specified UV and OV limits, or the upstream controller is disabled. When indicating power is not good, there is a 30s deglitching filter on the PGOOD output to assure the signal does not toggle repeatedly at lower values of TON_RISE/FALL due to noise on VOUT. If unwanted transitions still occur on PGOOD due to noise or longer rise/fall settings, place a capacitor to ground on the PGOOD pin to further filter the waveform. The RC time-constant of the filter should be low enough to assure no appreciable delay is incurred. A value of 300s to 500s will provide some additional filtering without significantly delaying the trigger event. START VOUT3 VOUT2 PGOOD0 RUN 0 LTC3882-1 RUN 1 PGOOD1 (PGOOD PULL-UP RESISTORS TO 3.3V NOT SHOWN) VOUT1 RUN 0 100ms/DIV 38821 F32 PGOOD0 LTC3882-1 PGOOD1 RUN 1 Figure 32. LTC3882-1 Time-Based Supply Sequencing TO NEXT CHANNEL IN THE SEQUENCE 38821 F35 Figure 35. Cascade Sequencing Configuration 1V/DIV VOUT4 VOUT3 VOUT2 1V/DIV VOUT1 VOUT4 VOUT3 100ms/DIV 38821 F33 Figure 33. LTC3882-1 Time-Based Coincident Supply Ramping VOUT2 VOUT1 100ms/DIV 1V/DIV 38821 F36 Figure 36. Cascade Sequencing Waveforms VOUT4 VOUT3 VOUT2 VOUT1 100ms/DIV 38821 F34 Figure 34. LTC3882-1 Time-Based Ratiometric Ramping When the system is turned off, rails will shut down in the same order as they turn on, as shown in Figure 36. If a different sequence is required, the circuit must be rewired or delays must be added by programming TON_DELAY or TOFF_DELAY. A fundamental limitation of this application is the inability of upstream rails to detect a start-up failure of 38821f For more information www.linear.com/LTC3882-1 53 LTC3882-1 Applications Information downstream rails. Due to this, cascade sequencing should not be implemented without an external fast supervisor to monitor downstream rails and assert a system fault if problems occur. AVP DISABLED IO (10A/DIV) Using Output Voltage Servo For best output voltage accuracy, enable digital servo mode on the master phase by setting bit 6 of MFR_PWM_MODE_LTC3882-1. In digital servo mode, the LTC3882-1 will adjust the regulated output voltage based on its related ADC voltage reading. Every 100ms the digital servo loop will step the LSB of the DAC (nominally 1.375mV or 0.6875mV depending on the voltage range bit) until the output is at the correct ADC reading. 173mV VOUT (50mV/DIV) WITH AVP IO (10A/DIV) When the master channel is turned on, digital servo is enabled after all of the following conditions are satisfied. * MFR_PWM_MODE_LTC3882-1 Bit 6 Is Set VOUT (50mV/DIV) 108mV * The TON_RISE Sequence Is Complete LOOP: BW = 118kHz, PM = 58, GM = 7dB * A VOUT_UV_FAULT Is Not Present Figure 37. Active Voltage Positioning * An IOUT_OC_FAULT Is Not Present * MFR_AVP = 0% Digital servo mode then engages after TON_MAX_ FAULT_LIMIT has expired as shown in Figure 29, unless that limit is set to 0s (infinite). In that case, the mode is engaged as soon as the above conditions are satisfied. Using AVP The LTC3882-1 features digitally programmable active voltage positioning (AVP), where output voltage set point is automatically adjusted as a function of output current at the full bandwidth of the converter. AVP normally entails specifying an output load line for a voltage mode switcher to allow current sharing between master phases connected in parallel. While AVP can be used to this effect in LTC3882-1 applications, use of the LTC3882-1 IAVG current sharing control loop is recommended instead. This will produce more accurate sharing across a wider number of phases without degrading supply output impedance. However, AVP can still be used to great benefit in LTC3882-1 applications. AVP can be applied to minimize the size of 54 38821 F37 output filter capacitance for some allowed output voltage variation over the anticipated load range. An example of AVP is shown in Figure 37. Refer to LTC Design Solution 10 for additional examples of using AVP to advantage. MFR_VOUT_AVP specifies the percent reduction in programmed VOUT from no load at an output current value equal to IOUT_WARN_LIMIT. LTC3882-1 AVP supports a maximum reduction in VOUT of 15%, corresponding to a 7.5% tolerance about a nominal output voltage at roughly 50% load. In order to effectively use AVP, apply the following steps. 1. Set IOUT_OC_WARN_LIMIT. This specifies the master phase output current at which the programmed AVP level will apply. Generally this is above the 100% load point to avoid spurious warnings at full load. 2. VOUT_COMMAND should be set to the value of VOUT desired with no load on the output. VOUT_MARGIN_HIGH/ LOW also specify no-load values when AVP is enabled. AVP on the LTC3882-1 can only reduce the output from these levels. 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information 3. Set MFR_VOUT_AVP to a percentage that produces the desired output excursion as a function of current. For example, if the goal is to allow a 2.5% output change on a 3.3V 6-phase supply rated at 120A during an output load step from 20% to 80%, the following parameters should be programmed. First set an output current warning level for the master (one of six phases) just slightly higher than the rated full load to avoid spurious warnings. Typically this same setting would also be applied to the five slave phases. IOUT_OC_WARN_LIMIT = 1.1 * 120A/6 = 22A The open circuit output voltage calculation for the master phase must reflect that the AVP specification in this case only covers an output load swing of 60%. VOUT_COMMAND = 3.3V(1 + 0.5 * 0.025/0.6) = 3.3687V The AVP calculation must then account for the fact that IOUT_OC_WARN_LEVEL is set higher than the 100% load point. 100% *1.1* 2 * ( 3.3687 - 3.3) MFR_VOUT_AVP = 3.3687 = 4.487% With the output voltage at 3.3V at 50% load these settings will move VOUT from approximately 3.34V to about 3.26V when the output load of the rail moves from 24A to 96A. Note that VOUT will drop to 3.23V at full load in this design example. Digital output servo mode is automatically disabled if AVP is enabled on a master phase. AVP is active during all output ramping when enabled (e.g., a TON_RISE sequence). AVP is disabled on master phases by programming MFR_VOUT_AVP to 0.0% (factory default). AVP is automatically disabled on phases configured as slaves (FB tied to VDD33). Because of related ISENSE input offsets, increased output voltage error can occur at all operating currents when AVP is engaged. To minimize this error a calibration offset can be added to the master phase VOUT_COMMAND value based on the READ_VOUT value obtained when operating at a known output current of at least 20% of full load (READ_IOUT). The necessary correction, which will typically be less than several percent of the no load output voltage, is calculated as: VOS = VOUT_COMMAND MFR_VOUT_AVP *READ_IOUT * 1- 100 *IOUT_OC_WARN_LIMIT - READ_VOUT PWM Frequency Synchronization The LTC3882-1 incorporates an internal phase-locked loop (PLL) which enables synchronization of both PWM channels (falling edge PWM) to an external CMOS clock from 250kHz to 1.25MHz. The PLL is locked to the falling edge of the SYNC pin clock signal. This PLL also generates very accurate channel phase relationships which can be selected with the MFR_PWM_CONFIG_LTC3882-1 command. For PolyPhase applications, all phases should be spaced evenly in the phase diagram for best results. For instance, a 4-phase system should use a separation of 90 between channels. The PLL has a lock detection circuit. If the PLL should lose lock during operation, bit 4 of the STATUS_MFR_SPECIFIC command is asserted and the ALERT pin is pulled low, unless masked. The fault can be cleared by writing a 1 to STATUS_MFR_SPECIFIC bit 4. A spurious ALERT for an unlocked PLL may occur at start-up or during a reset if this fault is not masked. Neither PWM channel will transition from off to the RUN state until PLL lock is indicated. When transitioning a channel from off to RUN, bit 4 of STATUS_MFR_SPECIFIC will be set if the PWM ramp generator for that channel is not also locked to the desired PLL output frequency. If the SYNC pin is not externally clocked in the application, the PWMs will operate at the frequency specified by a nonzero FREQUENCY_SWITCH command. If that command is set to 0x0000 (external clock only) in EEPROM or with RCONFIG (FREQ_CFG pin grounded), then at power-up, or MFR_RESET, or RESTORE_USER_ALL, the PWM will not start without an external clock input. If the external clock is lost while programmed for external clock only, or if the PWM is simply switched to this setting under power with no external clock present, the PLL will start/run at For more information www.linear.com/LTC3882-1 38821f 55 LTC3882-1 Applications Information the lowest free running frequency created by the internal VCO. This can be well below the intended PWM frequency of the application and may cause undesirable operation of the converter. For this reason, it is generally recommended that a useable PWM frequency be programmed for each channel, regardless of whether that particiular LTC3882-1 unit serves as clock master, or not. All channels of a PolyPhase rail are required to share SYNC pins. Between rails and for other configurations, such synchronization is optional. If the SYNC pin is shared between LTC3882-1s, only one LTC3882-1 should be programmed to control the SYNC output. PolyPhase Operation and Load Sharing When the LTC3882-1 is used in a PolyPhase application, the slave phases must be configured as such by connecting their FB pins to VDD33. Among other things, this disables the error amplifiers of the slave phases. Five other pins must then also be shared between all channels of a PolyPhase rail: * VINSNS * COMP * IAVG * IAVG_GND * SYNC Using a common VINSNS connection reduces the dynamic range required by the current loop and helps maintain well-controlled master modulator gain. The shared COMP signal allows the master phase error amplifier to control the duty cycle of all slave phases to produce the commanded output voltage. Slave phases can detect system faults that cause the master COMP (error amplifier) output to be too high. A slave phase detecting this kind of error amplifier fault immediately shuts off its PWM output, indicates the fault on its VOUT_OV Fault bit, and takes whatever additional action may be indicated by VOUT_OV_FAULT_RESPONSE for that channel. If this response is set to only provide hardwarelevel response (0x00), then normal channel operation will automatically resume when the fault condition is cleared. 56 The shared IAVG and IAVG_GND signals actively balance the amount of output current delivered from each channel using a secondary current sharing loop. A capacitor with a value between 100pF and 200pF should be placed between IAVG and IAVG_GND. This capacitance can be distributed across LTC3882-1 devices/pins for improved noise immunity. All IAVG_GND pins for a PolyPhase rail should be tied together and connected to a single ground point at or near the package paddle of the master phase. Load sharing accuracy is based primarily on the current sense amplifier offset of each phase (IAVG_VOS) and the offset of slave current error amplifiers (VSIOS). These are given in the EC table. Current sense gain errors between LTC3882-1 channels will be negligible. The secondary current sharing loop acts to average any errors among the phases. Because of this error averaging and the random nature of these variables, the EC table limits ensure actual per-phase offset will be less than or equal to 300V for most designs over the full operating temperature range. This signifies better than 2% matching when ISENSE = 15mV, not including external factors such as DCR make tolerance. It is necessary to properly connect VSENSE+ on a slave phase for accurate IOUT telemetry, even though slave phases do use need this information for PWM control. While not strictly required, the VSENSE lines of slave phases can simply share with the master to provide additional output voltage telemetry. If the only concern is accurate slave IOUT telemetry, VSENSE+ for that channel may be locally wired to ISENSE-. VSENSE- on a slave phase should always be shorted to VSENSE- for its master channel. IOUT OC/ROC function is not affected by VSENSE wiring. All phases must be synchronized to the same shared SYNC clock and should be programmed to run at the same default PWM frequency. Phases should be selected to be evenly spaced around a 360 phasor diagram, and all phases on a PolyPhase rail should be selected to have the same maximum duty cycle. Refer to details for MFR_ PWM_CONFIG_LTC3882-1. Figure 38 shows an example of connections for three phases and Figure 39 shows an example of an 8-phase rail. Additional shared signals in these figures highlight the ability of the LTC3882-1 to communicate fault status between phases and rails, perform 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information VIN + 3-PHASE SENSE - VDD33 (0,120) (60,240) VINSNS COMP0 FB0 LTC3882-1 COMP1 FB1 VSENSE0+ RUN0 VSENSE1+ RUN1 VSENSE0- VSENSE1- FAULT0 FAULT1 IAVG_GND SYNC (ENABLED) SHARE_CLK IAVG0 IAVG1 GND COMP0 VINSNS FB0 LTC3882-1 COMP1 FB1 VSENSE0+ RUN0 VSENSE1+ RUN1 VSENSE0- VSENSE1- FAULT0 FAULT1 IAVG_GND SYNC (DISABLED) SHARE_CLK IAVG0 IAVG1 GND + 1-PHASE SENSE - SYSTEM ON/OFF BOTH ICs SAME DEFAULT FREQUENCY SWITCH 38821 F38 Figure 38. 3+1-Phase Application 38821f For more information www.linear.com/LTC3882-1 57 LTC3882-1 Applications Information VIN + V SENSE - OUT VDD33 (0,180, CLOCK MASTER) (90,270) VINSNS COMP0 LTC3882-1 FB0 COMP1 FB1 VSENSE0+ RUN0 VSENSE1+ RUN1 VSENSE0- VSENSE1- FAULT0 IAVG_GND FAULT1 SYNC SHARE_CLK IAVG0 IAVG1 GND VINSNS COMP0 LTC3882-1 FB0 COMP1 FB1 VSENSE0+ VSENSE1+ RUN0 RUN1 VSENSE0- VSENSE1- FAULT0 (45,225) (135,315) VINSNS COMP0 LTC3882-1 FB0 COMP1 VSENSE0+ FB1 RUN0 VSENSE1+ RUN1 VSENSE0- VSENSE1- FAULT0 VINSNS COMP0 LTC3882-1 FB0 COMP1 FB1 VSENSE0+ RUN0 VSENSE1+ RUN1 VSENSE0- VSENSE1- FAULT0 FAULT1 SYNC IAVG_GND SHARE_CLK IAVG0 IAVG1 GND FAULT1 SYNC FAULT1 SYNC IAVG_GND SHARE_CLK IAVG0 IAVG1 GND IAVG_GND SHARE_CLK IAVG0 IAVG1 GND SYSTEM ON/OFF ALL ICs SAME DEFAULT FREQUENCY SWITCH 38821 F39 Figure 39. 8-Phase Application 58 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information SINGLE PHASE SW1 V DUAL PHASE SW1 V SW2 V ICIN IL1 ICOUT IL2 ICIN ICOUT 38821 F40 RIPPLE Figure 40. Single and 2-Phase Current Waveforms RMS INPUT RIPPLE CURRENT DC LOAD CURRENT 0.6 1-PHASE 0.5 0.4 0.3 2-PHASE 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 38821 F41 Figure 41. Normalized RMS Input Ripple Current 1.0 0.9 0.8 1-PHASE DIC(P-P) VO/L 0.7 0.6 0.5 0.4 0.3 0.2 2-PHASE 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 38821 F42 Figure 42. Normalized Output Ripple Current [IRMS ~ 0.3(DIC(PP))] synchronized time-based rail sequencing and ramping and report accurate output current telemetry for all phases. In general, only the PGOOD pin of the master phase needs to be used for external Power Good indication. However, PGOOD pins of slave phases may be shorted to a master PGOOD bus to indicate full output power is available, unless the slave channel is used in active phase shedding. In that case, the slave PGOOD should be left disconnected or used only to indicate operating status for that phase. Output current fault and warning limits should each be set to the same values across all PolyPhase channels using IOUT_FAULT_LIMIT and IOUT_WARN_LIMIT. The correct sense resistance and related temperature coefficient should also be set for each phase (IOUT_CAL_GAIN, MFR_IOUT_CAL_GAIN_TC) to achieve accurate IOUT telemetry and consistent fault handling across phases. Because the LTC3882-1 current sharing loop operates by matching sensed voltage, it is important that well-matched sense elements be used in the system. Current matching parameters specified for the LTC3882-1 do not include these external sources of error, such as inductor DCR tolerance. Programming of VOUT related parameters is not required for slave phases. A PolyPhase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied by, the number of phases used as long as the input voltage is greater than the number of phases used times the output voltage. The output ripple amplitude is also reduced by the number of phases used. Figure 40 graphically illustrates the principle. The worst-case RMS ripple current for a single stage design peaks at an input voltage of twice the output voltage. The worst case RMS ripple current for a 2-phase design peaks at output voltages of 1/4 and 3/4 of the input voltage. When the RMS current is calculated, higher effective duty factor results and the peak current levels are divided as long as the current in each stage is balanced. Refer to Application Note 19 at http://www.linear.com/designtools/ app_notes for a detailed description of how to calculate RMS current for the single stage switching regulator. Figure 41 and Figure 42 illustrate how the input and output currents are reduced by using an additional phase. For a 2-phase converter, the input current peaks drop in half and the frequency is doubled. The input capacitor requirement is then theoretically reduced by a factor of four. For more information www.linear.com/LTC3882-1 38821f 59 LTC3882-1 Applications Information high noise environments prevent use of the VBE approach with its lower signal levels. TSNS LTC3882-1 10nF GND MMBT3906 GND 38821 F43 Figure 43. External VBE Temperature Sense 495A TSNS LTC3882-1 GND 1nF GND 1.35V AT 25C 38821 F44 Figure 44. 2D+R Temperature Sense External Temperature Sense The LTC3882-1 facilitates external measurement of the power stage temperature of each channel with several silicon-junction-based means. The voltage produced by the remote sense circuit is digitized by the internal ADC, and the computed temperature value is returned by the paged READ_TEMPERATURE_1 telemetry command. The most accurate external temperature measurement can be made using a diode-connected PNP transistor such as the MMBT3906 as shown in Figure 43 with bit 5 of MFR_PWM_MODE_LTC3882-1 set to 0 (VBE method). The BJT should be placed in contact with or immediately adjacent to the power stage inductor. Its emitter should be connected to the TSNSn pin while the base and collector terminals of the PNP transistor must be returned to the LTC3882-1 GND paddle using a Kelvin connection. For best noise immunity, the connections should be routed differentially and a 10nF capacitor should be placed in parallel with the diode-connected PNP. The LTC3882-1 also supports direct junction voltage measurements when bit 5 of MFR_PWM_MODE_LTC3882-1 is set to one. The factory defaults support a resistor-trimmed dual diode network as shown in Figure 44. However, this measurement method can be applied to simple single-diode circuits of the type shown in Figure 43 with parameter adjustments as described below. This second measurement method is not generally as accurate as the first, but it supports legacy power blocks or may prove necessary if 60 For either method, the slope of the external temperature sensor can be modified with the coefficient stored in MFR_TEMP_1_GAIN. With the VBE approach, typical PNPs require temperature slope adjustments slightly less than 1. The MMBT3906 has a recommended value in this command of approximately MFR_TEMP_1_GAIN = 0.991 based on the ideality factor of 1.01. Simply invert the ideality factor to calculate the MFR_TEMP_1_GAIN. Different manufacturers and different lots may have different ideality factors. Consult with the manufacturer to set this value. Bench characterization over temperature is recommended when adjusting MFR_TEMP_1_GAIN for the direct p-n junction measurement. The offset of the external temperature sense can be adjusted by MFR_TEMP_1_OFFSET. For the VBE method a value of 0 in this register sets the temperature offset to -273.15C. For a direct p-n junction measurement, this parameter adjusts the nominal circuit voltage at 25C away from that shown in Figure 44. To ensure proper use of these temperature adjustment parameters, refer to the specific formulas given for the two methods by the MFR_PWM_MODE_LTC3882-1 command in the later section covering PMBus command details, as well as Application Note 137. Resistor Configuration Pins As a factory default, the LTC3882-1 is programmed to use external resistor configuration, allowing output voltage, PWM frequency and phasing, and the PMBus address to be set without programming the part through its serial interface or purchasing devices with custom EEPROM contents. The RCONFIG pins all require a resistor divider between VDD25 and GND. The RCONFIG pins are only interrogated at initial power up and during a reset, so modifying their values on the fly is not recommended. RCONFIG pins on the same IC can be shared with a single resistor divider if they require identical programming. Resistors with a tolerance of 1% or better must be used to assure proper operation. In the following tables, RTOP is connected between VDD25 and the RCONFIG pin, while RBOT is connected between the pin and GND. Noisy clock signals should not be routed near these pins. 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information Table 8. VOUTn_CFG Resistor Programming Table 9. FREQ_CFG Resistor Programming RTOP (k) RBOT (k) VOUT (V) 0 or Open 10 10 16.2 16.2 20 20 20 20 24.9 24.9 24.9 24.9 24.9 30.1 30.1 Open 23.2 15.8 20.5 17.4 17.8 15 12.7 11 11.3 9.09 7.32 5.76 4.32 3.57 1.96 From EEPROM 5.0 3.3 2.5 1.8 1.5 1.35 1.25 1.2 1.15 1.1 1.05 0.9 0.75 0.65 0.6 Open 0 Output OFF* (VOUT from EEPROM) *OPERATION value and RUNn pin must both command the channel to start from this configuration. Output voltage can be set as shown in Table 8. For example, setting RTOP to 16.2k and RBOT to 17.4k is equivalent to programming a VOUT_COMMAND value of 1.8V. Refer to the Operations section for related parameters that are also automatically set as a percentage of the programmed VOUT if resistor configuration pins are used to determined output voltage. RTOP (k) RBOT (k) SWITCHING FREQUENCY (kHz) 0 or Open 20 20 20 20 24.9 24.9 24.9 24.9 24.9 30.1 30.1 Open Open 17.8 15 12.7 11 11.3 9.09 7.32 5.76 4.32 3.57 1.96 0 from EEPROM 1250 1000 900 750 600 500 450 400 350 300 250 External SYNC Only Note that if SYNC pins are shared between LTC3882-1s, only one SYNC output should be enabled. All other SYNC outputs should be disabled. For example, if configuring two LTC3882-1s as a 4-phase rail operating at a frequency of 600kHz, both devices should have RTOP of 24.9k and RBOT of 11.3k on the FREQ_CFG pin. In this case, selecting RTOP of 24.9k and RBOT of 9.09k for PHAS_CFG on the first IC (clock master) affords 180 of phase separation and enables the SYNC output. The second device should have RTOP of 20k and RBOT of 12.7k on PHAS_CFG, to )disable its SYNC output and run its phases with 180 of separation in quadrature with the first IC. Only mix phase selections that have the same maximum duty cycle specified. Refer to Tables 9 and 10. Table 10. PHAS_CFG Resistor Programming RTOP (k) RBOT (k) SYNC TO 0 SYNC TO 1 MAXIMUM DUTY CYCLE SYNC OUTPUT DISABLED 0 or Open Open From EEPROM From EEPROM See MFR_PWM_CONFIG From EEPROM 20 15 135 315 87.5% Yes 20 12.7 90 270 20 11 45 225 24.9 11.3 0 180 24.9 9.09 0 180 24.9 7.32 120 300 24.9 5.76 60 240 24.9 4.32 0 180 30.1 3.57 0 120 30.1 1.96 0 180 Open 0 0 120 No 83.3% Yes No 38821f For more information www.linear.com/LTC3882-1 61 LTC3882-1 Applications Information The LTC3882-1 address is selected based on the programming of the two configuration pins ASEL0 and ASEL1 according to Table 11. ASEL0 programs the bottom four bits of the device address for the LTC3882-1, and ASEL1 programs the three most-significant bits. Either portion of the address can also be retrieved from the MFR_ADDRESS value in EEPROM. If both pins are left open, the full 7-bit MFR_ADDRESS value stored in EEPROM is used to determine the device address. In the 4-phase example above, it is recommended that one or both ASELn pins on both parts be programmed to create two unique addresses. The LTC3882-1 also responds to 7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS should not be set to either of these values. Table 11. ASELn Resistor Programming RTOP (k) RBOT (k) ASEL1 ASEL0 LTC3882-1 DEVICE ADDRESS BITS[6:4] LTC3882-1 DEVICE ADDRESS BITS[3:0] BINARY HEX from EEPROM BINARY HEX 0 or Open Open from EEPROM 10 23.2 1111 F 10 15.8 1110 E 16.2 20.5 1101 D 16.2 17.4 1100 C 20 17.8 1011 B 20 15 1010 A 20 12.7 1001 9 20 11 1000 8 24.9 11.3 111 7 0111 7 24.9 9.09 110 6 0110 6 24.9 7.32 101 5 0101 5 24.9 5.76 100 4 0100 4 24.9 4.32 011 3 0011 3 30.1 3.57 010 2 0010 2 30.1 1.96 001 1 0001 1 Open 0 000 0 0000 0 Do not draw more than 20mA from the internal 3.3V regulator for the host system, governed by IC power dissipation as discussed in the next section. This limit includes current required for external pull up resistors for the LTC3882-1 that are terminated to VDD33. VDD33 powers a second internal 2.5V LDO whose output is present on VDD25. This 2.5V supply provides power for much of the internal processor logic on the LTC3882-1. The VDD25 output should be bypassed directly to GND with a low ESR X5R or X7R ceramic capacitor with a value of 1F or greater. Do not draw any external system current from this supply beyond that required for LTC3882-1 specific configuration resistor dividers. IC Junction Temperature The user must ensure that the maximum rated junction temperature is not exceeded under all operating conditions. The thermal resistance of the LTC3882-1 package (JA) is 33C/W, provided the exposed pad is in good thermal contact with the PCB. The actual thermal resistance in the application will depend on forced air cooling and other heat sinking means, especially the amount of copper on the PCB to which the LTC3882-1 is attached. The following formula may be used to estimate the maximum average power dissipation PD (in watts) of the LTC3882-1 when VCC is supplied externally. PD = VCC(0.024 + fPWM * 1.6e-5 + IEXT + IRC25) where: Internal Regulator Outputs The VDD33 pin provides supply current for much of the internal LTC3882-1 analog circuitry at a nominal value of 3.3V. The LTC3882-1 features an internal linear regulator that can be used to supply 3.3V to VDD33 from a higher voltage VCC supply (up to 12V nominal). Use of this LDO is optional. The LTC3882-1 will also accept an external 3.3V 62 supply attached to this pin if VCC and VDD33 are shorted. If the internal 3.3V LDO is used, it can supply a peak current of 85mA (including internal consumption), and the VDD33 regulator output must be bypassed to GND with a low ESR X5R or X7R ceramic capacitor with a value of 2.2F. If an external source supplies VDD33, a local low ESR bypass capacitor with a value between 0.01F and 0.1F should be placed directly between the VDD33 and GND pins. IEXT = total external load drawn from VDD33, including local pull-up resistors, in amps IRC25 = total current drawn from VDD25 by LTC3882-1 configuration resistor dividers, in amps and the PWM frequency fPWM is given in kHz For more information www.linear.com/LTC3882-1 38821f LTC3882-1 Applications Information If an external source supplies VDD33 directly, the following formula may be used to estimate the maximum average power dissipation PD (in watts) of the LTC3882-1 PD = VDD33(0.024 + fPWM * 1.6e-5 + IRC25) The maximum junction temperature of the LTC3882-1 in C may then be found from the following equation Configuring Open-Drain Pins The LTC3882-1 has the following open-drain pins: 3.3V Pins 1. PGOODn 2. FAULTn 2. SYNC TJ = TA + 33 * PD with ambient temperature TA expressed in C Derating EEPROM Retention at Temperature EEPROM read operations between 85C and 125C will not affect data storage. But retention will be degraded if the EEPROM is written above 85C or stored above 125C. If an occasional fault log is generated above 85C, the slight reduction in data retention in the EEPROM fault log area will not affect the use of the function or other EEPROM storage. See the Operation section for other high temperature EEPROM functional details. Degradation in data can be approximated by calculating the dimensionless acceleration factor using the following equation. Ea 1 1 - * k TUSE +273 TSTRESS +273 AF = e Where: 3. SHARE_CLK 5V-Capable Pins (These pins operate correctly when pulled to 3.3V.) 1. RUNn 2. ALERT 3. SCL 4. SDA All of the above pins have on-chip pull-down transistors that can sink 3mA at 0.4V. The low-state threshold on these pins is 1.4V, so ample noise margin exists with 3mA of current. For 3.3V pins, 3mA of current is produced by a 1.1k pull-up resistor. Unless there are transient speed issues associated with the RC time constant of the net, a 10k resistor or larger is generally recommended. The pull-up resistor for PGOOD should be terminated to the LTC3882-1 VDD33 pin or a separate bias supply under 3.6V that is up before the LTC3882-1 is enabled. Otherwise, power-not-good may be falsely indicated after the PWM outputs are running. AF = acceleration factor Ea = activation energy = 1.4eV k = 8.617 * 10-5 eV/K TUSE = is the specified junction temperature TSTRESS = actual junction temperature in C As an example, if the device is stored at 130C for 10 hours, TSTRESS = 130C, and 1 1.4 1 - * -5 398 403 = 1.66 AF = e 8.617*10 indicating the effect is the same as operating the device at 125C for 10 * 1.66 = 16.6 hours, resulting in a retention derating of 6.6 hours. The SYNC pin has an on-chip pull-down transistor with the output held low for nominally 250ns when driven by the LTC3882-1. If the internal oscillator is set for 500kHz and the load is 100pF with a 1/3 rise time required, the resistor calculation is as follows: RPULLUP = 2s - 250ns = 5.83k 3 *100pF The closest 1% resistor is 5.76k. If timing errors are occurring or if the SYNC amplitude is not as large as required, monitor the waveform and determine if the RC time constant is too long for the 38821f For more information www.linear.com/LTC3882-1 63 LTC3882-1 Applications Information application. If possible reduce the parasitic capacitance. Otherwise reduce the pull-up resistor sufficiently to assure proper operation. The SHARE_CLK output has a nominal period of 10s and is pulled low for about 1s. If the system load on this shared line is 100pF, the resistor calculation for this line with a 1/3 rise time is: RPULLUP = 9s = 30k 3 *100pF The closest 1% resistor is 30.1k. For high speed signals such as SDA, SCL and SYNC, a lower value resistor may be required. The RC time constant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. For a 100pF load and a 400kHz PMBus communication rate, the resistor pull-up on the SDA and SCL pins with the time constant set to 1/3 the rise time equals RPULLUP = tRISE = 1k 3 *100pF The closest 1% resistor value is 1k. Be careful to minimize parasitic capacitance on the SDA and SCL lines to avoid communication problems. To estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. This is one time constant. PMBus Communication and Command Processing The LTC3882-1 has a one deep buffer to hold the last data written for each supported command prior to processing, as shown in Figure 45. Two distinct parallel sections of the LTC3882-1 manage command buffering and command processing to ensure the last data written to any command is never lost. When the part receives a new command from the bus, command data buffering copies the data into the write command data buffer and indicates to the internal processor that data for that command should be handled. The internal processor runs in parallel and performs the sometimes slower task of fetching, converting (to internal format) and executing commands so marked for processing. 64 Some computationally intensive commands (e.g., timing parameters, temperatures, voltages and currents) have internal processor execution times that may be long relative to PMBus timing. If the part is busy processing a command, and a new command(s) arrives, execution may be delayed or processed in a different order than received. The part indicates when internal calculations are in process with bit 5 of MFR_COMMON (LTC3882-1 Calculations Not Pending). When the internal processor is busy calculating, bit 5 is cleared. When this bit is set, the part is ready for another command. An example polling loop is provided in Figure 46, which ensures that commands are processed in order while simplifying error handling routines. MFR_COMMON always returns valid data at PMBus speeds between 10kHz and 400kHz. When the part receives a new command while it is busy, it will communicate this condition using standard PMBus protocol. Depending on part configuration it may either NACK the command or return all ones (0xFF) for reads. It may also generate a BUSY fault and ALERT notification, or stretch the SCL clock low. For more information refer to PMBus Specification V1.2, Part II, Section 10.8.7 and SMBus V2.0 section 4.3.3. Clock stretching can be enabled by asserting bit 1 of MFR_CONFIG_ALL_LTC3882-1. Clock stretching will only occur if enabled and the bus communication speed exceeds 100kHz. PMBus protocols for busy devices are well accepted standards but can make writing system level software somewhat complex. The part provides three handshaking status bits which reduce this complexity while enabling robust system level communication. The three hand CMD PMBus WRITE WRITE COMMAND DATA BUFFER DECODER PAGE CMDS DATA MUX CALCULATIONS PENDING S R 0x00 INTERNAL PROCESSOR 0x21 FETCH, CONVERT DATA AND EXECUTE * * * VOUT_COMMAND * * * MFR_RESET 0xFD x1 38821 F45 Figure 45. Write Command Data Processing 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information shaking status bits are in the MFR_COMMON register. When the part is busy executing an internal operation, it will clear bit 6 of MFR_COMMON (LTC3882-1 Not BUSY). When internal calculations are in process, the part will clear bit 5 of MFR_COMMON (LTC3882-1 Calculations Not Pending). When the part is busy specifically because it is // wait until bits 6, 5, and 4 of MFR_COMMON are all set do { mfrCommonValue = PMBUS_READ_BYTE(0xEF); partReady = (mfrCommonValue & 0x68) == 0x68; }while(!partReady) // now the part is ready to receive the next command PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V Figure 46. Example of a Polling Loop to Write VOUT_COMMAND transitioning VOUT (margining, off/on, moving to a new VOUT_COMMAND, etc.) it will clear bit 4 of MFR_COMMON (LTC3882-1 Output Not In Transition). These three status bits can be polled with a PMBus read byte of the MFR_COMMON register until all three bits are set. A command immediately following all these status bits being set will be accepted without a NACK, BUSY fault or ALERT notification. The part can NACK commands for other reasons, however, as required by the PMBus specification (e.g., an invalid command or data). An example of a robust command write algorithm for the VOUT_COMMAND register is provided in Figure 46. It is recommended that all command writes be preceded with such a polling loop to avoid the extra complexity of dealing with busy behavior or unwanted ALERT notifications. A simple way to achieve this is to embed the polling in subroutines to write command bytes and words. This polling mechanism will allow system software to remain clean and simple while robustly communicating with the part. For a detailed discussion of these topics and other special cases please refer to the application note section located at www.linear.com/designtools/app_notes. When communicating using bus speeds at or below 100kHz, the polling mechanism previously shown provides a simple solution that ensures robust communication without clock stretching. At bus speeds in excess of 100kHz, it is strongly recommended that the part be enabled to use clock stretching, requiring a PMBus mas- ter that supports that function. Clock stretching does not allow the LTC3882-1 to communicate reliably on busses operating above 400kHz. Operating the LTC3882-1 with PMBus SCL rates above 400kHz is not recommended. System software that detects and properly recovers from the standard PMBus NACK responses or BUSY faults described in PMBus Specification V1.2, Part II, Section 10.8.7 is required to communicate above 100kHz without clock stretching. Refer to Application Note 135 for techniques that may also apply to implement a robust PMBus interface to the LTC3882-1. Status and Fault Log Management Due to internal operation, very infrequently the LS byte of STATUS_WORD may be inconsistent with the state of bits in the MS byte. This condition is quite transient and can normally be resolved by simply re-reading STATUS_WORD. If power is lost during an internal store of a fault log to EEPROM, a partial write of the log can result. In this situation, the LTC3882-1 will not indicate that a fault log is present the next time adequate supply voltage is applied (bit 3 of STATUS_MFR_SPECIFIC). The existence of a partial fault log can be detected by examining the header of the log (MFR_FAULT_LOG). If the first two words of the Fault Log Preface contain valid data as specified by Table 2, and STATUS_MFR_SPECIFIC does not indicate the presence of a complete fault log, then a partial log existed in EEPROM at boot and has been retrieved to RAM. The only way to then determine how much of the log is actually valid is by subjective evaluation of the contents of each log event record. MFR_CLEAR_FAULT_LOG will permanently erase a partial fault log, allowing a subsequent log to be written. It is a good practice to always check for a partial fault log at power-up if fault logging is enabled (bit 7 of MFR_CONFIG_ALL_LTC3882-1). LTpowerPlay - An Interactive Digital Power GUI LTpowerPlay is a powerful Windows-based development environment that supports Linear Technology Power System Management ICs, including the LTC3882-1. LTpowerPlay can be used to evaluate LTC products by connecting to a Linear Technology demo circuit or user application. 38821f For more information www.linear.com/LTC3882-1 65 LTC3882-1 Applications Information LTpowerPlay can also be used offline (no hardware present) to build multiple IC configuration files that can be saved and later reloaded. LTpowerPlay uses the DC1613 USB-to-I2C/SMBus/PMBus controller to communicate with a system for evaluation, development or debug. The software also features automatic update to remain upto-date with the latest device drivers and documentation available from Linear Technology. A great deal of context sensitive help is available within LTpowerPlay, along with several tutorials. Complete information is available at http:// www.linear.com/ltpowerplay. Interfacing to the DC1613 The LTC DC1613 USB-to-I2C/SMBus/PMBus controller can be interfaced to the LTC3882-1 on any board for programming, telemetry and system debug. This includes the DC1936 from Linear Technology, or any customer target system. The controller, when used in conjunction with LTpowerPlay, provides a powerful way to debug an entire power system. Faults are quickly diagnosed using telemetry, fault status registers and the fault log. The final configuration can be quickly developed and stored to the LTC3882-1 EEPROM and/or LTpowerPlay configuration file. The DC1613 can communicate with, program and even power one or more LTC3882-1s, regardless of whether system supplies are up. The DC2086 Powered Programming Adapter can be used to extend the power sourcing capability of the DC1613. Figure 47 illustrates an application schematic for in-system programming of multiple LTC3882-1s normally powered from a VCC system supply (5V to 12V). If VCC is applied, the DC1613 will not supply the LTC3882-1s on the board. If the DC2086 is used, PFETs with lower RDS(ON), such as the SiA907EDJT, should be used in place of the TP0101K devices. Figure 48 shows an example when the system normally provides 3.3V directly to the LTC3882-1(s). If system supplies are not up in either of these circuits, the DC1613 will power the LTC3882-1 VDD33 supply, allowing in-circuit configuration or manufacturing customization. These circuits also facilitate remote diagnostics, control and reprogramming of the LTC3882-1 while the host system is fully operational, permitting very flexible insystem debugging. 66 If the system supply is restored while power is still applied by the DC1613 or DC2086, the LTC3882-1 can often be ready to initiate output soft-start before sufficient supply bias for the power stage has been established. Create additional LTC3882-1 delay with TON_DELAY or use a common system RUN line to control both the LTC3882-1 and its related power stages based on acceptable operating parameters, as shown in Figure 55. The DC1613 I2C connections are opto-isolated from the host PC USB. The DC1613 3.3V current limit is only 100mA, so it should only be used to power one or two LTC3882-1s in-system. Because of this limited current sourcing capability, only the LTC3882-1s, their associated pull-up resistors and the I2C pull-up resistors should be powered from the isolated 3.3V supply provided by the DC1613. Using the DC2086 will enable in-system programming of several tens of LTC3882-1 devices without normal system power applied. Any other device sharing the I2C bus with the LTC3882-1 should not have body diodes between their SDA/SCL pins and their respective logic supply, because this will interfere with bus communication in the absence of system power. Hold the RUN pins low externally to avoid providing power to the load until the part is fully configured. Design Example As a design example, consider a 132W 2-phase application such as the one shown in Figure 53, where VIN = 36V, VOUT = 3.3V, and IOUT = 40A. A fully discrete power stage design is employed to allow better optimization given these demanding requirements. Assume that a secondary 5V supply will be available in the system for the LTC3882-1 VCC supply. The necessary local bypassing is then provided for the VDD33 (2.2F) and VDD25 (1F) LDO outputs. These LDO outputs should not be shared with other ICs that might have outputs of the same name, because they have independent, internal control loops. When VDD33 is used as the LTC3882-1 supply input, it may be shared with other ICs operating from that 3.3V supply. Local HF bypassing of at least 0.1F is still required on VDD33 in this case. First, the regulated output is established by programming the VOUT_COMMAND stored in EEPROM to 3.3V. 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information SYSTEM VCC TP0101K 102k LT6703-2 -IN VS 10k VCC TP0101K - OUT 10k + 2N2002 10k VDD33 2.2F 10k VDD25 LTC3882-1 1F SDA 10k SCL GND 400mV REFERENCE GND LTC CONTROLLER HEADER VCC 4.7F ISOLATED 5V 2.2F SDA SCL VDD33 VDD25 LTC3882-1 1F SDA SCL GND TO LTC DC1613 USB TO I2C/SMBus/PMBus CONTROLLER 38821 F47 Figure 47. DC1613 Connection (VCC Supply) 38821f For more information www.linear.com/LTC3882-1 67 LTC3882-1 Applications Information ENBA STAT GND ENBB INB SYSTEM 3.3V LTC4413 VCC OUTB VDD33 0.1F CONTROL CIRCUIT 10k 10k INA OUTA VDD25 LTC3882-1 1F SDA SCL GND LTC CONTROLLER HEADER VCC ISOLATED 3.3V SDA 0.1F SCL VDD33 VDD25 LTC3882-1 1F SDA SCL GND TO LTC DC1613 USB TO I2C/SMBus/PMBus CONTROLLER 38821 F48 Figure 48. DC1613 Connections (VDD33 Supply) 68 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 Applications Information The frequency and phase are also set by EEPROM values. Assume that solution footprint or vertical clearance is an issue, so operating frequency will need to be increased in an effort to minimize inductor value (size). This choice could also result from the need to have above average transient performance, although efficiency may be reduced slightly. FREQUENCY_SWITCH is set to 1.0MHz. As a 2-phase system, MFR_PWM_CONFIG_LTC3882-1 is programmed to 0x14 to put Channel 0 phase at 0 and Channel 1 phase at 180. This produces the lowest input ripple possible with this configuration and allows this output to synchronize with other rails via SHARE_CLK. The design will plan on a nominal output ripple of 70% of IOUT to minimize the magnetics volume, and the inductance value is chosen based on this assumption. Each channel supplies an average 20A to the output at full load, resulting in a ripple of 14AP-P. A 200nH inductor per phase would create this peak-to-peak ripple at 1.0MHz. A Pulse PA0513.22LT 210nH inductor with a DCR of 0.32m typical is selected. Setting IOUT_FAULT_LIMIT to 35A per phase leaves plenty of headroom for transient conditions while still adequately protecting against the rated inductor saturation current of 45A at temperature. For top and bottom power FETs, the 40V rated Infineon BSC050N04LSG and BSC010N04LS are chosen, respectively. These afford both low RDS(ON) and low gate charge QG. Two of each of these could be paralleled to achieve improved efficiency at full load, if desired. The LTC4449 gate driver is chosen for its fast response (13ns), suitable gate drive, VIN capability (38V) and the ease with which it can be interfaced to the LTC3882-1. Basic three-state control, CCM operation, fast boost refresh, low VOUT range and digital output voltage servo are selected by programming MFR_PWM_MODE_LTC3882-1 to 0xC0 for both channels. For input filtering, a 47F SUNCON capacitor and four 22F ceramic capacitors are selected to provide acceptable AC impedance against the designed converter ripple current. Four 470F 9m POSCAPs and two 100F ceramic capacitors are chosen for the output to maintain supply regulation during severe transient conditions and to minimize output voltage ripple. A loop crossover frequency of 100kHz provides good transient performance while still being well below the switching frequency of the converter. The values of R29, R30 and C25 to C27 were determined to produce a nominal system phase margin of about 65 at this bandwidth. For the DCR sense filter network, R = 3.09k and C = 220nF are chosen to match the L/DCR time constant of the inductor. PolyPhase connections (IAVG, et al) are shown in the schematic to ensure good output current sharing between the two power stages. External temperature sense will employ an accurate VBE method, and Q1 and Q2 serve to sense the temperature of L1 and L2, respectively. These components will be located immediately adjacent to their chokes and the 10nF filter capacitors placed with the BJTs. Resistor configuration is used on the ASELn pins to program PMBus address (MFR_ADDRESS) to 0x4C. Each LTC3882-1 must be configured for a unique address. Using both ASELn pins to accomplish this programming is recommended for simpliest in-system programming. Check the selected address to avoid collision with global addresses other any other specific devices. Identical MFR_RAIL_ADDRESS can be set in EEPROM for both channels to allow single-command control of common rail parameters such as IOUT_OC_FAULT_LIMIT. The LTC3882-1 also responds to 7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS should not be set to either of these values. PMBus connection (three signals), as well as shared RUN control and fault propagation (FAULT) are provided. SYNC can be used to synchronize other PWMs to this rail if required. Pull-ups are provided on all these shared open-drain signals assuming a maximum 100pF line load and PMBus rate of 100kHz. These pins should not be left floating. Termination to 3.3V ensures the absolute maximum ratings for the pins are not exceeded. All other operating parameters such as soft start/stop and desired faults responses are programmed via PMBus command values stored in internal LTC3882-1 EEPROM. 38821f For more information www.linear.com/LTC3882-1 69 LTC3882-1 PMBus COMMAND DETAILS (by functional groups) Addressing and Write Protect COMMAND NAME CMD CODE DESCRIPTION DATA PAGED FORMAT PAGE 0x00 Channel (page) presently selected for any paged command. PAGE_PLUS_WRITE 0x05 Write a command directly to a specified page. PAGE_PLUS_READ 0x06 Read a command directly from a specified page. WRITE_PROTECT 0x10 Protect the device against unintended PMBus modifications. R/W Byte N MFR_ADDRESS 0xE6 Specify right-justified 7-bit device address. R/W Byte MFR_RAIL_ADDRESS 0xFA Specify unique right-justified 7-bit address for channels comprising a PolyPhase output. R/W Byte TYPE R/W Byte N W Block N Block R/W Process N UNITS NVM Reg DEFAULT VALUE 0x00 0x00 Reg l N Reg l 0x4F Y Reg l 0x80 Related commands: MFR_COMMON. PAGE The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physical address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating memory for one PWM channel. Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device. Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTC3882-1 will respond to read commands as if PAGE were set to 0x00 (Channel 0 results). This command has one data byte. PAGE_PLUS_WRITE The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command and then send the data for the command, all in one communication packet. Commands allowed by the present write protection level may be sent with PAGE_PLUS_WRITE. The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send a non-paged command, the Page Number byte is ignored. This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a command that has two data bytes is shown in Figure 49. 1 7 1 1 S SLAVE ADDRESS W A 8 1 PAGE_PLUS A COMMAND CODE 8 LOWER DATA BYTE 8 1 8 1 8 1 BLOCK COUNT (= 4) A PAGE NUMBER A COMMAND CODE A 1 8 1 8 1 1 A UPPER DATA BYTE A PEC BYTE A P ... 38821 F49 Figure 49. Example of PAGE_PLUS_WRITE 70 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Addressing and Write Protect) PAGE_PLUS_READ The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command and then read the data returned by the command, all in one communication packet . The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access data from a non-paged command, the Page Number byte is ignored. This command uses Block Write - Block Read Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown in Figure 50. NOTE: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another PAGE_PLUS command. If this is attempted, the LTC3882-1 will NACK the entire PAGE_PLUS packet and issue a CML fault for Invalid/Unsupported Data. 1 7 S SLAVE ADDRESS 1 7 Sr SLAVE ADDRESS 1 1 W PAGE_PLUS A A COMMAND CODE 1 R 8 1 8 A BLOCK COUNT (= 2) 1 8 BLOCK COUNT (= 2) 1 8 A LOWER DATA BYTE 1 8 A PAGE NUMBER 1 8 1 A COMMAND CODE A 1 8 1 8 A UPPER DATA BYTE A PEC BYTE 1 ... 1 NA P 38821 F50 Figure 50. Example of PAGE_PLUS_READ WRITE_PROTECT The WRITE_PROTECT command is used to control PMBus write access to the LTC3882-1. Supported Values: VALUE MEANING 0x80 Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL and MFR_EE_UNLOCK commands. 0x40 Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL, MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands. Individual faults can also be cleared by writing a 1 to the respective status bit. 0x20 Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL, MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG and VOUT_COMMAND commands. Individual faults can be cleared by writing a 1 to the respective status bit. 0x00 Enables writes to all commands. This command has one data byte. 38821f For more information www.linear.com/LTC3882-1 71 LTC3882-1 PMBus COMMAND DETAILS (Addressing and Write Protect) MFR_ADDRESS The MFR_ADDRESS command sets the seven bits of the PMBus device address for this unit (right justified). Setting this command to a value of 0x80 disables device-level addressing. The GLOBAL device addresses 0x5A and 0x5B cannot be disabled. The LTC3882-1 always responds at these addresses. Even if bit 6 of MFR_CONFIG_ALL_ LTC3882-1 is set to ignore the device resistor configuration pins, any valid address, or portion of an address, specified with external resistors on ASEL0 or ASEL1 is applied. If both of these pins are open, the device address is determined strictly by the MFR_ADDRESS value stored in EEPROM. Refer to the Operation section on Resistor Configuration Pins for additional details. This command has one data byte. MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command sets a direct 7-bit PMBus address (right justified) for the active channel(s) as determined by the PAGE command. This address should be common to all channels attached to a single power supply rail. Setting this command to a value of 0x80 disables rail device addressing for the selected channel. Only command writes should be made to the rail address. If a read is performed from this address, a CML fault may result. This command has one data byte. General Device Configuration COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT PMBUS_REVISION 0x98 Supported PMBus version. R Byte Y Reg 0x22 V1.2 CAPABILITY 0x19 Summary of supported optional PMBus features. R Byte N Reg 0xB0 MFR_CONFIG_ALL_LTC3882-1 0xD1 LTC3882-1 device-level configuration. R/W Byte N Reg UNITS NVM l DEFAULT VALUE 0x01 PMBUS_REVISION The PMBUS_REVISION command returns the revision of the PMBus Specification that the device supports. The LTC3882-1 is compliant with PMBus Version 1.2, both Part I and Part II. This read-only command has one data byte. CAPABILITY The CAPABILITY command reports some key LTC3882-1 features to the PMBus host device. The LTC3882-1 supports packet error checking, 400kHz bus speeds and has an ALERT output. This read-only command has one data byte. 72 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (General Device Configuration) MFR_CONFIG_ALL_LTC3882-1 The MFR_CONFIG_ALL_LTC3882-1 command provides device-level configuration common to multiple LTC PMBus products. Bit Definitions: BIT MEANING 7 Enable fault logging. 6 Ignore resistor configuration pins. Does not apply to ASEL0 or ASEL1. 5 Disable CML fault for Quick Command message. 4 Disable SYNC output. 3 Enable 255ms PMBus timeout. 2 Require valid PEC for PMBus write. 1 Enable PMBus clock stretching. 0 Execute CLEAR_FAULTS on rising edge of either RUN pin. If a legal command is received with an invalid PEC, the LTC3882-1 will not execute the command, regardless of the state of bit 2. If clock stretching is enabled, the LTC3882-1 only uses it as required, generally above SCL rates of 100kHz. This command has one data byte. On, Off and Margin Control COMMAND NAME CMD CODE DESCRIPTION ON_OFF_CONFIG 0x02 RUN pin and PMBus on/off command configuration. OPERATION 0x01 On, off and margin control. MFR_RESET 0xFD Force full reset without removing power. TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE Y Reg l 0x1E R/W Byte Y Reg l 0x80 Send Byte N R/W Byte ON_OFF_CONFIG The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to turn the PWM channel on and off. Supported Values: VALUE MEANING 0x1F OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off. 0x1E OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off. 0x17 RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored. 0x16 RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored. Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored. This command has one data byte. 38821f For more information www.linear.com/LTC3882-1 73 LTC3882-1 PMBus COMMAND DETAILS (On, Off and Margin Control) OPERATION The OPERATION command is used to turn the PWM channel on and off in conjunction with RUN pin hardware control. This command may also be used to move the output voltage to margin levels. VOUT changes commanded by OPERATION margin commands occur at the programmed VOUT_TRANSITION_RATE. The unit stays in the commanded operating state until an OPERATION command or RUN pin voltage instructs the device to change to another state. Execution of margin commands is delayed until any on-going TON_RISE or TOFF_FALL output sequencing is completed. Margin values are affected by AVP function, if enabled. Margin operations that ignore faults are not supported by the LTC3882-1. Supported Values: VALUE MEANING 0xA8 Margin high. 0x98 Margin low. 0x80 On (VOUT back to nominal even if bit 3 of ON_OFF_CONFIG is not set). 0x40* Soft off (with sequencing). 0x00* Immediate off (no sequencing). *Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set. Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored. This command has one data byte. MFR_RESET This command provides a means to reset the LTC3882-1 from the serial bus. This forces the LTC3882-1 to turn off both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of both PWM channels, if enabled. This write-only command has no data bytes. 74 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (PWM Configuration) PWM Configuration COMMAND NAME CMD CODE DESCRIPTION FREQUENCY_SWITCH 0x33 PWM frequency control. R/W Word N L11 MFR_PWM_CONFIG_LTC3882-1 0xF5 LTC3882-1 PWM configuration common to both channels. R/W Byte N MFR_CHAN_CONFIG_LTC3882-1 0xD0 LTC3882-1 channel-specific configuration. R/W Byte MFR_PWM_MODE_LTC3882-1 0xD4 LTC3882-1 channel-specific PWM mode control. R/W Byte TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE l 500kHz 0xFBE8 Reg l 0x14 Y Reg l 0x1D Y Reg l 0xC8 kHz Related commands MFR_TEMP_1_GAIN_ADJUST, MFR_TEMP_1_OFFSET. FREQUENCY_SWITCH The FREQUENCY_SWITCH command sets the switching frequency of both LTC3882-1 PWM channels in kilohertz. At most only one IC sharing SYNC should be programmed as clock master. See bit 4 in MFR_CONFIG_ALL_LTC3882-1. FREQUENCY_SWITCH value will determine the free-running frequency of PWM operation if an expected external clock source is not present or the bussed SYNC line becomes stuck due an external fault or conflict. Both PWM channels must be turned off by the RUNn pins, OPERATION command, or their combination, to process this command. If this command is sent while either PWM controller is operating, the LTC3882-1 will NACK the command byte, ignore the command and its data, and assert a BUSY fault. A PLL Unlocked status may be reported after changing the value of this command until the new frequency is established. Supported Frequencies: VALUE PWM FREQUENCY (TYPICAL) 0x0A71 1.25MHz 0x03E8 1MHz 0x0384 900kHz 0x02EE 750kHz 0x0258 600kHz 0xFBE8 500kHz 0xFB84 450kHz 0xFB20 400kHz 0xFABC 350kHz 0XFA58 300kHz 0xF3E8 250kHz 0x0000 External SYNC Only This command has two data bytes in Linear_5s_11s format. 38821f For more information www.linear.com/LTC3882-1 75 LTC3882-1 PMBus COMMAND DETAILS (PWM Configuration) MFR_PWM_CONFIG_LTC3882-1 The MFR_PWM_CONFIG_LTC3882-1 command controls PWM-related clocking for the LTC3882-1. Both PWM channels must be turned off by the RUNn pins, OPERATION command, or their combination, to process this command. If this command is sent while either PWM controller is operating, the LTC3882-1 will NACK the command byte, ignore the command and its data, and assert a BUSY fault. Supported Values: BIT MEANING 7 (Reserved, must write as 0). 6 (Reserved, must write as 0). 5 (Reserved). 4 SHARE_CLK configuration: 0: SHARE_CLK continuously enabled once VINSNS VIN_ON after initialization. 1: SHARE_CLK always forced low if VINSNS VIN_OFF, then held low until VINSNS VIN_ON. 3 2:0 (Reserved). Phase Channel 0 Channel 1 Maximum Duty Cycle 111b 135 315 87.5% 110b 90 270 101b 45 225 100b 0 180 011b 120 300 010b 60 240 001b 0 180 000b 0 120 Value 83.3% Phase is expressed from the falling edge of SYNC to the falling edge of PWM. This command has one data byte. 76 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (PWM Configuration) MFR_CHAN_CONFIG_LTC3882-1 The MFR_CHAN_CONFIG_LTC3882-1 command provides per-channel configuration common to multiple LTC PMBus products. Bit Definitions: BIT MEANING 7:5 (Reserved). 4 RUN pin control: 0: When the channel is commanded off, the associated RUN pin is pulsed low for TOFF_DELAY + TOFF_FALL + 136ms (or MFR_RESTART_DELAY, if longer) regardless of the state of bit 3. 1: RUN pin is not pulsed low if channel is commanded off. 3 Short cycle control: 0: No special control. Device attempts to follow on/off commands exactly as issued. 1: Output is immediately disabled if commanded back on while waiting for TOFF_DELAY or TOFF_FALL to expire. A minimum off time of 120ms is then enforced before the channel is turned back on. Additional delay will apply if bit 4 is clear. 2 SHARE_CLK output control: 0: No special control. 1: Output disabled if SHARE_CLK is held low. 1 (Reserved, must write as 0). 0 MFR_RETRY_DELAY control: 0: Output decay to 12.5% of programmed value required for retry after ANY action that turns off the rail. 1: Output decay not required for retry. This command has one data byte. 38821f For more information www.linear.com/LTC3882-1 77 LTC3882-1 PMBus COMMAND DETAILS (PWM Configuration) MFR_PWM_MODE_LTC3882-1 The MFR_PWM_MODE_LTC3882-1 command sets important PWM controls for each channel. The addressed channel(s) must be turned off by its RUN pin, OPERATION command, or their combination, when this command is issued. Otherwise the LTC3882-1 will NACK the command byte, ignore the command and its data, and assert a BUSY fault. When bit 5 is cleared, the LTC3882-1 computes temperature in C from VBE measured by the ADC at the TSNSn pin as T = (G * VBE * q/(K * ln(16))) - 273.15 + O When bit 5 is set, the LTC3882-1 computes temperature in C from TSNSn voltage measured by the ADC as T = (G * (1.35 - VTSNSn + O)/4.3e-3) + 25 For both equations, G = MFR_TEMP_1_GAIN * 2-14, and O = MFR_TEMP_1_OFFSET Supported Values: BIT 7 MEANING Output voltage range select: 0: Maximum VOUT = 5.25V. 1: Maximum VOUT = 2.65V. 6* Enable VOUT servo. 5 External temperature sense: 0: VBE measurement. 1: Direct voltage measurement. 4:3 BOOST refresh width: 11b: 250ns 10b: 125ns 01b: 50ns 00b: 25ns 2 (Reserved). 1 PWM control protocol: 0: 3-State PWM output. 1: 3-State PWM output with no DCM (including soft-start) or hardware ROC response (including OV). 0 PWM mode: 0: Forced continuous inductor current. 1: Discontinuous inductor current. *This bit is ignored (servo disabled) if MFR_VOUT_AVP for this channel is programmed to a value greater than 0.0%. This command has one data byte. 78 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Input Voltage and Limits) Input Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION VIN_ON 0x35 Minimum input voltage to begin power conversion. R/W Word N L11 V l 6.5V 0xCB40 VIN_OFF 0x36 Decreasing input voltage at which power conversion stops. R/W Word N L11 V l 6.0V 0xCB00 VIN_OV_FAULT_LIMIT 0x55 VIN overvoltage fault limit. R/W Word N L11 V l 15.5V 0xD3E0 VIN_UV_WARN_LIMIT 0x58 VIN undervoltage warning limit. R/W Word N L11 V l 6.3V 0xCB26 TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE Related commands: STATUS_INPUT, SMBALERT_MASK, READ_VIN, VIN_OV_FAULT_RESPONSE VIN_ON The VIN_ON command sets the input voltage, in volts, required to start power conversion. This command has two data bytes in Linear_5s_11s format. VIN_OFF The VIN_OFF command sets the minimum input voltage, in volts, at which power conversion stops. This command has two data bytes in Linear_5s_11s format. VIN_OV_FAULT_LIMIT The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes an input overvoltage fault. This command has two data bytes in Linear_5s_11s format. VIN_UV_WARN_LIMIT The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input undervoltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON command and the unit has been enabled. If the VIN_UV_WARN_LIMIT is then exceeded, the device: * Sets the INPUT Bit in the STATUS_WORD * Sets the VIN Undervoltage Warning Bit in the STATUS_INPUT Command * Notifies the Host by Asserting ALERT, Unless Masked 38821f For more information www.linear.com/LTC3882-1 79 LTC3882-1 PMBus COMMAND DETAILS (Output Voltage and Limits) Output Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE VOUT_MODE 0x20 Output voltage format and exponent. R Byte Y Reg VOUT_COMMAND 0x21 Nominal VOUT value. R/W Word Y L16 V l 1.0V 0x1000 MFR_VOUT_MAX 0xA5 Maximum value of any VOUT-related command. R Word Y L16 V l 5.6V 0x599A VOUT_MAX 0x24 R/W Word Y L16 V l 5.5V 0x5800 MFR_VOUT_AVP 0xD3 Specify VOUT load line. R/W Word Y L11 % l 0% 0x8000 VOUT_MARGIN_HIGH 0x25 VOUT at high margin, must be greater than VOUT_COMMAND. R/W Word Y L16 V l 1.05V 0x10CD VOUT_MARGIN_LOW 0x26 VOUT at low margin, must be less than VOUT_COMMAND. R/W Word Y L16 V l 0.95V 0x0F33 VOUT_OV_FAULT_LIMIT 0x40 VOUT overvoltage fault limit. R/W Word Y L16 V l 1.1V 0x119A VOUT_OV_WARN_LIMIT 0x42 VOUT overvoltage warning limit. R/W Word Y L16 V l 1.075V 0x1133 VOUT_UV_WARN_LIMIT 0x43 VOUT undervoltage warning limit. R/W Word Y L16 V l 0.925V 0x0ECD VOUT_UV_FAULT_LIMIT 0x44 VOUT undervoltage fault limit. R/W Word Y L16 V l 0.9V 0x0E66 Maximum VOUT that can be set by any command, including margin. DATA PAGED FORMAT UNITS NVM DEFAULT VALUE 2-12 0x14 Related commands: OPERATION, STATUS_WORD, STATUS_VOUT, SMBALERT_MASK, READ_VOUT, MFR_VOUT_PEAK, READ_POUT, VOUT_OV_FAULT_ RESPONSE, VOUT_UV_FAULT_RESPONSE VOUT_MODE The VOUT_MODE command gives the format used by the LTC3882-1 for output voltage related commands. Only Linear Mode is supported, with a mantissa expressed in microvolts. Sending the VOUT_MODE command to the LTC3882-1 using a write protocol will result in a CML fault. This read-only command has one data byte. VOUT_COMMAND The VOUT_COMMAND is used to set the output voltage in volts (no load value if AVP is enabled). Execution of this command is delayed until any on-going TON_RISE or TOFF_FALL output sequencing is completed, otherwise the output voltage moves to a new value at VOUT_TRANSITION_RATE. This command has two data bytes in Linear_16u format. MFR_VOUT_MAX The MFR_VOUT_MAX command returns the maximum value, in volts, allowed for any VOUT-related command, including VOUT_OV_FAULT_LIMIT. This value represents the maximum regulated voltage the selected channel could be capable of producing. This read-only command has two data bytes in Linear_16u format. 80 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Output Voltage and Limits) VOUT_MAX The VOUT_MAX command sets an upper limit, in volts, on the allowed value of any command that sets the output voltage, including VOUT_MARGIN_HIGH. Setting VOUT_MAX to a value greater than MFR_VOUT_MAX will result in a CML fault and VOUT_MAX will be set to the value of MFR_VOUT_MAX. A VOUT_MAX warning may also be generated if VOUT_MAX is set above 5.5V in output range 0 or above 2.75V in range 1. This command ensures that any combination of commands attempting to set VOUT above VOUT_MAX will result in a warning with the output clamped at VOUT_MAX. When a VOUT_MAX warning occurs, the device takes the following actions: * Sets The Offending Command Value to the Voltage Specified by VOUT_MAX * Sets the VOUT Bit in the STATUS_WORD * Sets the VOUT_MAX Warning Bit in the STATUS_VOUT Command * Notifies the Host by Asserting ALERT, Unless Masked This command has two data bytes in Linear_16u format. MFR_VOUT_AVP The MFR_VOUT_AVP command sets the change in output voltage, in percent, for a full-scale change in output current. MFR_VOUT_AVP can be used for active voltage positioning (AVP) requirements or passive current sharing schemes. The LTC3882-1 interprets the IOUT_OC_WARN_LIMIT value as full-scale current for AVP. If MFR_VOUT_AVP is nonzero, VOUT_COMMAND sets the maximum, no-load output voltage and servo mode for that channel is automatically disabled. Setting MFR_VOUT_AVP to 0.0% automatically disables the AVP function. Refer to the Applications Information section for additional details on range and resolution when using MFR_VOUT_AVP. This command has two data bytes in Linear_5s_11s format. VOUT_MARGIN_HIGH The VOUT_MARGIN_HIGH command programs the output voltage, in volts, to be produced when Margin High is set with the OPERATION command (no load value if AVP is enabled). The value must be greater than VOUT_ COMMAND. This command has two data bytes in Linear_16u format. VOUT_MARGIN_LOW The VOUT_MARGIN_LOW command programs the output voltage, in volts, to be produced when Margin Low is set by the OPERATION command (no load value if AVP is enabled). The value must be less than VOUT_COMMAND. This command has two data bytes in Linear_16u format. VOUT_OV_FAULT_LIMIT The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor at the VSENSE pins, in volts, which causes an output overvoltage fault. If VOUT_OV_FAULT_LIMIT is modified while the channel is on, 10ms should be allowed for the new value to take effect. Modifying VOUT during that time can result an erroneous OV fault. The LTC3882-1 sets MFR_COMMON bits[6:5] low while it establishes the new VOUT_OV_FAULT_LIMIT value. This command has two data bytes in Linear_16u format. 38821f For more information www.linear.com/LTC3882-1 81 LTC3882-1 PMBus COMMAND DETAILS (Output Voltage and Limits) VOUT_OV_WARN_LIMIT The VOUT_OV_WARN_LIMIT command sets the value, in volts, of the output voltage measured by the ADC at the VSENSE pins that causes an output overvoltage warning. If the VOUT_OV_WARN_LIMIT is exceeded, the device: * Sets the VOUT Bit in the STATUS_WORD * Sets the VOUT Overvoltage Warning Bit in the STATUS_VOUT Command * Notifies the Host by Asserting ALERT, Unless Masked This command has two data bytes in Linear_16u format. VOUT_UV_WARN_LIMIT The VOUT_UV_WARN_LIMIT command sets the value, in volts, of the output voltage measured by the ADC at the VSENSE pins that causes an output undervoltage warning. If the VOUT_UV_WARN_LIMIT is exceeded, the device: * Sets the VOUT Bit in the STATUS_WORD * Sets the VOUT Undervoltage Warning Bit in the STATUS_VOUT Command * Notifies the Host by Asserting ALERT, Unless Masked This command has two data bytes in Linear_16u format. VOUT_UV_FAULT_LIMIT The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage measured by the UV supervisor at the VSENSE pins, in volts, which causes an output undervoltage fault. This command has two data bytes in Linear_16u format. 82 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Output Current and Limits) Output Current and Limits COMMAND NAME CMD CODE DESCRIPTION IOUT_CAL_GAIN 0x38 Ratio of ISENSE voltage to sensed current. R/W Word Y L11 m l 0.63m 0xB285 MFR_IOUT_CAL_GAIN_TC 0xF6 Output current sense element temperature coefficient. R/W Word Y CF ppm/C l 3900ppm/C 0x0F3C IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A l 29.75A 0xDBB8 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A l 20.0A 0xDA80 TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE Related commands: STATUS_IOUT, SMBALERT_MASK, READ_IOUT, MFR_IOUT_PEAK, READ_POUT, IOUT_OC_FAULT_RESPONSE, MFR_VOUT_AVP IOUT_CAL_GAIN The IOUT_CAL_GAIN command is used to set the resistance value of the output current sense element in milliohms. This command has two data bytes in Linear_5s_11s format. MFR_IOUT_CAL_GAIN_TC The MFR_IOUT_CAL_GAIN_TC command sets the temperature coefficient of the output current sense element in ppm/C. Effective sense resistance, in milliohms, is computed by the LTC3882-1 as RSENSE = IOUT_CAL_GAIN * (1 + 1E-6 * MFR_IOUT_CAL_GAIN_TC * (READ_TEMPERATURE_1 - 27)) This command has two data bytes representing a 2's compliment integer. IOUT_OC_FAULT_LIMIT The IOUT_OC_FAULT_LIMIT command sets the value of the instantaneous peak output current, in amperes, which will cause the OC supervisor to detect an output overcurrent fault. The LTC3882-1 uses the computed effective sense resistance and the voltage across the ISENSE inputs to determine the output current. The programmed limit voltage is rounded to the nearest 0.4mV in a range from 0.0mV to 80.0mV. Output overcurrent faults are ignored during TON_RISE and TOFF_FALL output sequencing. This command has two data bytes in Linear_5s_11s format. IOUT_OC_WARN_LIMIT The IOUT_OC_WARN_LIMIT command sets the value of the output current measured by the ADC, in amperes, that causes an output overcurrent warning. To provide meaningful responses, this value should be set below IOUT_OC_FAULT_LIMIT minus 1/2 of the maximum anticipated ripple current. If the IOUT_OC_WARN_LIMIT is exceeded, the device: * Sets the IOUT Bit in the STATUS_WORD * Sets the IOUT Overcurrent Warning Bit in the STATUS_IOUT Command * Notifies the Host by Asserting ALERT, Unless Masked Output overcurrent warnings are ignored during TON_RISE and TOFF_FALL output sequencing. This command has two data bytes in Linear_5s_11s format. 38821f For more information www.linear.com/LTC3882-1 83 LTC3882-1 PMBus COMMAND DETAILS (Output Timing, Delays, and Ramping) Output Timing, Delays, and Ramping COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE MFR_RESTART_DELAY 0xDC Minimum time RUN pin is held low by the LTC3882-1. R/W Word Y L11 ms l 500ms 0xFBE8 TON_DELAY 0x60 Delay from RUN pin or OPERATION on command to TON_RISE ramp start. R/W Word Y L11 ms l 0.0ms 0x8000 TON_RISE 0x61 Time for VOUT to rise from 0V to VOUT_COMMAND after TON_DELAY. R/W Word Y L11 ms l 8.0ms 0xD200 TON_MAX_FAULT_LIMIT 0x62 Maximum time for VOUT to rise above VOUT_UV_FAULT_LIMIT after TON_DELAY. R/W Word Y L11 ms l 10.0ms 0xD280 VOUT_TRANSITION_RATE 0x27 VOUT slew rate for programmed output changes. R/W Word Y L11 V/ms l 0.25V/ms 0xAA00 TOFF_DELAY 0x64 Delay from RUN pin or OPERATION off command to TOFF_FALL ramp start. R/W Word Y L11 ms l 0.0ms 0x8000 TOFF_FALL 0x65 Time for VOUT to fall to 0V from VOUT_COMMAND after TOFF_DELAY. R/W Word Y L11 ms l 8.0ms 0xD200 TOFF_MAX_WARN_LIMIT 0x66 R/W Word Maximum time for VOUT to decay below 12.5% of VOUT_COMMAND after TOFF_FALL completes. Y L11 ms l 150ms 0xF258 Related commands: MFR_RETRY_DELAY, STATUS_VOUT, SMBALERT_MASK, TON_MAX_FAULT_RESPONSE, MFR_CHAN_CONFIG_LTC3882-1, MFR_PWM_MODE_LTC3882-1 These commands can be used to establish required on/off sequencing for any number of system power supply rails. MFR_RESTART_DELAY The MFR_RESTART DELAY command specifies the minimum PWM off time (RUN low) in milliseconds. The LTC3882-1 will actively hold its RUN pin low for this length of time if a falling RUN edge is detected. After this delay, a standard start-up sequence can be initiated. A minimum of TOFF_DELAY + TOFF_FALL + 136ms is recommended for this command value. Valid value range is 136ms to 65.52 seconds. The LTC3882-1 uses a resolution of 16ms for this command and will not produce delays outside of this range. This command has two data bytes in Linear_5s_11s format. TON_DELAY The TON_DELAY command sets the delay, in milliseconds, between a start condition and the beginning of the output voltage rise. Values from 0ms to 83 seconds are considered valid, and the LTC3882-1 will not produce delays outside of this range. This command has two data bytes in Linear_5s_11s format. TON_RISE The TON_RISE command sets the desired time, in milliseconds, from the point the output starts to rise until it enters the regulation band. Values from 0 seconds to 1.3 seconds are considered valid, and the LTC3882-1 will not produce rise times outside of this range. Values of TON_RISE less than 0.25ms or resulting slopes greater than 4V/ms will result in an output step to the commanded voltage limited only by PWM analog loop response. This command has two data bytes in Linear_5s_11s format. 84 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Output Timing, Delays and Ramping) TON_MAX_FAULT_LIMIT The TON_MAX_FAULT_LIMIT command sets the maximum time, in milliseconds, the unit is allowed from the beginning of TON_RISE to power up the output without passing VOUT_UV_FAULT_LIMIT. A value of 0ms means there is no limit and the unit can attempt to bring up the output voltage indefinitely. The maximum allowed TON_MAX is 8 seconds. This command has two data bytes in Linear_5s_11s format. VOUT_TRANSITION_RATE The VOUT_TRANSITION_RATE command sets the rate at which the output voltage changes, in volts per millisecond (or mV/s), in response to a VOUT_COMMAND or OPERATION (margin) command. This rate of change does not apply to operations that fully turn the PWM channel on or off. Values from 1mV/ms to 4V/ms are considered valid. The LTC3882-1 will not produce VOUT transitions slower than 1mV/ms, and values exceeding 4V/ms cause the device to transition the output as quickly as possible, limited only by PWM analog loop response. This command has two data bytes in Linear_5s_11s format. TOFF_DELAY The TOFF_DELAY command sets the delay, in milliseconds, between a stop condition and the beginning of the output voltage fall. Values from 0s to 16s are considered valid. This command has two data bytes in Linear_5s_11s format. TOFF_FALL The TOFF_FALL command sets the time, in milliseconds, from the end of TOFF_DELAY until the output voltage is commanded fully to zero. The part attempts to linearly reduce the commanded output voltage to zero during TOFF_FALL. At the end of this period, the PWM output is disabled. The part will maintain its programmed PWM operating mode during TOFF_FALL. Using continuous conduction mode will produce a well defined VOUT ramp off but may result in negative output current. The minimum supported fall time is 0.25ms, or any value that results in a rate of fall exceeding 4V/ms. Programmed values less than this will result in a commanded 0.25ms ramp, possibly limited by PWM analog loop response. Maximum fall time is 1.3 seconds. In discontinuous conduction mode, the controller will not be able to draw current from the load and fall time will be set by output capacitance and load current. This command has two data bytes in Linear_5s_11s format. TOFF_MAX_WARN_LIMIT The TOFF_MAX_WARN_LIMIT command sets the time, in milliseconds, the unit is allotted to have the output off after TOFF_FALL completes before a warning is issued. The output is considered off when VOUT is less than 12.5% of the VOUT_COMMAND value. A data value of 0ms means there is no limit and the unit can attempt to turn the output off indefinitely. There is also no limit enforced if bit 0 of MFR_CHAN_CONFIG_LTC3882-1 is set. This command has two data bytes in Linear_5s_11s format. 38821f For more information www.linear.com/LTC3882-1 85 LTC3882-1 PMBus COMMAND DETAILS (External Temperature and Limits) External Temperature and Limits COMMAND NAME CMD CODE DESCRIPTION MFR_TEMP_1_GAIN 0xF8 Set slope for external temperature calculations. R/W Word Y CF MFR_TEMP_1_OFFSET 0xF9 Offset addend for external temperature calculations. R/W Word Y L11 OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE l 1.0 0x4000 C or V l 0.0 0x8000 L11 C l 100.0C 0xEB20 Y L11 C l 85.0C 0xEAA8 Y L11 C l -40.0C 0xE580 Related commands: STATUS_TEMPERATURE, SMBALERT_MASK, MFR_TEMPERATURE1_PEAK, OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, STATUS_MFR_SPECIFIC, READ_TEMPERATURE_2, MFR_OT_FAULT_RESPONSE, MFR_PWM_MODE_LTC3882-1 MFR_TEMP_1_GAIN The MFR_TEMP_1_GAIN command sets the slope used in the calculation of external temperature to account for nonidealities in the element and remote sensing errors, if any. Refer to the MFR_PWM_MODE_LTC3882-1 command for equation details. This command has two data bytes representing a 2's complement integer. MFR_TEMP_1_OFFSET The MFR_TEMP_1_OFFSET command sets the offset used in the calculation of external temperature to account for non-idealities in the element and remote sensing errors, if any. The unit of measure for MFR_TEMP1_OFFSET depends on bit 5 of MFR_PWM_MODE. MFR_TEMP1_ OFFSET is expressed volts if this bit is set and in C otherwise. Refer to the MFR_PWM_MODE_ LTC3882-1 command for equation details. This command has two data bytes in Linear_5s_11s format. OT_FAULT_LIMIT The OT_FAULT_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an overtemperature fault. This command has two data bytes in Linear_5s_11s format. OT_WARN_LIMIT The OT_WARN_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an overtemperature warning. If the OT_WARN_LIMIT is exceeded, the device: * Sets the TEMPERATURE Bit in the STATUS_BYTE * Sets the Overtemperature Warning Bit in the STATUS_TEMPERATURE Command * Notifies the Host by Asserting ALERT, Unless Masked This command has two data bytes in Linear_5s_11s format. 86 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (External Temperature Limits) UT_FAULT_LIMIT The UT_FAULT_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an undertemperature fault. This command has two data bytes in Linear_5s_11s format. Status Reporting COMMAND NAME CMD CODE DESCRIPTION STATUS_BYTE 0x78 One-byte channel status summary. R/W Byte Y Reg STATUS_WORD 0x79 Two-byte channel status summary. R/W Word Y Reg STATUS_VOUT 0x7A VOUT fault and warning status. R/W Byte Y Reg TYPE DATA PAGED FORMAT STATUS_IOUT 0x7B IOUT fault and warning status. R/W Byte Y Reg STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg STATUS_TEMPERATURE 0x7D External temperature fault and warning status. R/W Byte Y Reg STATUS_CML 0x7E Communication, memory and logic fault and warning status. R/W Byte N Reg STATUS_MFR_SPECIFIC 0x80 LTC3882-1-specific status. R/W Byte Y Reg MFR_PADS_LTC3882-1 0xE5 State of selected LTC3882-1 pads. R Word N Reg MFR_COMMON 0xEF LTC-generic device status reporting. R Byte N Reg CLEAR_FAULTS 0x03 Clear all set fault bits. Send Byte N UNITS NVM DEFAULT VALUE Refer to Figure 2 for a graphical depiction of these register contents and their relationships. STATUS_BYTE The STATUS_BYTE command returns a one-byte summary of the most critical faults. STATUS_BYTE Message Contents: BIT STATUS BIT NAME MEANING 7* BUSY 6 OFF 5 VOUT_OV An output overvoltage fault has occurred. 4 IOUT_OC An output overcurrent fault has occurred. 3 VIN_UV Not supported (LTC3882-1 returns 0). 2 TEMPERATURE 1 CML 0* NONE OF THE ABOVE A fault was declared because the LTC3882-1 was unable to respond. This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. A temperature fault or warning has occurred. A communications, memory or logic fault has occurred. A fault Not listed in bits[7:1] has occurred. *ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_FAULTS command. This command has one data byte. 38821f For more information www.linear.com/LTC3882-1 87 LTC3882-1 PMBus COMMAND DETAILS (Status Reporting) STATUS_WORD The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the STATUS_WORD is the same as the STATUS_BYTE command. STATUS_WORD High Byte Message Contents: BIT STATUS BIT NAME 15 VOUT An output voltage fault or warning has occurred. MEANING 14 IOUT An output current fault or warning has occurred. 13 INPUT An input voltage fault or warning has occurred. 12 MFR_SPECIFIC A fault or warning specific to the LTC3882-1 has occurred. 11 POWER_GOOD# The POWER_GOOD state is false if this bit is set. 10 FANS Not supported (LTC3882-1 returns 0). 9 OTHER Not supported (LTC3882-1 returns 0). 8 UNKNOWN Not supported (LTC3882-1 returns 0). This command has two data bytes. STATUS_VOUT The STATUS_VOUT command returns one byte of VOUT status information. STATUS_VOUT Message Contents: BIT MEANING 7 VOUT overvoltage fault. 6 VOUT overvoltage warning. 5 VOUT undervoltage warning. 4 VOUT undervoltage fault. 3 VOUT_MAX warning. 2 TON_MAX fault. 1 TOFF_MAX warning. 0 Not supported by the LTC3882-1 (returns 0). ALERT can be asserted if any of bits[7:1] are set. These may be cleared by writing a 1 to their bit position in STATUS_VOUT, in lieu of a CLEAR_FAULTS command. This command has one data byte. 88 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Status Reporting) STATUS_IOUT The STATUS_IOUT command returns one byte of IOUT status information. STATUS_IOUT Message Contents: BIT MEANING 7 IOUT overcurrent fault. 6 Not supported (LTC3882-1 returns 0). 5 IOUT overcurrent warning. 4:0 Not supported (LTC3882-1 returns 0). ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_IOUT, in lieu of a CLEAR_FAULTS command. This command has one data byte. STATUS_INPUT The STATUS_INPUT command returns one byte of VIN (VINSNS) status information. STATUS_INPUT Message Contents: BIT MEANING 7 VIN overvoltage fault. 6 Not supported (LTC3882-1 returns 0). 5 VIN undervoltage warning. 4 Not supported (LTC3882-1 returns 0). 3 2:0 Unit off for insufficient VIN. Not supported (LTC3882-1 returns 0). ALERT can be asserted if bit 7 is set. Bit 7 may be cleared by writing it to a 1, in lieu of a CLEAR_FAULTS command. This command has one data byte. STATUS_TEMPERATURE The STATUS_TEMPERATURE command returns one byte of sensed external temperature status information. STATUS_TEMPERATURE Message Contents: BIT MEANING 7 External overtemperature fault. 6 External overtemperature warning. 5 Not supported (LTC3882-1 returns 0). 4 External undertemperature fault. 3:0 Not supported (LTC3882-1 returns 0). ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_TEMPERATURE, in lieu of a CLEAR_FAULTS command. This command has one data byte. 38821f For more information www.linear.com/LTC3882-1 89 LTC3882-1 PMBus COMMAND DETAILS (Status Reporting) STATUS_CML The STATUS_CML command returns one byte of status information on received commands, internal memory and logic. STATUS_CML Message Contents: BIT MEANING 7 Invalid or unsupported command received. 6 Invalid or unsupported data received. 5 Packet error check failed. 4 Memory fault detected. 3 Processor fault detected. 2 Reserved (LTC3882-1 returns 0). 1 Other communication fault. 0 Other memory or logic fault. ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_CML, in lieu of a CLEAR_FAULTS command. This command has one data byte. STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC command returns one byte with LTC3882-1 specific status information. STATUS_MFR_SPECIFIC Message Contents: BIT MEANING 7 Internal temperature fault (>160C). 6 Internal temperature warning (>130C). 5 EEPROM CRC error. 4 Internal PLL unlocked. 3 Fault log present. 2 Not supported (LTC3882-1 returns 0). 1 Output short cycled. 0 FAULT low. If any supported bits are set, the MFR bit in the STATUS_WORD will be set and ALERT may be asserted. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_MFR_SPECIFIC, in lieu of a CLEAR_FAULTS command. This command has one data byte. 90 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Status Reporting) MFR_PADS_LTC3882-1 The MFR_PADS_LTC3882-1 command provides status of the LTC3882-1 digital I/O and control pins, in addition to general output voltage conditions. MFR_PADS_LTC3882-1 Message Contents: BIT MEANING 15 Channel 1 is a slave. 14 Channel 0 is a slave. 13:12 Not supported (LTC3882-1 returns 0). 11 ADC results for IOUT may be invalid. 10 SYNC output disabled externally. 9 Channel 1 POWER_GOOD (normally returns 1 if slave). 8 Channel 0 POWER_GOOD (normally returns 1 if slave). 7 LTC3882-1 forcing RUN1 low. 6 LTC3882-1 forcing RUN0 low. 5 RUN1 pin state. 4 RUN0 pin state. 3 LTC3882-1 forcing FAULT1 low. 2 LTC3882-1 forcing FAULT0 low. 1 FAULT1 pin state. 0 FAULT0 pin state. This read-only command has two data bytes. MFR_COMMON The MFR_COMMON command contains status bits that are common to multiple LTC PMBus products. MFR_COMMON Message Contents: BIT MEANING 7 LTC3882-1 not forcing ALERT low. 6 LTC3882-1 not BUSY. 5 LTC3882-1 calculations not pending. 4 LTC3882-1 output not in transition. 3 LTC3882-1 EEPROM initialized. 2 Not supported (LTC3882-1 returns 0). 1 SHARE_CLK timeout. 0 Not supported (LTC3882-1 returns 0). This read-only command has one data byte. 38821f For more information www.linear.com/LTC3882-1 91 LTC3882-1 PMBus COMMAND DETAILS (Status Reporting) CLEAR_FAULTS The CLEAR_FAULTS command clears any fault bits that have been set and deasserts (releases) the ALERT pin. This command clears all bits in all status commands simultaneously. CLEAR_FAULTS does not cause a channel that has latched off for a fault condition to restart. Channels that are latched off for a fault condition are restarted when the output is commanded to turn off and then on through the OPERATION command or RUN pins, or IC supply power is cycled. If a fault is still present when CLEAR_FAULTS is commanded, that fault bit will immediately be set and ALERT again asserted low. This write-only command has no data bytes. Telemetry COMMAND NAME CMD CODE DESCRIPTION READ_VIN 0x88 MFR_VIN_PEAK READ_VOUT MFR_VOUT_PEAK TYPE Measured VIN. DATA PAGED FORMAT UNITS NVM R Word N L11 V 0xDE Maximum VIN measurement since last MFR_CLEAR_PEAKS. R Word N L11 V 0x8B Measured VOUT. 0xDD Maximum VOUT measurement since last MFR_CLEAR_PEAKS. R Word Y L16 V R Word Y L16 V READ_IOUT 0x8C Measured IOUT. R Word Y L11 A MFR_IOUT_PEAK 0xD7 Maximum IOUT measurement since last MFR_CLEAR_PEAKS. R Word Y L11 A READ_POUT 0x96 Calculated output power. R Word Y L11 W READ_TEMPERATURE_1 0x8D Measured external temperature. R Word Y L11 C MFR_TEMPERATURE_1_PEAK 0xDF Maximum external temperature measurement since last MFR_CLEAR_PEAKS. R Word Y L11 C READ_TEMPERATURE_2 0x8E Measured internal temperature. R Word N L11 C MFR_TEMPERATURE_2_PEAK 0xF4 Maximum internal temperature measurement since last MFR_CLEAR_PEAKS. R Word N L11 C READ_DUTY_CYCLE 0x94 Measured commanded PWM duty cycle. R Word Y L11 % READ_FREQUENCY 0x95 Measured PWM input clock frequency. R Word Y L11 kHz MFR_CLEAR_PEAKS 0xE3 Clear all peak values. Send Byte N DEFAULT VALUE Related commands: IOUT_CAL_GAIN, MFR_IOUT_CAL_GAIN_TC, MFR_PWM_MODE_LTC3882-1 READ_VIN The READ_VIN command returns the input voltage measured between VINSNS and GND in volts. This read-only command has two data bytes in Linear_5s_11s format. 92 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Telemetry) MFR_VIN_PEAK The MFR_VIN_PEAK command reports the highest voltage, in volts, measured for READ_VIN. This peak value can be reset by a MFR_CLEAR_PEAKS command. This read-only command has two data bytes in Linear_5s_11s format. READ_VOUT The READ_VOUT command returns the output voltage measured at the VSENSE pins in volts. This read-only command has two data bytes in Linear_16u format. MFR_VOUT_PEAK The MFR_VOUT_PEAK command reports the highest voltage, in volts, measured for READ_VOUT. This peak value can be reset by a MFR_CLEAR_PEAKS command. This read-only command has two data bytes in Linear_16u format. READ_IOUT The READ_IOUT command returns the output current in amperes. This value is computed from: * The differential voltage measured across the ISENSE pins * The IOUT_CAL_GAIN value * The MFR_IOUT_CAL_GAIN_TC value * The READ_TEMPERATURE_1 value * The MFR_TEMP_1_GAIN value * The MFR_TEMP_1_OFFSET value This read-only command has two data bytes in Linear_5s_11s format. MFR_IOUT_PEAK The MFR_IOUT_PEAK command reports the highest current, in amperes, calculated for READ_IOUT. This peak value can be reset by a MFR_CLEAR_PEAKS command. This read-only command has two data bytes in Linear_5s_11s format. READ_POUT The READ_POUT command reports the output power in watts. The value is calculated from the product of the most recent correlated output voltage and current readings. This read-only command has two data bytes in Linear_5s_11s format. 38821f For more information www.linear.com/LTC3882-1 93 LTC3882-1 PMBus COMMAND DETAILS (Telemetry) READ_TEMPERATURE_1 The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element. This read-only command has two data bytes in Linear_5s_11s format. MFR_TEMPERATURE_1_PEAK The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, calculated for READ_TEMPERATURE_1. This peak value can be reset by a MFR_CLEAR_PEAKS command. This read-only command has two data bytes in Linear_5s_11s format. READ_TEMPERATURE_2 The READ_TEMPERATURE_2 command returns the LTC3882-1 internal temperature in degrees Celsius. This read-only command has two data bytes in Linear_5s_11s format. MFR_TEMPERATURE_2_PEAK The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, calculated for READ_TEMPERATURE_2. This peak value can be reset by a MFR_CLEAR_PEAKS command. This read-only command has two data bytes in Linear_5s_11s format. READ_DUTY_CYCLE The READ_DUTY_CYCLE command returns the duty cycle of the PWM control in percent. This will not be the exact duty cycle of the PWM switch node due to efficiency losses in the power stage and current consumption of the LTC3882-1 itself. This read-only command has two data bytes in Linear_5s_11s format. READ_FREQUENCY The READ_FREQUENCY command returns the switching frequency supplied to the internal PLL in kilohertz, whether derived internally or provided by external clock on the SYNC pin. This may not be the actual PWM output switching frequency during certain exception processing, such as an output overcurrent condition. This read-only command has two data bytes in Linear_5s_11s format. MFR_CLEAR_PEAKS The MFR_CLEAR_PEAKS command resets all stored _PEAK values. The LTC3882-1 determines new peak values after this command is received. This write-only command has no data bytes. 94 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Fault Response and Communication) Fault Response and Communication COMMAND NAME CMD CODE DESCRIPTION VIN_OV_FAULT_RESPONSE 0x56 VIN overvoltage fault response. R/W Byte Y Reg l 0x80 VOUT_OV_FAULT_RESPONSE 0x41 VOUT overvoltage fault response. R/W Byte Y Reg l 0xB8 VOUT_UV_FAULT_RESPONSE 0x45 VOUT undervoltage fault response. R/W Byte Y Reg l 0xB8 IOUT_OC_FAULT_RESPONSE 0x47 Output overcurrent fault response. R/W Byte Y Reg l 0x00 OT_FAULT_RESPONSE 0x50 External overtemperature fault response. R/W Byte Y Reg l 0xB8 UT_FAULT_RESPONSE 0x54 External undertemperature fault response. R/W Byte Y Reg l 0xB8 MFR_OT_FAULT_RESPONSE 0xD6 Internal overtemperature fault response. R/W Byte N Reg l 0xC0 TON_MAX_FAULT_RESPONSE 0x63 R/W Byte Y Reg l 0xB8 MFR_RETRY_DELAY 0xDB Minimum time before retry after a fault. R/W Word N L11 l 350ms 0xFABC SMBALERT_MASK 0x1B Mask ALERT Activity. Block R/W Y Reg l See CMD Details MFR_FAULT_PROPAGATE_ LTC3882-1 0xD2 Configure status propagation via FAULTn pins. R/W Word Y Reg l 0x6993 MFR_FAULT_RESPONSE 0xD5 PWM response when FAULTn pin is low. R/W Byte Y Reg l 0xC0 R Block N Reg Send Byte N Fault response when TON_MAX_FAULT_LIMIT is exceeded. MFR_FAULT_LOG 0xEE MFR_FAULT_LOG_CLEAR 0xEC Clear existing EEPROM fault log. Read fault log data. TYPE DATA PAGED FORMAT UNITS NVM ms DEFAULT VALUE Related commands: STATUS_BYTE, STATUS_WORD, MFR_PADS_LTC3882-1, MFR_RESTART_DELAY, MFR_CHAN_CONFIG_LTC3882-1, MFR_FAULT_ LOG_STORE, CLEAR_FAULTS These commands detail programmable device responses for detected faults beyond the hardware-level actions described in the Operations section. LTC3882-1 hardware-level fault responses cannot be modified. Refer to Table 1 to Table 4 for details of fault log contents. PMBus warning event responses are listed under _WARN_LIMIT command details. VIN_OV_FAULT_RESPONSE The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input overvoltage fault. The format for this command is given in Table 13. The device also: * Sets the INPUT Bit in the STATUS_WORD * Sets the VIN Overvoltage Fault Bit in the STATUS_INPUT Command * Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte. 38821f For more information www.linear.com/LTC3882-1 95 LTC3882-1 PMBus COMMAND DETAILS (Fault Response and Communication) VOUT_OV_FAULT_RESPONSE The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. The format for this command is given in Table 12. The device also: * Sets the VOUT_OV Bit in the STATUS_BYTE * Sets the VOUT Bit in the STATUS_WORD * Sets the VOUT Overvoltage Fault Bit in the STATUS_VOUT Command * Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte. VOUT_UV_FAULT_RESPONSE The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output undervoltage fault. The format for this command is given in Table 12. The device also: * Sets the VOUT Bit in the STATUS_WORD * Sets the VOUT Undervoltage Fault Bit in the STATUS_VOUT Command, * Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte. Table 12. Data Byte Contents for VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE BITS DESCRIPTION [7:6] For all values of bits [7:6], the LTC3882-1: VALUE * Sets the corresponding fault bits in the status commands. * Notifies the host by asserting ALERT, unless masked. The fault, once set, is cleared only when one or more of the following events occurs: * The device receives a CLEAR_FAULTS command. * The corresponding STATUS_VOUT bit is written to a one. * The output is commanded off, then on, by the RUN pin or OPERATION command. * The device receives a RESTORE_USER_ALL command. * The device receives an MFR_RESET command. * IC supply power is cycled. [5:3] [2:0] 96 Retry setting. Delay time. MEANING 00 The LTC3882-1 continues to operate indefinitely with the normal hardware response described in the Operation section. 01 The LTC3882-1 continues operating with the normal hardware response for the delay time specified by bits [2:0]. If the fault is continuously present for the entire delay, the unit then disables the output and does attempt to restart. 10 The LTC3882-1 immediately disables the output and responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. 000-110 The LTC3882-1 does not attempt to restart. The output remains disabled until the fault is cleared, the device is commanded off and then on, or bias power (LTC3882-1 power supply input) is cycled. 111 The LTC3882-1 attempts to restart continuously without limitation with an interval set by MFR_RETRY_DELAY. This response persists until the unit is commanded off, or bias power is removed, or another fault response forces shutdown without retry. xxx Response delay time in 10s increments. This delay time determines how long the fault may have to persist before the controller is disabled, depending on bits [7:6]. Hardware-level response, if any, will occur during this delay. These bits always return zero if bits [7:6] are not set to 0x2. 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Fault Response and Communication) IOUT_OC_FAULT_RESPONSE The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output overcurrent fault. The device also: * Sets the IOUT_OC Bit in the STATUS_BYTE * Sets the IOUT Bit in the STATUS_WORD * Sets the IOUT Overcurrent Fault Bit in the STATUS_IOUT Command * Notifies the Host by Asserting ALERT Output overcurrent faults are ignored during TON_RISE and TOFF_FALL output sequencing. Data Byte Contents for IOUT_OC_FAULT_RESPONSE: BITS [7:6] DESCRIPTION VALUE For all values of bits [7:6], the LTC3882-1: * Sets the corresponding fault bits in the status commands. * Notifies the host by asserting ALERT, unless masked. The fault, once set, is cleared only when one or more of the following events occurs: * The device receives a CLEAR_FAULTS command. * The corresponding STATUS_IOUT bit is written to a one. * The output is commanded off, then on, by the RUN pin or OPERATION command. * The device receives a RESTORE_USER_ALL command. * The device receives an MFR_RESET command. * IC supply power is cycled. [5:3] [2:0] Retry setting. Delay time. MEANING 0x The LTC3882-1 continues to operate indefinitely with the normal hardware response described in the Operation section. 10 The LTC3882-1 continues operating with the normal hardware response for the delay time specified by bits [2:0]. If the fault is continuously present for the entire delay, the unit then disables the output and does not attempt to restart. 11 The LTC3882-1 shuts down (disables the output) and responds according to the retry setting in bits [5:3]. 000-110 The LTC3882-1 does not attempt to restart. The output remains disabled until the fault is cleared, the device is commanded off and then on, or bias power is cycled. 111 The LTC3882-1 attempts to restart continuously without limitation with an interval set by MFR_RETRY_DELAY. This response persists until the unit is commanded off, bias power is removed, or another fault response forces shutdown without retry. xxx Response delay time in 16ms increments. This delay time determines how long the fault may have to persist before the controller is disabled, depending on bits [7:6]. These bits always return zero if bits [7:6] are not set to 0x2. Programming an unsupported IOUT_OC_FAULT_RESPONSE value will generate a CML fault and the command will be ignored. This command has one data byte. 38821f For more information www.linear.com/LTC3882-1 97 LTC3882-1 PMBus COMMAND DETAILS (Fault Response and Communication) OT_FAULT_RESPONSE The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an overtemperature fault. The format for this command is given in Table 13. The device also: * Sets the TEMPERATURE Bit in the STATUS_BYTE * Sets the Overtemperature Fault Bit in the STATUS_TEMPERATURE Command * Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte. UT_FAULT_RESPONSE The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an undertemperature fault. The format for this command is given in Table 13. The device also: * Sets the TEMPERATURE Bit in the STATUS_BYTE * Sets the Undertemperature Fault Bit in the STATUS_TEMPERATURE Command * Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte. MFR_OT_FAULT_RESPONSE The MFR_OT_FAULT_RESPONSE command instructs the device on what action to take in response to an internal overtemperature fault (150C to 160C). The device also: * Sets the MFR Bit in the STATUS_WORD * Sets the Overtemperature Fault Bit in the STATUS_MFR_SPECIFIC Command * Notifies the Host by Asserting ALERT, Unless Masked Supported Values: VALUE MEANING 0xC0 The LTC3882-1 continues to operate indefinitely with the normal hardware response described in the Operation section. 0x80 The LTC3882-1 shuts down immediately and does not attempt to restart. The output remains disabled until the fault is cleared and the unit is commanded off and then on, or bias power (LTC3882-1 power supply input) is cycled. Programming an unsupported MFR_OT_FAULT_RESPONSE value will generate a CML fault and the command will be ignored. This command has one data byte. 98 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Fault Response and Communication) TON_MAX_FAULT_RESPONSE The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX fault. The format for this command is given in Table 13. The device also: * Sets the VOUT Bit in the STATUS_WORD * Sets the TON_MAX_FAULT Bit in the STATUS_VOUT Command * Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte. Table 13. Data Byte Contents for the Following _FAULT_RESPONSE Commands: VIN_OV, OT, UT and TON_MAX BITS [7:6] DESCRIPTION VALUE For all values of bits [7:6], the LTC3882-1: * Sets the corresponding fault bits in the status commands. * Notifies the host by asserting ALERT, unless masked. The fault, once set, is cleared only when one or more of the following events occurs: * The device receives a CLEAR_FAULTS command. * The corresponding fault bit is written to a one. * The output is commanded off, then on, by the RUN pin or OPERATION command. * The device receives a RESTORE_USER_ALL command. * The device receives an MFR_RESET command. * IC supply power is cycled. [5:3] [2:0] Retry setting. Delay time. MEANING 00 The LTC3882-1 continues operating without interruption. 01 Not supported. Writing this value will generate a CML fault. 10 The LTC3882-1 shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. 000-110 The LTC3882-1 does not attempt to restart. The output remains disabled until the fault is cleared, the device is commanded off and then on, or bias power is cycled. 111 The LTC3882-1 attempts to restart continuously without limitation with an interval set by MFR_RETRY_DELAY. This response persists until the unit is commanded off, bias power is removed, or another fault response forces shutdown without retry. xxx Not supported. Values ignored. MFR_RETRY_DELAY The MFR_RETRY_DELAY command sets the time in milliseconds between restart attempts for all retry fault responses. The actual retry delay may be the longer of MFR_RETRY_DELAY or the time required for the output voltage to decay below 12.5% of its programmed value. Decay qualification can be disabled using the MFR_CHAN_CONFIG_LTC3882-1 command. Retry delay starts once the fault is no longer detected by the LTC3882-1 or its FAULT pin is externally released. Legal values run from 120ms to 32.7 seconds. This command has two data bytes in Linear_5s_11s format. 38821f For more information www.linear.com/LTC3882-1 99 LTC3882-1 PMBus COMMAND DETAILS (Fault Response and Communication) SMBALERT_MASK The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they are asserted. Figure 51 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE bits would continue to assert ALERT if set. 1 7 1 1 S SLAVE ADDRESS W A SMBALERT_MASK A COMMAND CODE 8 1 8 8 1 1 MASK BYTE A P 1 STATUS_x A COMMAND CODE 38821 F51 Figure 51. Example of Setting SMBALERT_MASK Figure 52 shows an example of the Block Write - Block Read Process Call protocol used to read back the present state of any supported status register, again without PEC. 1 7 1 1 S SLAVE ADDRESS W A SMBALERT_MASK A COMMAND CODE 1 7 Sr SLAVE ADDRESS 8 1 R 1 8 1 BLOCK COUNT (= 1) A 8 1 STATUS_x A COMMAND CODE 1 8 1 8 A BLOCK COUNT (= 1) A MASK BYTE 1 ... 1 NA P 38821 F52 Figure 52. Example of Reading SMBALERT_MASK SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTC3882-1. Factory default masking for applicable status registers is shown below. Providing an unsupported command code to SMBALERT_MASK will generate a CML for Invalid/Unsupported Data. SMBALERT_MASK Default Setting: (Refer Also to Figure 2) STATUS RESISTER ALERT Mask Value MASKED BITS STATUS_VOUT 0x00 None STATUS_IOUT 0x00 None STATUS_TEMPERATURE 0x00 None STATUS_CML 0x00 None STATUS_INPUT 0x00 None STATUS_MFR_SPECIFIC 0x11 Bit 4 (internal PLL unlocked), bit 0 (FAULT low) 100 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (Fault Response and Communication) MFR_FAULT_PROPAGATE_LTC3882-1 The MFR_FAULT_PROPAGATE_LTC3882-1 command determines events that cause FAULT to be asserted. Setting a bit in this register to a one allows the specified condition to assert the FAULT output for that channel. FAULT is not asserted by a fault, even if set to propagate, if that FAULT_RESPONSE is set to Ignore. The state of SMBLALERT_MASK does not affect FAULT propagation. Supported Values: BIT PROPAGATED CONDITION 15 Waiting for VOUT decay before restart. 14 VOUT short cycled (automatically deasserted 120ms after VOUT is fully OFF). 13 TON_MAX_FAULT_LIMIT exceeded. 12 (Reserved, must be set to 0). 11 MFR_OT_FAULT_LIMIT exceeded. 10 (Reserved, must be set to 0). 9 (Reserved, must be set to 0). 8 UT_FAULT_LIMIT exceeded. 7 OT_FAULT_LIMIT exceeded. 6 (Reserved). 5 (Reserved). 4 VIN_OV_FAULT_LIMIT exceeded. 3 (Reserved). 2 IOUT_OC_FAULT_LIMIT exceeded. 1 VOUT_UV_FAULT_LIMIT exceeded. 0 VOUT_OV_FAULT_LIMIT exceeded. This command has two data bytes. MFR_FAULT_RESPONSE The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to a FAULT pin being pulled low by anything other than an internal fault. Supported Values: VALUE MEANING 0xC0 Related PWM output is immediately disabled. 0x00 Input ignored, PWM operation continues without interruption. When a FAULT pin is low, the device also: * Sets the MFR_SPECIFIC Bit in the STATUS_WORD * Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULT Is or Has Been Low * Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte. 38821f For more information www.linear.com/LTC3882-1 101 LTC3882-1 PMBus COMMAND DETAILS (Fault Response and Communication) MFR_FAULT_LOG The MFR_FAULT_LOG command allows the contents of the fault log to be read. This log is created with a MFR_FAULT_LOG_STORE command or at the first fault occurrence after a CLEAR_FAULTS or MFR_FAULT_LOG_CLEAR command. If a fault occurs within the first second after applying power, some earlier pages in the log may not contain valid data. This read-only command uses block protocol with 147 bytes of data requiring an estimated data transfer time of 3.4ms at 400kHz. The tTIMEOUT parameter is extended when this command is executed and a fault log is present. MFR_FAULT_LOG_CLEAR The MFR_FAULT_LOG_CLEAR command erases all stored fault log values. After a clear is issued, up to 8ms may be required to clear related bit 3 in STATUS_MFR_SPECIFIC. This write-only command has no data bytes. EEPROM User Access COMMAND NAME CMD CODE DESCRIPTION STORE_USER_ALL 0x15 Store entire operating memory in EEPROM. Send Byte N NA RESTORE_USER_ALL 0x16 Restore entire operating memory from EEPROM. Send Byte N NA MFR_COMPARE_USER_ALL 0xF0 Compare operating memory with EEPROM contents. Send Byte N MFR_FAULT_LOG_STORE 0xEA Force transfer of fault log from operating memory to EEPROM. Send Byte N MFR_EE_UNLOCK 0xBD (contact the factory) MFR_EE_ERASE 0xBE (contact the factory) TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE MFR_EE_DATA 0xBF USER_DATA_00 0xB0 EEPROM word reserved for LTpowerPlay. (contact the factory) R/W Word N Reg l USER_DATA_01 0xB1 EEPROM word reserved for LTpowerPlay. R/W Word Y Reg l USER_DATA_02 0xB2 EEPROM word reserved for OEM use. R/W Word N Reg l USER_DATA_03 0xB3 EEPROM word available for general data storage. R/W Word Y Reg l 0x0000 USER_DATA_04 0xB4 EEPROM word available for general data storage. R/W Word N Reg l 0x0000 Related commands: MFR_CONFIG_ALL_LTC3882-1 Note that if the LTC3882-1 die temperature exceeds 130C, execution of any command in the above table except RESTORE_USER_ALL and MFR_FAULT_LOG_STORE will be disabled until the IC temperature drops below 125C. RESTORE_USER_ALL is executed immediately, and MFR_FAULT_LOG_STORE is executed after the IC temperature drops below 125C. Refer to Table 4 for details of fault log contents. Using any command that writes data to the EEPROM is strongly discouraged if bit 6 of STATUS_MFR_ SPECIFIC is set, indicating the internal die temperature is above 85C. Data retention of 10 years is not guaranteed if the EEPROM is written above a junction temperature of 85C. 102 38821f For more information www.linear.com/LTC3882-1 LTC3882-1 PMBus COMMAND DETAILS (EEPROM User Access) STORE_USER_ALL The STORE_USER_ALL command instructs the PMBus device to copy the entire contents of the operating memory to internal EEPROM PMBus configuration space. This write-only command has no data bytes. RESTORE_USER_ALL The RESTORE_USER_ALL command instructs the PMBus device to copy the entire contents of the internal EEPROM to matching locations in operating memory. The values in operating memory are overwritten by the values retrieved from EEPROM. Both channels should be turned off prior to issuing this command. The LTC3882-1 ensures both PWM channels are off, loads the operating memory from internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both PWM channels, if enabled This write-only command has no data bytes. MFR_COMPARE_USER_ALL The MFR_COMPARE_USER_ALL command instructs the LTC3882-1 to compare current operating memory (PMBus command values in RAM) with the contents of the internal EEPROM. If the compared memories differ, a CML fault is generated. This write-only command has no data bytes. MFR_FAULT_LOG_STORE The MFR_FAULT_LOG_STORE command forces a data log to be written to internal EEPROM as if a fault event had occurred. This command will generate a CML fault if the Enable Fault Logging bit is cleared in MFR_CONFIG_ALL_LTC3882-1. This write-only command has no data bytes. MFR_EE_xxxx The MFR_EE_xxxx commands facilitate bulk programming of the LTC3882-1 internal EEPROM. Contact the factory for details. USER_DATA_0x The USER_DATA_0x commands provide uncommitted EEPROM locations that may be applied as system scratchpad space. USER_DATA_00 and USER_DATA_01 should not be modified when using the LTpowerPlay GUI. Some contract manufacturers also reserve use of USER_DATA_02 for their own inventory control. 38821f For more information www.linear.com/LTC3882-1 103 LTC3882-1 PMBus COMMAND DETAILS (Unit Identification) Unit Identification COMMAND NAME CMD CODE DESCRIPTION MFR_ID 0x99 MFR_MODEL MFR_SERIAL Manufacturer identification. TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE R String N ASC LTC 0x9A LTC model number. R String N ASC LTC3882-1 0x9E R Block N Reg Device serial number. MFR_ID The MFR_ID command returns the manufacturer ID of the LTC3882-1 using 8-bit ASCII characters. This read-only command is in block format. MFR_MODEL The MFR_MODEL command returns the LTC part number using 8-bit ASCII characters. This read-only command is in block format. MFR_SERIAL The MFR_SERIAL command returns the serial number of this specific device using a maximum of fourteen 8-bit ASCII characters. This read-only command is in block format. 104 38821f For more information www.linear.com/LTC3882-1 R14 1.37k R15 10k For more information www.linear.com/LTC3882-1 R35 5.76k R34 24.9k 22 VOUT0_CFG ASEL1 ASEL0 C35 100pF 5 IAVG_GND VOUT1_CFG 20 FREQ_CFG 21 PHAS_CFG 39 IAVG0 30 IAVG1 19 18 17 16 PGOOD1 PWM1 ISENSE1+ ISENSE1- VSENSE1 27 26 31 32 2 TSNS0 3 TSNS1 28 COMP1 29 FB1 + 33 COMP0 1 VDD33 C58 2.2F VDD33 R84 2.21 VCC C27 11pF VDD33 VDD33 C26 270pF R30 100k R21 100k C18 4.7F R85 2.21 IN VCC BOOST C28 10nF D2 Q1 TS TG 2 1 6 9 LTC4449 3 VLOGIC BG 5 4 IN GND GND 7 8 4 3 2 1 C56 0.22F C29 10nF C55 0.22F Q2 PLACE Q1,Q2 NEAR L1, L2 RESPECTIVELY 9 GND BG TS TG GND LTC4449 VLOGIC VCC BOOST R29 C25 1.07k 200pF C57 2.2F 5 6 7 8 D1 Q4 Q3 Q6 Q5 Figure 53. 36V Input 3.3V/40A 1.0MHz Converter with Discrete Gate Drivers 41 GND VCC 25 VCC VCC +5V INPUT SUPPLY 7 PWM0 6 PGOOD0 + 38 ISENSE0 37 ISENSE0- 36 VSENSE0+ VSENSE0- 35 34 VSENSE1- 40 FB0 VINSNS C17 1F 4 LTC3882-1 VDD33 VDD25 24 VDD25 SCL 10 SDA 11 ALERT 12 FAULT0 13 FAULT1 14 RUN0 15 RUN1 23 SHARE_CLK 8 SYNC R20 4.99k 9 C16 2.2F C8 100nF Q1, Q2: MMBT3906 Q3, Q5: BSC050N04LSG Q4, Q6: BSC010N04LS L1, L2: PULSE PA0513.221NLT R31 17.4k RUN R18 10k R19 4.99k R32 16.2k VDD25 R17 10k + VDD33 C4 47F R5 1 VIN 24V TO 36V VIN VIN CIN1 22F x2 C24 0.22F R8 3.09k L1 0.2H PULSE CIN3 22F x2 38821 F53 L2 0.2H PULSE R55 3.09k C66 0.22F C12 100F x2 + C14 470F x4 GND VOUT 3.3V 40A LTC3882-1 Typical Applications 38821f 105 106 RUN ALERT SDA SCL R14 4.22k VDD25 R15 10k R18 10k R34 24.9k R17 10k R35 5.76k R19 4.99k VOUT0_CFG ASEL0 ASEL1 SYNC SHARE_CLK For more information www.linear.com/LTC3882-1 C35 100pF 30 39 41 GND LTC3882-1 VCC 25 36 37 PGOOD1 PWM1 27 26 32 31 ISENSE1+ ISENSE1- VSENSE1 1 2 TSNS0 3 TSNS1 28 COMP1 29 FB1 + 33 COMP0 35 VSENSE0- 34 VSENSE1- 40 FB0 VSENSE0+ ISENSE0- 7 PWM0 6 PGOOD0 38 ISENSE0+ VINSNS C17 1F 4 VDD33 PWM1 VDD33 R30 60.4k C27 18pF C26 180pF R21 100k VIN TSNS0 TSNS1 C130 0.22F VSENSE- VSENSE+ C110 47F 38821 F54 C119 0.22F R29 C25 4.12k 470pF VDD33 +3.3V INPUT SUPPLY PWM0 C18 4.7F C111 22F +7V VOUTB VOUTA PWMB PWMA TEMPB TEMPA 2 6 11 GND GND GND +CSB -CSB D12S1R845A -CSA +CSA VINB VINA 4 16 15 5 3 10 12 C107 2.2F POWER BLOCK: DELTA D12S1R845A TSNS1 TSNS0 C129 1.0F 8 7 C124 1.0F 1 14 9 13 +7V INPUT SUPPLY Figure 54. High Density 1.5V/45A 650kHz Converter Using Dual Power Block 5 IAVG_GND IAVG1 IAVG0 VOUT1_CFG 20 FREQ_CFG 21 PHAS_CFG 19 18 17 16 8 23 22 VDD25 C8 100nF VDD33 VDD25 SCL 24 R5 1 10 SDA 11 ALERT 12 FAULT0 13 FAULT1 14 RUN0 15 RUN1 R20 4.99k 9 C16 0.1F VIN 7V TO 13.2V + VSENSE- C117 100F x2 VSENSE+ PWM1 PWM0 C120 470F x3 GND VOUT 1.5V 45A LTC3882-1 Typical Applications 38821f LTC3882-1 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UJ Package 40-Lead Plastic QFN (6mm x 6mm) (Reference LTC DWG # 05-08-1728 Rev O) 0.70 0.05 6.50 0.05 5.10 0.05 4.42 0.05 4.50 0.05 (4 SIDES) 4.42 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 0.10 (4 SIDES) 0.75 0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 4.50 REF (4-SIDES) 4.42 0.10 2 PIN 1 NOTCH R = 0.45 OR 0.35 x 45 CHAMFER 4.42 0.10 (UJ40) QFN REV O 0406 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD 38821f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC3882-1 107 LTC3882-1 Typical Application VIN 7V TO 14V 1 330F x2 + 10k 4.99k 10k 10k 4.99k 10k 5VBIAS 100nF VDD33 VDD25 VCC 2.2F 9 VDD25 16.2k 17.4k 17 7 6 PGOOD0 38 ISENSE0+ ISENSE0 VSENSE0+ 19 22F x2 100k VDD33 COMP0 1 7.32k IAVG_GND GND 5 28 29 33 VSENSE1+ VSENSE1- 34 32 ISENSE1- 31 ISENSE1+ 26 PWM1 27 PGOOD1 PWM PWM0 DISB RUN 220pF 1.21k + VOUT0 1.8V, 30A 470F x4 0.22F PLACE Q1,Q2 NEAR L1, L2 RESPECTIVELY 10nF Q2 5VBIAS 220pF 10nF 100pF 100F x4 GND 137 Q1 7.32k L1 0.22H PULSE VSWH GL 10nF 100pF 10nF VOUT1_CFG 20 FREQ_CFG 21 PHAS_CFG 39 IAVG0 30 IAVG1 FDMF6820A CGND 2 TSNS0 3 TSNS1 FB1 VCIN SMOD 36 ASEL0 VOUT0_CFG VIN PHASE GH CGND GND BOOT VDRV PGND 35 VSENSE0- 40 FB0 COMP1 18 PWM0 - 37 ASEL1 2k 1F VCC PWM0 LTC3882-1 16 +5V INPUT SUPPLY 10 25 VINSNS SCL 2.2F VIN 4.7F 4 22 VDD33 VDD25 10 SDA 11 ALERT 12 FAULT0 13 FAULT1 14 RUN0 15 RUN1 23 SHARE_CLK 8 SYNC RUN INPUT SUPPLY +5V TO +12V 1F 24 4.99k 1F 1F 137 2.2F 10 2k VIN 1F 22F x2 PWM1 100k 0.22F VIN PHASE GH CGND GND BOOT VDRV PGND VDD33 41 FDMF6820A VCIN SMOD PWM PWM1 DISB RUN VSWH CGND DrMOS: FAIRCHILD FD6802A GL 1.21k L2 0.22H PULSE 100F x4 + VOUT1 1V, 40A 470F x4 GND 38821 F55 Figure 55. 1V/40A and 1.8V/30A 500kHz Converter with DrMOS Power Stage Related Parts PART NUMBER DESCRIPTION COMMENTS LTM4676A Dual 13A or Single 26A Step-Down DC/DC Module Regulator with Digital Power Management VIN Up to 26.5V; 0.5V VOUT (0.5%) 5.4V, 2% IOUT ADC Accuracy, Fault Logging, I2C/PMBus Interface, 16mm x 16mm x 5mm, BGA Package LTC3887/ LTC3887-1 Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management, 70ms Start-Up VIN Up to 24V, 0.5V VOUT0,1 5.5V, 70mS Start-Up, I2C/PMBus Interface, with EEPROM and 16-Bit ADC. -1 Version Operates with DrMOS and Power Blocks LTC3886 60V Dual Output Step-Down Controller with Digital Power System Management. 70ms Start-Up VIN Up to 60V, 0.5V VOUT 13.8V, Analog Control Loop, I2C/ PMBus Interface with EEPROM and 16-Bit ADC, Programmable Loop Compensation LTC3880/ LTC3880-1 Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management VIN Up to 24V, 0.5V VOUT 5.5V, Analog Control Loop, I2C/PMBus Interface with EEPROM and 16-Bit ADC LTC3883/ LTC3883-1 Single Phase Step-Down DC/DC Controller with Digital Power VIN Up to 24V, 0.5V VOUT 5.5V, Input Current Sense Amplifier, I2C/ System Management PMBus Interface with EEPROM and 16-Bit ADC LTC2977 8-Channel PMBus Power System Manager Featuring Accurate Output Voltage Measurement Fault Logging to Internal EEPROM Monitors Eight Output Voltages, Input Voltage and Die Temperature LTC2974 Quad Digital Power Supply Manager with EEPROM Controls and Monitors Four Outputs, 16-Bit ADC, Differential Inputs, with Fault Logging LTC3774 Dual, Multiphase Current Mode Synchronous Controller for Sub-Milliohm DCR Sensing, with Remote Sense Operates with Power Blocks, DrMOS Devices or External MOSFETs 4.5V VIN 38V LTC3861 Dual, Multiphase, Synchronous Step-Down DC/DC Controller Operates with Power Blocks, DrMOS Devices or External MOSFETs 3V with Accurate Current Share VIN 24V LTC4449 High Speed Synchronous N-Channel MOSFET Driver 108 Linear Technology Corporation VIN Up to 38V, 4V VCC 6.5V, Adaptive Shoot-Through Protection, 2mm x 3mm DFN-8 Package 1630 McCarthy Blvd., Milpitas, CA For95035-7417 more information www.linear.com/LTC3882-1 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC3882-1 38821f LT 0915 * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2015