LTC3882-1
1
38821f
For more information www.linear.com/LTC3882-1
TYPICAL APPLICATION
FEATURES DESCRIPTION
Dual Output PolyPhase
Step-Down DC/DC Voltage Mode Controller
with Digital Power System Management
The LT C
®
3882-1 is a dual, PolyPhase DC/DC synchronous
step-down switching regulator controller with PMBus
compliant serial interface. It uses a constant frequency,
leading-edge modulation, voltage mode architecture for
excellent transient response and output regulation. Each
PWM channel can produce output voltages from 0.5V to
5.25V using a wide range of 3.3V compatible power stages,
including power blocks, DrMOS or discrete FET drivers.
Up to four LTC3882-1 devices can operate in parallel for
2-, 3-, 4-, 6- or 8-phase operation.
System configuration and monitoring is supported by the
LTpowerPlay™ software tool. The LTC3882-1 serial interface
can read back input voltage, output voltage and current,
temperature and fault status. Most operating parameters can
be set via the digital interface or stored in internal EEPROM
for use at power up. Switching frequency and phase, output
voltage and device address can also be set using external
configuration resistors.
n PMBus/I2C Compliant Serial Interface
Monitor Voltage, Current, Temperature and Faults
Program Voltage, Soft-Start/Stop, Sequencing,
Margining, AVP and UV/OV/OC Limits
n 3V ≤ VINSNS ≤ 38V, 0.5V ≤ VOUT ≤ 5.25V
n ±0.5% Output Voltage Error
n Programmable PWM Frequency or External Clock
Synchronization from 250kHz to 1.25MHz
n Accurate PolyPhase
®
Current Sharing
n Internal EEPROM with Fault Logging
n IC Supply Range: 3V to 13.2V
n Resistor or Inductor DCR Current Sensing
n Power Good Output Voltage Monitor
n Optional Resistor Programming for Key Parameters
n 40-Pin (6mm × 6mm) QFN Package
L, LT, LTC, LTM, Linear Technology,the Linear logo and PolyPhase are registered trademarks
and LTpowerPlay is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 5396245, 5859606,
6144194, 6937178, 7420359 and 7000125.
APPLICATIONS
n High Current Distributed Power Systems
n Servers, Network and Storage Equipment
n Intelligent Energy Efficient Power Regulation
LTC3882-1
SDA
RUN1
ISENSE0+
ISENSE0
VSENSE0+
VSENSE0
VSENSE1
RUN0
FAULT1
FAULT0
FB0
COMP0
TSNS0
TSNS1
GND
38821 TA01a
IAVG_GND
PWM0
VSENSE1+
ISENSE1
ISENSE1+
PWM1
V
IN
7V TO 13.2V
TO/FROM
MCU
SCL
ALERT COMP1
VCC VINSNS
FDMF5820DC
FDMF5820DC
INDUCTORS: COOPER FP1007R1-R22
SOME DETAILS OMITTED FOR CLARITY
PWM
VIN
V
OUT
1V
70A
SW
GND
IAVG1
IAVG0
TO/FROM
EXTERNAL DEVICES
PGOOD1
SYNC
SHARE_CLK
PGOOD0
PWM
VIN
SW
GND
Load Step Transient Current Sharing
(Using FDMF5820DC DrMOS)
PWM ENABLE
OUTPUT
TG/BG
CONTROL
HW WRITE
PROTECT
DEDICATED
PGOOD OUTPUT
DIFFERENTIAL
VOUT SENSE
LTC3882 VOUT0 Only
LTC3882-1 VOUT0 & VOUT1
50µs/DIV
IOUT
10A/DIV
IL0, IL1
10A/DIV
38821 TA01b
LTC3882-1
2
38821f
For more information www.linear.com/LTC3882-1
TABLE OF CONTENTS
Features ..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings .............................. 4
Order Information .......................................... 4
Pin Configuration .......................................... 4
Electrical Characteristics ................................. 5
Typical Performance Characteristics ................... 9
Pin Functions .............................................. 13
Block Diagram ............................................. 15
Test Circuit ................................................. 16
Timing Diagram ........................................... 16
Operation................................................... 16
Overview ............................................................ 16
Main Control Loop .............................................. 17
Power-Up and Initialization ................................. 19
Soft-Start ...........................................................20
Time-Based Output Sequencing .........................20
Output Ramping Control .....................................20
Voltage-Based Output Sequencing .....................20
Minimum Output Disable Times .........................21
Output Short Cycle .............................................21
Light Load Current Operation .............................21
Switching Frequency and Phase .........................21
PolyPhase Load Sharing .....................................22
Active Voltage Positioning .................................. 22
Input Supply Monitoring .....................................22
Output Voltage Sensing and Monitoring ............. 22
Output Current Sensing and Monitoring ............. 22
External and Internal Temperature Sense ...........23
Resistor Configuration Pins ................................23
Internal EEPROM with CRC ................................ 24
Fault Detection ....................................................24
Input Supply Faults ............................................. 24
Hardwired PWM Response to VOUT Faults ......... 24
Power Good Indication (Master) .........................25
Power Good Indication (Slave) ...........................25
Hardwired PWM Response to IOUT Faults ............... 25
Hardwired PWM Response to Temperature Faults .. 25
Hardwired PWM Response to Timing Faults ......26
External Faults ....................................................26
Fault Handling .....................................................26
Status Registers and ALERT Masking .................26
FAULT Pin I/O ......................................................28
Fault Logging ......................................................28
Factory Default Operation ...................................31
Serial Interface ...................................................32
Serial Bus Addressing ........................................32
Serial Bus Timeout .............................................36
Serial Communication Errors..............................36
PMBus Command Summary ............................ 37
PMBus Commands .............................................37
Data Formats ...................................................... 37
Applications Information ................................ 42
Efficiency Considerations ...................................42
PWM Frequency and Inductor Selection .............42
Power MOSFET Selection ...................................43
MOSFET Driver Selection ...................................44
Using PWM Protocols ........................................44
CIN Selection .......................................................44
COUT Selection ....................................................45
Feedback Loop Compensation ............................46
PCB Layout Considerations ................................47
Output Current Sensing ......................................48
Output Voltage Sensing ...................................... 50
Soft-Start and Stop ............................................ 51
Time-Based Output Sequencing and Ramping ... 51
Voltage-Based Output Sequencing .....................52
Using Output Voltage Servo ...............................54
Using AVP ..........................................................54
PWM Frequency Synchronization .......................55
PolyPhase Operation and Load Sharing .............56
External Temperature Sense ............................... 60
Resistor Configuration Pins ................................ 60
Internal Regulator Outputs .................................62
IC Junction Temperature.....................................62
Derating EEPROM Retention at Temperature ...... 63
Configuring Open-Drain Pins .............................. 63
PMBus Communication and Command Processing 64
Status and Fault Log Management .....................65
LTpowerPlay – An Interactive Digital Power GUI 65
Interfacing to the DC1613 ................................... 66
Design Example ..................................................66
PMBus COMMAND DETAILS ............................. 70
Addressing and Write Protect ................................. 70
PAGE ..................................................................70
PAGE_PLUS_WRITE ..........................................70
PAGE_PLUS_READ ............................................ 71
WRITE_PROTECT ...............................................71
MFR_ADDRESS .................................................72
MFR_RAIL_ADDRESS .......................................72
General Device Configuration .................................72
PMBUS_REVISION ............................................. 72
CAPABILITY ........................................................72
MFR_CONFIG_ALL_LTC3882-1 .........................73
On, Off and Margin Control .....................................73
ON_OFF_CONFIG ................................................ 73
OPERATION ........................................................ 74
MFR_RESET ....................................................... 74
LTC3882-1
3
38821f
For more information www.linear.com/LTC3882-1
TABLE OF CONTENTS
PWM Configuration ................................................75
FREQUENCY_SWITCH ........................................ 75
MFR_PWM_CONFIG_LTC3882-1 .......................76
MFR_CHAN_CONFIG_LTC3882-1 ......................77
MFR_PWM_MODE_LTC3882-1 ......................... 78
Input Voltage and Limits .........................................79
VIN_ON ..............................................................79
VIN_OFF .............................................................79
VIN_OV_FAULT_LIMIT ........................................79
VIN_UV_WARN_LIMIT ....................................... 79
Output Voltage and Limits ......................................80
VOUT_MODE ......................................................80
VOUT_COMMAND ..............................................80
MFR_VOUT_MAX ...............................................80
VOUT_MAX ........................................................ 81
MFR_VOUT_AVP ................................................81
VOUT_MARGIN_HIGH ........................................ 81
VOUT_MARGIN_LOW.........................................81
VOUT_OV_FAULT_LIMIT ....................................81
VOUT_OV_WARN_LIMIT ....................................82
VOUT_UV_WARN_LIMIT .................................... 82
VOUT_UV_FAULT_LIMIT ....................................82
Output Current and Limits ......................................83
IOUT_CAL_GAIN ................................................83
MFR_IOUT_CAL_GAIN_TC .................................83
IOUT_OC_FAULT_LIMIT .....................................83
IOUT_OC_WARN_LIMIT .....................................83
Output Timing, Delays, and Ramping .....................84
MFR_RESTART_DELAY ......................................84
TON_DELAY .......................................................84
TON_RISE ..........................................................84
TON_MAX_FAULT_LIMIT ...................................85
VOUT_TRANSITION_RATE .................................85
TOFF_DELAY ......................................................85
TOFF_FALL .........................................................85
TOFF_MAX_WARN_LIMIT ..................................85
External Temperature and Limits ............................86
MFR_TEMP_1_GAIN ...........................................86
MFR_TEMP_1_OFFSET .......................................86
OT_FAULT_LIMIT ................................................86
OT_WARN_LIMIT ...............................................86
UT_FAULT_LIMIT ................................................87
Status Reporting .....................................................87
STATUS_BYTE ....................................................87
STATUS_WORD ..................................................88
STATUS_VOUT ...................................................88
STATUS_IOUT ....................................................89
STATUS_INPUT ..................................................89
STATUS_TEMPERATURE ....................................89
STATUS_CML ..................................................... 90
STATUS_MFR_SPECIFIC .................................... 90
MFR_PADS_LTC3882-1 .....................................91
MFR_COMMON ..................................................91
CLEAR_FAULTS..................................................92
Telemetry ................................................................ 92
READ_VIN ..........................................................92
MFR_VIN_PEAK .................................................93
READ_VOUT ....................................................... 93
MFR_VOUT_PEAK .............................................. 93
READ_IOUT ........................................................93
MFR_IOUT_PEAK ............................................... 93
READ_POUT .......................................................93
READ_TEMPERATURE_1 ...................................94
MFR_TEMPERATURE_1_PEAK ..........................94
READ_TEMPERATURE_2 ...................................94
MFR_TEMPERATURE_2_PEAK ..........................94
READ_DUTY_CYCLE ..........................................94
READ_FREQUENCY ............................................ 94
MFR_CLEAR_PEAKS .........................................94
Fault Response and Communication .......................95
VIN_OV_FAULT_RESPONSE ............................... 95
VOUT_OV_FAULT_RESPONSE ............................96
VOUT_UV_FAULT_RESPONSE ............................96
IOUT_OC_FAULT_RESPONSE .............................97
OT_FAULT_RESPONSE ....................................... 98
UT_FAULT_RESPONSE .......................................98
MFR_OT_FAULT_RESPONSE .............................98
TON_MAX_FAULT_RESPONSE ..........................99
MFR_RETRY_DELAY ..........................................99
SMBALERT_MASK ........................................... 100
MFR_FAULT_PROPAGATE_LTC3882-1 ............ 101
MFR_FAULT_RESPONSE .................................. 101
EEPROM User Access ........................................... 102
MFR_FAULT_LOG ............................................. 102
MFR_FAULT_LOG_CLEAR ................................ 102
STORE_USER_ALL .......................................... 103
RESTORE_USER_ALL ...................................... 103
MFR_COMPARE_USER_ALL ........................... 103
MFR_FAULT_LOG_STORE ............................... 103
MFR_EE_xxxx .................................................. 103
USER_DATA_0x ...............................................103
Unit Identification ................................................. 104
MFR_ID ............................................................ 104
MFR_MODEL .................................................... 104
MFR_SERIAL .................................................... 104
Typical Applications .................................... 105
Package Description ................................... 107
Typical Application ..................................... 108
Related Parts ............................................ 108
LTC3882-1
4
38821f
For more information www.linear.com/LTC3882-1
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VCC Supply Voltage .................................... 0.3V to 15V
VINSNS Voltage ......................................... 0.3V to 40V
VSENSEn ...................................................... 0.3V to 1V
VSENSEn+, ISENSEn+, ISENSEn ........................ 0.3V to 6V
FBn, COMPn, TSNSn, IAVG_GND, IAVGn ...... 0.3V to 3.6V
SYNC, FA ULTn , PGOODn, SHARE_CLK ........0.3V to 3.6V
SCL, SDA, RUNn, ALERT ........................... 0.3V to 5.5V
ASELn, VOUTn_CFG, FREQ_CFG,
PHAS_CFG .............................................. 0.3V to 2.75V
PWMn, VDD25 .................................................. (Note 13)
VDD33 ............................................................... (Note 14)
Operating Junction Temperature
(Notes 2, 3) .......................................... 40°C to 125°C*
Storage Temperature Range ................ 65°C to 125°C*
*See Derating EEPROM Retention at Temperature in the
Applications Information section for junction temperatures
in excess of 125°C.
(Note 1)
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
TOP VIEW
41
GND
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
COMP0
TSNS0
TSNS1
VINSNS
IAVG_GND
PGOOD0
PWM0
SYNC
SCL
SDA
IAVG1
FB1
COMP1
PGOOD1
PWM1
VCC
VDD33
SHARE_CLK
VDD25
PHAS_CFG
FB0
IAVG0
ISENSE0+
ISENSE0
VSENSE0+
VSENSE0
VSENSE1
VSENSE1+
ISENSE1
ISENSE1+
ALERT
FAULT0
FAULT1
RUN0
RUN1
ASEL0
ASEL1
VOUT0_CFG
VOUT1_CFG
FREQ_CFG
21
30
10
1
TJMAX = 125°C, θJA = 33°C/W , θJC = 2.5°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3882EUJ-1#PBF LTC3882EUJ-1#TRPBF LTC3882UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
LTC3882IUJ-1#PBF LTC3882IUJ-1#TRPBF LTC3882UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC3882-1
5
38821f
For more information www.linear.com/LTC3882-1
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IC Supply
VCC VCC Voltage Range VDD33 = Internal LDO 4.5 13.8 V
VDD33_EXT VDD33 Voltage Range VCC = VDD33 (Note 6) l3 3.6 V
VUVLO Undervoltage Lockout Threshold VDD33 Rising
Hysteresis
l
42
3 V
mV
IQIC Operating Current 32 mA
tINIT Controller Initialization Time Delay from RESTORE_USER_ALL, MFR_RESET or
VDD33 > VUVLO Until TON_DELAY Can Begin
70 ms
VDD33 Linear Regulator
VDD33 VDD33 Regulator Output Voltage VCC ≥ 4.5V 3.2 3.3 3.4 V
IDD33 VDD33 Current Limit VDD33 = 2.8V
VDD33 = 0V
85
40
mA
mA
VDD25 Linear Regulator
VDD25 VDD25 Regulator Output Voltage 2.25 2.5 2.75 V
IDD25 VDD25 Current Limit 95 mA
PWM Control Loops
VINSNS VIN Sense Voltage Range 3 38 V
RVINSNS VINSNS Input Resistance 278
VOUT_R0 Range 0 Maximum VOUT
Range 0 Set Point Error (Note 7)
Range 0 Set Point Resolution
0.6V ≤ VOUT ≤ 5V
0.6V ≤ VOUT ≤ 5V
l
–0.5
5.25
±0.2
1.375
0.5
V
%
%
mV
VOUT_R1 Range 1 Maximum VOUT
Range 1 Set Point Error (Note 7)
Range 1 Set Point Resolution
0.6V ≤ VOUT ≤ 2.5V
0.6V ≤ VOUT ≤ 2.5V
l
–0.5
2.65
±0.2
0.6875
0.5
V
%
%
mV
IVSENSE VSENSE Input Current VSENSE+ = 5.5V
VSENSE = 0V
235
–335
µA
µA
VLINEREG VCC Line Regulation, No Output Servo 4.5V ≤ VCC ≤ 13.2V (See Test Circuit) –0.02 0.02 %/V
AVP AVP ∆VOUT AVP = 10%, VOUT_COMMAND = 1.8V,
ISENSE Differential Step 3mV to 12mV
with IOUT_OC_WARN_LIMIT = 15mV
l–118 –108 –96 mV
AV(OL) Error Amplifier Open-Loop Voltage Gain 87 dB
SR Error Amplifier Slew Rate 9.5 V/µs
f0dB Error Amplifier Bandwidth (Note 12) 30 MHz
ICOMP Error Amplifier Output Current Sourcing
Sinking
–2.6
34
mA
mA
RVSFB Resistance Between VSENSE+ and FB Range 0
Range 1
l
l
52
37
67
49
83
61
VISENSE ISENSE Differential Input Range ±70 mV
IISENSE ISENSE± Input Current 0V ≤ VPIN ≤ 5.5V –1 ±0.1 1 µA
IAVG_VOS IAVG Current Sense Offset Referred to ISENSE Inputs
l
–600
±175
650
µV
µV
VSIOS Slave Current Sharing Offset Referred to ISENSE Inputs
l
–800
±300
700
µV
µV
fSYNC SYNC Frequency Error 250kHz ≤ fSYNC ≤ 1.25MHz l–10 10 %
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0 =
VSENSE1 = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
LTC3882-1
6
38821f
For more information www.linear.com/LTC3882-1
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Voltage Supervisor
VON_TOL Input ON/OFF Threshold Error 15V ≤ VIN_ON ≤ 35V l–2 2 %
NVON Input ON/OFF Threshold Resolution 143 mV
Output Voltage Supervisors
VUVOV_R0 Range 0 Maximum Threshold
Range 0 Error
Range 0 Threshold Resolution
Range 0 Threshold Hysteresis
2V ≤ VOUT ≤ 5V (Falling for UV and Rising for OV)
l
–1
5.5
11
1
54
V
%
mV
mV
VUVOV_R1 Range 1 Maximum Threshold
Range 1 Error
Range 1 Threshold Resolution
Range 1 Threshold Hysteresis
1V ≤ VOUT ≤ 2.5V (Falling for UV and Rising for OV)
l
–1
2.75
5.5
1
27
V
%
mV
mV
Output Current Supervisors
VILIM_TOL Output Current Limit Tolerance
ISENSE+ – ISENSE15mV < ISENSE+ – ISENSE ≤ 30mV
30mV < ISENSE+ – ISENSE ≤ 50mV
50mV < ISENSE+ – ISENSE ≤ 70mV
l
l
l
–1.7
–2.5
–5.2
1.7
2.5
5.2
mV
mV
mV
NlLIM ISENSE+ – ISENSEThreshold Resolution 1LSB 0.4 mV
ADC Readback Telemetry (Note 8)
NVIN VINSNS Readback Resolution (Note 9) 10 Bits
VIN_TUE VINSNS Total Unadjusted Readback Error 4.5V ≤ VINSNS ≤ 38V
l
0.5
2
%
%
NDC PWM Duty Cycle Resolution (Note 9) 10 Bits
DCTUE PWM Duty Cycle Total Unadjusted
Readback Error
PWM Duty Cycle = 12.5% –2 2 %
NVOUT VOUT Readback Resolution 244 µV
VOUT_TUE VOUT Total Unadjusted Readback Error 0.6V ≤ VOUT ≤ 5.5V, Constant Load
l
–0.5
±0.2
0.5
%
%
NISENSE IOUT Readback Resolution
LSB Step Size (at ISENSE±)
(Note 9)
0mV ≤ |ISENSE+ – ISENSE| < 16mV
16mV ≤ |ISENSE+ – ISENSE| < 32mV
32mV ≤ |ISENSE+ – ISENSE| < 63.9mV
63.9mV ≤ |ISENSE+ – ISENSE| ≤ 70mV
10
15.625
31.25
62.5
125
Bits
µV
µV
µV
µV
ISENSE_TUE IOUT Total Unadjusted Readback Error |ISENSE+ – ISENSE| ≥ 6mV, 0V ≤ VOUT ≤ 5.5V l–1 1 %
ISENSE_OS IOUT Zero-Code Offset Voltage ±32 µV
NTEMP Temperature Resolution 0.25 °C
TEXT_TUE External Temperature Total Unadjusted
Readback Error
TSNS0, TSNS1 ≤ 1.85V (Note 10)
MFR_PWM_MODE_LTC3882-1[6] = 0
MFR_PWM_MODE_LTC3882-1[6] = 1
l
l
–3
–7
3
7
°C
°C
TINT_TUE Internal Temperature Total Unadjusted
Readback Error
Internal Diode (Note 10) ±1 °C
tCONVERT Update Rate (Note 11) 100 ms
Internal EEPROM (Notes 4, 6)
Endurance Number of Write Operations 0°C ≤ TJ ≤ 85°C During All Write Operations 10,000 Cycles
Retention Stored Data Retention TJ ≤ 125°C 10 Years
Mass Write Time STORE_USER_ALL Execution Duration 0°C ≤ TJ ≤ 85°C During All Write Operations 0.2 2 s
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0 =
VSENSE1 = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
LTC3882-1
7
38821f
For more information www.linear.com/LTC3882-1
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Inputs (SCL, SDA, RUNn, FAULTn, SYNC, SHARE_CLOCK)
VIH Input High Voltage SCL, SDA, RUN0, RUN1, FAULT0, FAULT1
SYNC, SHARE_CLK
l
l
2.0
1.8
V
V
VIL Input Low Voltage SCL, SDA, RUN0, RUN1, FAULT0, FAULT1
SYNC, SHARE_CLK
l
l
1.4
0.6
V
V
VHYST Input Hysteresis SCL, SDA 80 mV
CIN Input Capacitance SCL, SDA, RUN0, RUN1, FAULT0, FAULT1, SYNC,
SHARE_CLK (Note 12)
10 pF
tFILT Input Digital Filter Delay FAULT0, FAULT1
RUN0, RUN1
3
10
µs
µs
Digital Outputs (SCL, SDA, RUNn, FAULTn, SYNC, SHARE_CLOCK, ALERT, PWMn, PGOODn)
VOL Output Low Voltage ISINK = 3mA; SDA, SCL, RUN0, RUN1, FAULT0,
FAULT1, SYNC, SHARE_CLK, ALERT,
ISINK = 2mA; PWMn, PGOODn
l
l
0.2 0.4
0.3
V
V
VOH PWMn Output High Voltage ISOURCE = 2mA l2.7 V
ILKG Output Leakage Current 0V ≤ PWM0, PWM1, PGOOD0, PGOOD1 ≤ VDD33
0V ≤ FAULT0, FAULT1, SYNC, SHARE_CLK ≤ 3.6V
0V ≤ RUN0, RUN1 ≤ 5.5V
0V ≤ SCL, SDA, ALERT ≤ 5.5V
l
–1
–5
–5
1
5
5
µA
µA
µA
tRO PWMn Output Rise Time CLOAD = 30pF, 10% to 90% 5 ns
tFO PWMn Output Fall Time CLOAD = 30pF, 90% to 10% 4 ns
Serial Bus Timing
fSMB Serial Bus Operating Frequency l10 400 kHz
tBUF Bus Free Time Between Stop and Start l1.3 µs
tHD,STA Hold Time After (Repeated) Start
Condition. After This Period, the First
Clock Is Generated
l0.6 µs
tSU,STA Repeated Start Condition Setup Time l0.6 µs
tSU,STO Stop Condition Setup Time l0.6 µs
tHD,DAT Data Hold Time:
Receiving Data
Transmitting Data
l
l
0
0.3
0.9
ns
µs
tSU,DAT Input Data Setup Time l100 ns
tTIMEOUT Clock Low Timeout l25 35 ms
tLOW Serial Clock Low Period l1.3 10000 µs
tHIGH Serial Clock High Period l0.6 µs
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0 =
VSENSE1 = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
LTC3882-1
8
38821f
For more information www.linear.com/LTC3882-1
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3882-1 is tested under pulsed load conditions such that
TJ≈TA. The LTC3882-1E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3882-1I is guaranteed
over the full –40°C to 125°C operating junction temperature range.
Junction temperature TJ is calculated in °C from the ambient temperature
TA and power dissipation PD according to the formula:
TJ = TA + (PDθJA)
where θJA is the package thermal impedance. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors. Refer to the
Applications Information section.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: EEPROM endurance, retention and mass write times are
guaranteed by design, characterization and correlation with statistical
process controls. Minimum retention applies only for devices cycled less
than the minimum endurance specification. EEPROM read commands
(e.g. RESTORE_USER_ALL) are valid over the entire specified operating
junction temperature range.
Note 5: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 6: Minimum EEPROM endurance, retention and mass write time
specifications apply when writing data with 3.15V ≤ VDD33 ≤ 3.45V.
EEPROM read commands are valid over the entire specified VDD33
operating range.
Note 7: Specified VOUT error with AVP = 0% requires servo mode to be
set with MFR_PWM_MODE_LTC3882-1 command bit 6. Performance is
guaranteed by testing the LTC3882-1 in a feedback loop that servos VOUT
to a specified value.
Note 8: ADC tested with PWMs disabled. Comparable capability
demonstrated by in-circuit evaluations. Total Unadjusted Error includes all
gain and linearity errors, as well as offsets.
Note 9: Internal 32-bit calculations using 16-bit ADC results are limited to
10-bit resolution by PMBus Linear 11-bit data format.
Note 10: Limits guaranteed by TSNS voltage and current measurements
during test, including ADC readback.
Note 11: Data conversion is done in round robin fashion. All inputs signals
are continuously scanned in sequence resulting in a typical conversion
latency of 100ms.
Note 12: Guaranteed by design.
Note 13: Do not apply a voltage or current source directly to these pins.
They should only be connected to passive RC loads, otherwise permanent
damage may occur.
Note 14: Do not apply a voltage source to this pin unless shorted to VCC.
See Electrical Characteristics for applicable limits beyond which permanent
damage may occur.
LTC3882-1
9
38821f
For more information www.linear.com/LTC3882-1
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
(1-Phase Using D12S1R880A
Power Block)
Typical LTC3882-1 Output Voltage
Distribution at 0°C
Efficiency and Loss vs Load
(2-Phase Using FDMF5820DC
DRMOS)
LTC3882-1 1.0V Regulated Output
vs Temperature
Efficiency vs Load Current
(3-Phase Using D12S1R845A
Power Block)
Typical LTC3882-1 Output Voltage
Distribution at 105°C
LOAD CURRENT (A)
0
EFFICIENCY (%)
95
90
80
85
75 10 20 30
38821 G04
40
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
VIN = 12V
LOAD CURRENT (A)
0
EFFICIENCY (%)
94
92
88
84
90
86
82
80 4020 60
38821 G05
70
3010 50
VIN = 12V
VOUT = 1.5V
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
NUMBER OF ICs
4000
3500
2500
1500
500
3000
2000
1000
0
38821 G06
CH1 ISENSE OFFSET TO IDEAL (µV)
–400 400300200100–300–200–100 0
9595 UNITS
FROM 3 LOTS
TA = –40°C
TJ = –22°C
CHO MASTER
NUMBER OF ICs
3500
2500
1500
500
3000
2000
1000
0
38821 G07
CH1 ISENSE OFFSET TO IDEAL (µV)
–400 400300200100–300–200–100 0
8593 UNITS
FROM 3 LOTS
TJ = 38°C
CHO MASTER
NUMBER OF ICs
4500
2500
1500
500
4000
3500
3000
2000
1000
0
38821 G08
CH1 ISENSE OFFSET TO IDEAL (µV)
–300 500400300200100–200–100 0
11783 UNITS
FROM 3 LOTS
TJ = 121°C
CHO MASTER
LOAD CURRENT (A)
0
EFFICIENCY (%)
92
90
88
86
84
82
91
89
87
85
83
81
80
POWERLOSS (W)
13
9
5
11
7
3
1
2010 30
38821 G03
8070605040
VIN = 12V
VOUT = 1V
SYNC = 500kHz
TA (°C)
–5
VOUT (V)
1.001
1.0005
0.9995
1.0
0.999
0.9985 95
38821 G01
7515 5535
VIN = 12V
VOUT_COMMAND = 1.0V
DIGITAL SERVO ENGAGED
IOUT = 6.5A
NUMBER OF CHANNELS
1000
900
700
500
300
200
100
800
600
400
0
38821 G01a
VOUT ERROR (mV)
–1.25 11.250.750.50.25–1 0.75 0.50.25 0
1094 UNITS
VOUT_COMMAND = 1.0V
DIGITAL SERVO
ENGAGED
1078 UNITS
VOUT_COMMAND = 1.0V
DIGITAL SERVO
ENGAGED
VOUT ERROR (mV)
–2.5
NUMBER OF CHANNELS
1200
1000
600
200
800
400
00.5 1 1.5 2
38821 G02
2.50–2 –1 –0.5–1.5
LTC3882-1
10
38821f
For more information www.linear.com/LTC3882-1
Efficiency and Power Loss vs
Input Voltage
(1-Phase Using LTC4449)
3-Phase Transient Response
(Using D12S1R860A Power Block)
1-Phase Single Cycle Response
(Using D12S1R860A Power Block
with COUT = 6 × 100µF X5R 1210)
TYPICAL PERFORMANCE CHARACTERISTICS
3+1 Channel Crosstalk
(Using D12S1R845A Power
Blocks)
Load Step Transient Response
Using AVP
Line Step Transient Response
(1-phase Using LTC4449)
VIN (V)
5
EFFICIENCY (%)
100
98
96
94
92
90
88
86
84
82
80
POWERLOSS (W)
3.0
2.0
1.0
2.5
1.5
0.5
0
2010 2515
38821 G12
30
VO = 1.8V
POWER FET: BSC050N04LS G
SYNC FET: BSC010N04LS
VOUT0
(1-PHASE)
20mV/DIV
VOUT1
(3-PHASE)
20mV/DIV
IOUT1
10A/DIV
100µs/DIV 38821 G15
25%
LOAD STEP VOUT
IO
10A/DIV
VOUT
VIN
2V/DIV
7V
1.8V
100µs/DIV
VOUT
(10mV/DIV)
IOUT
(10A/DIV)
38821 G13
VOUT = 0.9V/90A
VIN = 12V
SYNC = 500kHz
L = 210nH
25mVP-P
2µs/DIV
IOUT
(10A/DIV)
VSW
(10V/DIV)
VOUT
(20mV/DIV)
38821 G14
VOUT = 1V/25A
VIN = 12V
SYNC = 1MHz
L = 210nH
3-Phase DC Output Current
Sharing (Using D12S1R845A
Power Block
Load Step Transient Current
Sharing (Using FDMF6707B
DrMOS)
Load Dump Transient Current
Sharing (Using FDMF6707B
DrMOS)
TOTAL RAIL CURRENT (A)
0
PHASE CURRENT (A)
20
2
18
14
10
6
16
12
8
4
060 70
38821 G09
80
5020 4010 30
CHANNEL 1
CHANNEL 2
CHANNEL 3
IL1, IL2
10A/DIV
VOUT
IOUT
20A/DIV
5µs/DIVVOUT = 1V
VIN = 12V
SYNC = 500kHz
IL1, IL2
10A/DIV
VOUT
IOUT
20A/DIV
5µs/DIVVOUT = 1V
VIN = 12V
SYNC = 500kHz
LTC3882-1
11
38821f
For more information www.linear.com/LTC3882-1
Soft-Start Ramp Start-Up Into a Prebiased Load Soft-Off Ramp
TYPICAL PERFORMANCE CHARACTERISTICS
Output Overvoltage Threshold
Error vs Temperature
Output Overcurrent Threshold
Error vs Temperature PWM Frequency vs Temperature
TEMPERATURE (°C)
–40
VOUT OV THRESHOLD ERROR (%)
0.10
0.05
0
–0.10
–0.05
–0.15 60 80
38821 G21
12010020 40–20 0
VOUT_OV_FAULT_LIMIT = 2V
VOUT RANGE = 1
OUTPUT OC THRESHOLD ERROR (%)
1.2
0.8
0.4
0
1.0
0.6
0.2
–0.2
–0.4
38821 G22
TEMPERATURE (°C)
–40 60 80 12010020 40–20 0
PWM FREQUENCY (kHz)
500.2
500.1
499.9
499.7
500.0
499.8
499.6
499.5
38821 G23
TEMPERATURE (°C)
–40 60 80
120
10020 40–20 0
FREQUENCY_SWITCH = 500kHz
RUN
2V/DIV
VOUT
1V/DIV
5ms/DIV
TOFF_DELAY = 10ms
TOFF_FALL = 5ms
38821 G20
VOUT
0.5V/DIV
1ms/DIV
38821 G18
IL1, IL2
10A/DIV
V
IN
= 12V
VOUT
0.5V/DIV
0V
1ms/DIV
38821 G19
IL1, IL2
10A/DIV
V
IN
= 12V
VOUT_COMMAND INLRegulated Output vs Temperature VOUT_COMMAND DNL
VOUT (V)
0.3
INL (LSB)
1.5
1.0
0
0.5
–0.5
–1.0 4.3 5.1
38821 G01
5.53.51.1 2.71.9
VOUT (V)
0.3
DNL (LSB)
1.0
0.8
0.4
0
–0.4
0.6
0.2
–0.2
–0.6
–0.8 4.3 5.1
38821 G02
5.53.51.1 2.71.9
TEMPERATURE (°C)
–40
VOUT (V)
1.8000
1.7995
1.7985
1.7975
1.7990
1.7980
1.7970 60 80
38821 G01a
12010020 40–20 0
VOUT_COMMAND = 1.8V
DIGITAL SERVO OFF
LTC3882-1
12
38821f
For more information www.linear.com/LTC3882-1
TYPICAL PERFORMANCE CHARACTERISTICS
VIN(SNS) ADC TUE VOUT ADC TUE IOUT ADC TUE
VINSNS (V)
0
MEASUREMENT ERROR (mV)
0
–1
–3
–5
–7
–2
–4
–6
–8
–9 30 35
38821 G24
402510 205 15
VOUT (V)
0.5
MEASUREMENT ERROR (mV)
0.40
0.30
0.20
0.10
0
–0.10
–0.20
–0.30
–0.40
4.5
38821 G25
1.5 2.5 3.5
5.5
41 2 3 5
OUTPUT CURRENT (A)
0
MEASUREMENT ERROR (mA)
0
2
4
20
38821 G26
–2
–4
–8 510 15
–6
8
6
Temperature ADC TUE
SHARE_CLK Frequency vs
Temperature
IC Operating Current vs
Temperature
ACTUAL TEMPERATURE (°C)
–45
–1.0
MEASUREMENT ERROR (°C)
–0.8
–0.4
–0.2
0
1.0
0.4
–5 35 55
38821 G27
–0.6
0.6
0.8
0.2
–25 15 75 95 115
TEMPERATURE (°C)
–50
90
SHARE_CLK FREQUENCY (kHz)
95
100
105
110
–30 –10 10 30
38821 G28
50 70 90
110
I
CC
OPERATING CURRENT (mA)
31.0
30.8
30.4
30.0
30.6
30.2
29.8
29.4
29.6
38821 G29
TEMPERATURE (°C)
–40 60 80
120
10020 40–20 0
VCC = 14V
LTC3882-1
13
38821f
For more information www.linear.com/LTC3882-1
PIN FUNCTIONS
COMP0/COMP1 (Pin 1/Pin 29): Error Amplifier Outputs.
PWM duty cycle increases with this control voltage. These
are true low impedance outputs and cannot be directly
connected together when active. For PolyPhase operation,
wiring FB to VDD33 will three-state the error amplifier output
of that channel, making it a slave. PolyPhase control is
then implemented in part by connecting all slave COMP
pins together to one master error amplifier output.
TSNS0/TSNS1 (Pin 2/Pin 3): External Temperature Sense
Inputs. The LTC3882-1 supports two methods of calcula-
tion of external temperature based on forward-biased P/N
junctions between these pins and GND.
VINSNS (Pin 4): VIN Supply Sense. Connect to the VIN
power supply to provide line feedforward compensation.
A change in VIN immediately modulates the input to the
PWM comparator and inversely changes the pulse width
to provide excellent transient line regulation and fixed
modulator voltage gain. An external lowpass filter can be
added to this pin to prevent noisy signals from affecting
the loop gain.
IAVG_GND (Pin 5): IAVG Ground Reference. The same
IAVG_GND should be shared between all channels of a
PolyPhase rail and connected to system ground at a single
point. IAVG_GND may be wired directly to GND on ICs that
do not share phases with other chips.
PGOOD/PGOOD1 (Pin 6/Pin 27): Power Good Indicator
Open-Drain Outputs. These outputs are driven low through
a 30µs filter when the respective channel output is below
its programmed UV fault limit or above its programmed
OV fault limit. If used, a pull-up resistor is required in the
application. Operating voltage range is GND to VDD33.
PWM0/PWM1 (Pin 7/Pin 26): PWM Three-State Control
Outputs. These pins provide single-wire PWM switching
control for each channel to an external gate driver, DrMOS
or power block. Operating voltage range is GND to VDD33.
SYNC (Pin 8): External Clock Synchronization Input and
Open-Drain Output. If desired, an external clock can be
applied to this pin to synchronize the internal PWM chan-
nels. If the LTC3882-1 is configured as a clock master, this
pin will also pull to ground at the selected PWM switching
frequency with a 125ns pulse width. A pull-up resistor to
3.3V is required in the application if SYNC is driven by
any LTC3882-1. Minimize the capacitance on this line to
ensure its time constant is fast enough for the application.
SCL (Pin 9): Serial Bus Clock Input. A pull-up resistor to
3.3V is required in the application.
SDA (Pin 10): Serial Bus Data Input and Output. A pull-up
resistor to 3.3V is required in the application.
ALERT (Pin 11): Open-Drain Status Output. This pin may
be connected to the system SMBALERT wire-AND inter-
rupt signal and should be left open if not used. If used, a
pull-up resistor is required in the application. Operating
voltage range is GND to VDD33.
FAULT0/FAULT1 (Pin 12/Pin 13): Programmable Digital
Inputs and Open-Drain Outputs for Fault Sharing. Used
for channel-to-channel fault communication and propaga-
tion. These pins should be left open if not used. If used,
a pull-up resistor to 3.3V is required in the application.
RUN0/RUN1 (Pin 14/Pin 15): Run Control Inputs and
Open-Drain Outputs. A voltage above 2V is required on
these pins to enable the respective PWM channel. The
LTC3882-1 will drive these pins low under certain reset/
restart conditions regardless of any PMBus command
settings. A pull-up resistor to 3.3V is required in the ap-
plication.
ASEL0/ASEL1 (Pin 16/Pin 17): Serial Bus Address Select
Pins. Connect optional 1% resistor dividers between VDD25
and GND to these pins to select the serial bus interface
address. Refer to the Applications Information section
for more detail.
VOUT0_CFG/VOUT1_CFG (Pin 18/Pin 19): Output Voltage
Configuration Pins. Connect optional 1% resistor divid-
ers between VDD25 and GND to these pins to select the
output voltage for each channel. Refer to the Applications
Information section for more detail.
FREQ_CFG (Pin 20): Frequency Configuration Pin. Connect
an optional 1% resistor divider between VDD25 and GND
to this pin to configure PWM switching frequency. Refer
to the Applications Information section for more detail.
LTC3882-1
14
38821f
For more information www.linear.com/LTC3882-1
PIN FUNCTIONS
PHAS_CFG (Pin 21): Phase Configuration Pin. Connect
an optional 1% resistor divider between VDD25 and GND
to this pin to configure the phase of each PWM channel
relative to SYNC. Refer to the Applications Information
section for more detail.
VDD25 (Pin 22): Internal 2.5V Regulator Output. Bypass
this pin to GND with a low ESR 1µF capacitor. Do not load
this pin with external current beyond that required for local
LTC3882-1 configuration pins, if any.
SHARE_CLK (Pin 23): Share Clock Open-Drain Output
(bussed). Share Clock, nominally 100kHz, is used to
sequence multiple rails in a power system utilizing more
than one LTC PSM controller. A pull-up resistor is required
in the application. Minimize the capacitance on this line to
ensure the time constant is fast enough for the application.
Operating voltage range is GND to VDD33.
VDD33 (Pin 24): Internal 3.3V Regulator Output. Bypass this
pin to GND with a low ESR 2.2µF capacitor. The LTC3882-1
may also be powered from an external 3.3V rail attached
to this pin, if also shorted to VCC. Do not overload this pin
with external system current. Local pull-up resistors for
the LTC3882-1 itself may be powered from VDD33. Refer
to the Applications Information section for more detail.
VCC (Pin 25): 3.3V Regulator Input. Bypass this pin to
GND with a capacitor (0.1µF to 1µF ceramic) in close
proximity to the IC.
VSENSE0–/VSENSE1 (Pin 35/Pin 34): Negative Output
Voltage Sense Inputs. These pins must still be properly
connected on slave channels for accurate output current
telemetry.
VSENSE0+/VSENSE1+ (Pin 36/Pin 33): Positive Output Voltage
Sense Inputs. These pins must still be properly connected
on slave channels for accurate output current telemetry.
ISENSE0/ISENSE1 (Pin 37/Pin 32): Current Sense Ampli-
fier Inputs. The (–) inputs to the amplifiers are normally
connected to the low side of a DCR sensing network or
output current sense resistor for each phase.
ISENSE0+/ISENSE1+ (Pin 38/Pin 31): Current Sense Ampli-
fier Inputs. The (+) inputs are normally connected to the
high side of an output current sense resistor or the R-C
midpoint of a parallel DCR sense circuit.
IAVG0/IAVG1 (Pin 39/Pin 31): Average Current Control Pins.
A capacitor connected between these pins and IAVG_GND
stores a voltage proportional to the average output current
of the master channel. PolyPhase control is then imple-
mented in part by connecting all slave IAVG pins together
to the master IAVG output. This pin should be left open
on channels that control single-phase outputs. Operating
voltage range is GND to 2.1V.
FB0/FB1 (Pin 40/Pin 30): Error Amplifier Inverting Inputs.
These pins provide an internally scaled version of the
output voltage for use in loop compensation. Refer to the
Applications Information section for additional details on
compensating the output voltage control loop with external
components.
GND (Exposed Pad Pin 41): Ground and VSENSE1. All
small-signal and compensation components should
connect to this pad, which also serves as the negative
voltage sense input for channel 1. The exposed pad must
be soldered to a suitable PCB copper ground plane for
proper electrical operation and to obtain the specified
package thermal resistance.
LTC3882-1
15
38821f
For more information www.linear.com/LTC3882-1
BLOCK DIAGRAM
16-BIT
ADC
PWM1
VSENSE1±
ANALOG
MUX
3882-1 BD
ISENSE1±
INTERNAL
TEMPERATURE
PWM1
VINSNS
BIAS AND
HOUSEKEEPING
3.3V
REGULATOR
2.5V
REGULATOR
MCU AND
CUSTOM
LOGIC
TSNS1
VSENSE1±
ISENSE1±
IAVG1
TSNS0
PWM0
VSENSE0±
ISENSE0±
VINSNS
VDD33
VCC
PLL
SYNC
R_CONFIG
SHARE_CLK
PMBus
RAM
ROM
EEPROM
VOLTAGE
REFERENCE
VREF
12-BIT
DAC
INTERNAL DATA BUS
PWM0
VINSNS
ISENSE0±
VSENSE0±
IAVG0
I
AVG_GND
12-BIT
DAC
PGOOD0
PWM0
PWM1
PGOOD1
LTC3882-1
16
38821f
For more information www.linear.com/LTC3882-1
TEST CIRCUIT
TIMING DIAGRAM
OPERATION
SDA
SCL
tHD(STA) tHD(DAT)
tSU(STA) tSU(STO)
tSU(DAT)
tLOW
tHD(SDA) tSP tBUF
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
tr
tftr
tf
tHIGH
38821 TD
(Channel 0 Example)
135 36 40
+
DIGITAL
LTC3882-1
COMP0FB0VSENSE0+
VR
VSENSE0
1.024V
1V
12-BIT
D/A
+
LTC1055
TARGET = VOUT_COMMAND
EA
38821 TC
Overview
The LTC3882-1 is a dual channel/dual phase, constant
frequency analog voltage mode controller for DC/DC step-
down applications. It features a PMBus compliant digital
interface for monitoring and control of important power
system parameters. The chip operates from an IC power
supply between 3V and 13.2V and is intended for conversion
from VIN between 3V and 38V to output voltages between
0.5V and 5.25V. It is designed to be used in a switching
architecture with external FET drivers, including higher
level integrations such as non-isolated power blocks.
Major features include:
Digitally Programmable Output Voltage
Digitally Programmable Output Current Limit
Digitally Programmable Input Voltage Supervisor
Digitally Programmable Output Voltage Supervisors
Digitally Programmable Switching Frequency
Digitally Programmable On and Off Delay Times
Digitally Programmable Soft-Start/Stop
LTC3882-1
17
38821f
For more information www.linear.com/LTC3882-1
OPERATION
Operating Condition Telemetry
Phase Locked Loop for Synchronous PolyPhase Opera-
tion (2, 3, 4, 6, or 8 phases)
Fully Differential Load Sense
Non-Volatile Configuration Memory
Optional External Configuration Resistors for Key Op-
erating Parameters
Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
Fault Event Data Logging
Capable of Standalone Operation with Default Factory
Configuration
PMBus Revision 1.2 Compliant Interface up to 400kHz
The PMBus interface provides access to important power
management data during system operation including:
Average Input Voltage
Average Output Voltages
Average Output Currents
Average PWM Duty Cycles
Internal LTC3882-1 Temperature
External Sensed Temperatures
Warning and Fault Status, Including Input and Output
Undervoltage and Overvoltage
The LTC3882-1 supports four serial bus addressing
schemes to access the individual PWM channels separately
or jointly.
Fault communication, reporting and system response
behavior are fully configurable. Two fault I/Os are pro-
vided (FAULT0, FAUL
T1) that can be controlled indepen-
dently. A separate ALERT pin also provides for a maskable
SMBALERT#. Fault responses for each channel may be
individually programmed, depending on the fault type.
PMBus status commands allow fault reporting over the
serial bus to identify a specific fault event.
Main Control Loop
The LTC3882-1 utilizes constant frequency voltage mode
control with leading-edge modulation. This provides
improved response to a load step increase, especially at
larger VIN/VOUT ratios found in the low voltage, high cur-
rent solutions demanded by modern digital subsystems.
The LTC3882-1 leading-edge modulation architecture
does not have a minimum on-time requirement. Minimum
duty cycle will be determined by performance limits of
the external power stage. The IC is also capable of active
voltage positioning (AVP) to afford the smallest output
capacitors possible for a given output voltage accuracy
over the anticipated full load range. The LTC3882-1 error
amplifiers have high bandwidth, low offset and low out-
put impedance, allowing the control loop compensation
network to be optimized for very high crossover frequen-
cies and excellent transient response. The controller also
achieves outstanding line transient response by using
input feedforward compensation to instantaneously adjust
PWM duty cycle and significantly reduce output under/
overshoot during supply voltage changes. This also has the
added advantage of making the DC loop gain independent
of input voltage.
The main PWM control loop used for each channel is
illustrated in Figure 1. During normal operation the top
MOSFET (power switch) driving choke L1 is commanded
off when the clock for that channel resets the RS latch.
The power switch is commanded back on when the main
PWM comparator VC, sets the RS latch. The error ampli-
fier EA output (COMP) controls the PWM duty cycle to
match the FB voltage to the EA positive terminal voltage
in steady state. A patented circuit adjusts this output for
VINSNS line feedforward.
The positive terminal of the EA is connected to the output
of a 12-bit DAC with values ranging from 0V to 1.024V. The
DAC value is determined by the resistor configuration pins
detailed in application Table 8, by values retrieved from inter-
nal EEPROM, or by a combination of PMBus commands to
synthesize the desired output voltage. Refer to the following
PMBus Command Details section of this document for more
information. The LTC3882-1 supports two output ranges.
EA can regulate the output voltage to 5.5x the DAC output
(Range 0) or 2.75x the DAC output (Range 1).
LTC3882-1
18
38821f
For more information www.linear.com/LTC3882-1
OPERATION
VINSNS
38821 F01
LTC3882
IAVG0
VSENSE0+
38
ISENSE0+
5
IAVG_GND
40
FB0
1
COMP0
(RANGE 0)
35
VSENSE0
37
ISENSE0
PWM0
9R
LOOP
COMPENSATION
NETWORK
2R
RS
VIN
VOC0
CS
L1
COUT
V
OUT
+
MODE
36
IOUT_OC_FAUL