Call Progress and "Voice" Detector CMX683
© 2006 CML Microsystems Plc 7 D/683/2
5.3 Block Diagram Description
Amplifier
The input signal is amplified by a self-biased inverting amplifier. The dc bias of this input is
internally set at ½VDD.
Signal Analyser
The frequency range, quality and consistency of the input signal is analysed by this functional
block. To be classified as a Call Progress signal the input signal frequencies must lie between
315 and 650 Hz, and the signal to noise ratio must be 16dB or greater. The signal must have a
minimum rms amplitude of about -60dB (relative to 775mVrms) and the signal must be consistent
over a period of about 80ms. These decode criteria are continuously monitored and the
assessment is updated every 6ms. To be classified as a Non Call Progress ("Voice") signal the
input signal frequencies must lie between 190 and 895 Hz and the frequencies must not match
the predefined profiles for DTMF or Call Progress signals. The signal must have a minimum rms
amplitude of about -60dB (relative to 775mVrms) and the signal must show activity over a period
of about 145ms (fast response) or 500ms (slow response).
Control and Output Logic
This block categorises the nature of the signal into Call Progress and Non Call Progress output
states. A Non Call Progress output is further checked for activity over a longer detection period,
resulting in a VOICE FAST output responding to speech/music in around 90ms and a VOICE
SLOW output (with a more consistent detection) responding in around 370ms. If the VOICE
FAST output is at logic 1 for more than 51% of the previous 728ms then the VOICE SLOW output
will change to a logic 1. If the VOICE FAST output is at logic 1 for less than 10% of the previous
728ms then the VOICE SLOW output will change to a logic 0. The Decode Output Truth Table on
the following page gives further details. Also refer to the timing diagram in Figure 5.
Level Detector
The Level Detector operates by measuring the level of the amplified input signal and comparing it
with a preset threshold, which has a nominal value of -42dB (relative to 775mVrms). The Level
Detector output goes to the Control and Output Logic block, where the Call Progress signal and
Voice detector outputs are gated with the Level Detector output. The CP DETECT, VOICE FAST
and VOICE SLOW outputs are valid only if the input signal level is above this preset threshold.
Xtal Oscillator
If the on-chip Xtal oscillator is to be used, an external 3.58MHz crystal (X1) only is required and
the CONFIG pin should be left unconnected. If an external clock source is to be used, the clock
should be connected to the CLOCK IN input pin and the XTAL pin should be connected to VSS.
The XTALN pin should be left unconnected and the CONFIG pin must be connected to VDD.
Note that this external clock option is not available with the P1 package.
Enable Input
A logic 1 applied to this input enables the whole device, including the outputs and the xtal
oscillator circuit. About 15ms should be allowed for the oscillator to start up, once enabled.
A logic 0 applied to this input resets the device, then powersaves the xtal oscillator, the signal
analyser, level detector and control and output logic. In addition the CPDETECT, VOICE FAST
and VOICE SLOW outputs will be cleared to a logic 0. The VREF supply is maintained at ½VDD, so
will continue to draw a small amount of current.
5.4 Decode Output Truth Table
In the following Truth Table it should be noted that it is possible to get both CP DETECT and
VOICE FAST or VOICE SLOW outputs simultaneously at logic 1. If the activity is initially