80C552/83C552
Single-chip 8-bit microcontroller
Product specification
Supersedes data of 1998 Jan 06
IC20 Data Handbook
1998 Aug 13
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
2
1998 Aug 13
DESCRIPTION
The 80C552/83C552 (hereafter generically
referred to as 8XC552) Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
8XC552 has the same instruction set as the
80C51. Three versions of the derivative exist:
•83C552—8k bytes mask programmable
ROM
•80C552—ROMless version of the 83C552
•87C552—8k bytes EPROM (described in a
separate chapter)
The 8XC552 contains a non-volatile 8k × 8
read-only program memory (83C552), a
volatile 256 × 8 read/write data memory, five
8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of
the 80C51), an additional 16-bit timer coupled
to capture and compare latches, a 15-source,
two-priority-level, nested interrupt structure,
an 8-input ADC, a dual DAC pulse width
modulated interface, two serial interfaces
(UART and I2C-bus), a “watchdog” timer and
on-chip oscillator and timing circuits. For
systems that require extra capability, the
8XC552 can be expanded using standard
TTL compatible memories and logic.
In addition, the 8XC552 has two software
selectable modes of power reduction—idle
mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM,
timers, serial ports, and interrupt system to
continue functioning. The power-down mode
saves the RAM contents but freezes the
oscillator, causing all other chip functions to
be inoperative.
The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte, and
17 three-byte. With a 16MHz (24MHz)
crystal, 58% of the instructions are executed
in 0.75µs (0.5µs) and 40% in 1.5µs (1µs).
Multiply and divide instructions require 3µs
(2µs).
FEATURES
•80C51 central processing unit
•8k × 8 ROM expandable externally to 64k
bytes
•ROM code protection
•An additional 16-bit timer/counter coupled
to four capture registers and three compare
registers
•Two standard 16-bit timer/counters
•256 × 8 RAM, expandable externally to 64k
bytes
•Capable of producing eight synchronized,
timed outputs
•A 10-bit ADC with eight multiplexed analog
inputs
•Two 8-bit resolution, pulse width
modulation outputs
•Five 8-bit I/O ports plus one 8-bit input port
shared with analog inputs
LOGIC SYMBOL
•I2C-bus serial I/O port with byte oriented
master and slave functions
•Full-duplex UART compatible with the
standard 80C51
•On-chip watchdog timer
•Three speed ranges:
–3.5 to 16MHz
–3.5 to 24MHz (ROM, ROMless only)
–3.5 to 30MHz (ROM, ROMless only)
•Three operating ambient temperature
ranges:
–P83C552xBx: 0°C to +70°C
–P83C552xFx: –40°C to +85°C
(XTAL frequency max. 24 MHz)
–P83C552xHx: –40°C to +125°C
(XTAL frequency max. 16 MHz)
PORT 5
PORT 4
ADC0-7
CMT0
CMT1
CMSR0-5
RST
EW
XTAL1
XTAL2
EA
ALE
PSEN
AVref+
AVref–
STADC
PWM0
PWM1
PORT 0
LOW ORDER
ADDRESS AND
DATA BUS
PORT 1PORT 2PORT 3
CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA
RxD/DATA
TxD/CLOCK
INT0
INT1
T0
T1
WR
RD
VSS
VDD
AVSS
AVDD
HIGH ORDER
ADDRESS AND
DATA BUS
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 3
PIN CONFIGURATIONS
Plastic Leaded Chip Carrier
NC*
P3.7/RD
P3.6/WR
P5.0/ADC0
10
11
12
13
14
15
16
30 31 32 33 34 35 36
P4.3/CMSR3
P4.4/CMSR4
P4.5/CMSR5
P4.6/CMT0
P4.7/CMT1
P1.0/CT0I
RST
37 3828 29
17
18
19
20
P1.1/CT1I
P1.2/CT2I
P1.4/T2
P1.3/CT3I
PLASTIC LEADED CHIP CARRIER
SU00932
21
22
23
24
25
26
P1.5/RT2
P1.6/SCL
P1.7/SDA
P3.0/RxD
P3.2/INT0
P3.1/TxD
39 40 41 42 43
P3.4/T0
P3.5/T1
NC*
NC*
XTAL2
XTAL1
VSS
P2.1/A09
P2.2/A10
P2.3/A11
P2.4/A12
60
59
58
57
56
55
54
AVSS
AVREF+
AVREF–
P0.0/AD0
P0.1/AD1
P0.3/AD3
P0.2/AD2
53
52
51
50
P0.4/AD4
P0.5/AD5
P0.7/AD7
P0.6/AD6
49
48
47
46
45
44
EA
ALE
PSEN
P2.7/A15
P2.5/A13
P2.6/A14
44
765432168 6798 66 65 64 63 62
P4.2/CMSR2
P4.1/CMSR1
P4.0/CMSR0
EW
PWM1
PWM0
STADC
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3
P5.4/ADC4
P5.5/ADC5
P5.6/ADC6
P5.7/ADC7
61
27
AVDD
VDD
P3.3/INT1
VSS
P2.0/A08
* Do not connect.
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 4
Plastic Quad Flat Pack
VDD
1
2
3
4
5
6
7
27 28 29 30 31 32 33
P4.1/CMSR1
P4.2/CMSR2
NC*
P4.3/CMSR3
P4.4/CMSR4
P4.6/CMT0
P4.5/CMSR5
34 3525 26
8
9
10
11
P4.7/CMT1
RST
P1.1/CT1I
P1.0/CT0I
PLASTIC QUAD FLAT PACK
SU00931
12
13
14
15
16
17
P1.2/CT2I
P1.3/CT3I
P1.4/T2
P1.5/RT2
P1.7/SDA
P1.6/SCL
18
19
20
21
P3.0/RxD
P3.1/TxD
NC*
P3.2/INT0
22
23
24
NC*
P3.3/INT1
PP3.4/T0
36 37 38 39 40
P3.5/T1
P3.6/WR
P3.7/RD
NC*
NC*
NC*
XTAL2
XTAL1
IC
VSS
VSS
VSS
NC*
P2.0/A08
P2.1/A09
P2.2/A10
64
63
62
61
60
59
58
P5.7/ADC7
AVDD
NC*
AVSS
AVREF+
P0.0/AD0
AVREF–
57
56
55
54
P0.1/AD1
P0.2/AD2
P0.4/AD4
P0.3/AD3
53
52
51
50
49
48
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
PSEN
ALE
47
46
45
44
P2.7/A15
P2.6/A14
NC*
P2.5/A13
43
42
41
NC*
P2.4/A12
P2.3/A11
78 77 76 75 74 73 72 71 7080 79 69 68 67 66 65
P4.0/SMSR0
NC*
NC*
EW
PWM1
PWM0
STADC
IC
P5.0/ADC0
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3
P5.4/ADC4
P5.5/ADC5
P5.6/ADC6
* Do not connect.
IC = Internally connected (do not use).
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 5
BLOCK DIAGRAM
CPU ADC
8-BIT INTERNAL BUS
16
P0 P1 P2 P3 TxD RxD P5 P4 CT0I-CT3I T2 RT2 CMSR0-CMSR5
CMT0, CMT1 RST EW
XTAL1
XTAL2
EA
ALE
PSEN
WR
RD
T0 T1 INT0 INT1
VDD VSS
PWM0 PWM1 AVSS
AVDD
AVREF
–+
STADC
ADC0-7 SDA SCL
3 3 3 3
3 3
0
2
1 1 1 4
115
0
1
2
ALTERNATE FUNCTION OF PORT 0 3
4
5
AD0-7
A8-15
3
3
16
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
PROGRAM
MEMORY
8k x 8 ROM
DATA
MEMORY
256 x 8 RAM
DUAL
PWM SERIAL
I2C PORT
80C51 CORE
EXCLUDING
ROM/RAM
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
8-BIT
PORT
FOUR
16-BIT
CAPTURE
LATCHES
T2
16-BIT
TIMER/
EVENT
COUNTERS
T2
16-BIT
COMPARA-
TORS
wITH
REGISTERS
COMPARA-
TOR
OUTPUT
SELECTION
T3
WATCHDOG
TIMER
ALTERNATE FUNCTION OF PORT 1
ALTERNATE FUNCTION OF PORT 2
ALTERNATE FUNCTION OF PORT 3
ALTERNATE FUNCTION OF PORT 4
ALTERNATE FUNCTION OF PORT 5
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 6
ORDERING INFORMATION
PHILIPS
PART ORDER NUMBER
PART MARKING
NORTH AMERICA PHILIPS
PART ORDER NUMBER DRAWING
NUMBER TEMPERATURE (°C)
AND PACKAGE FREQ
(MHz)
ROMless ROM1ROMless ROM EPROM2
()
P80C552EBA P83C552EBA/xxx S80C552-4A68 S83C552-4A68 S87C552-4A68 SOT188-2 0 to +70,
Plastic Leaded Chip Carrier 16
P80C552EBB P83C552EBB/xxx S80C552-4B S83C552-4B S87C552-4BA SOT318-2 0 to +70,
Plastic Quad Flat Pack 16
P80C552EFA P83C552EFA/xxx S80C552-5A68 S83C552-5A68 S87C552-5A68 SOT188-2 –40 to +85,
Plastic Leaded Chip Carrier 16
P80C552EFB P83C552EFB/xxx S80C552-5B S83C552-5B SOT318-2 –40 to +85,
Plastic Quad Flat Pack 16
P80C552EHA P83C552EHA/xxx S80C552-6A68 S83C552-6A68 SOT188-2 –40 to +125,
Plastic Leaded Chip Carrier 16
P80C552EHB P83C552EHB/xxx S80C552-6B S83C552-6B SOT318-2 –40 to +125,
Plastic Quad Flat Pack 16
P80C552IBA P83C552IBA/xxx S80C552-AA68 S83C552-AA68 SOT188-2 0 to +70,
Plastic Leaded Chip Carrier 24
P80C552IBB P83C552IBB/xxx S80C552-AB S83C552-AB SOT318-2 0 to +70,
Plastic Quad Flat Pack 24
P80C552IFA P83C552IFA/xxx S80C552-BA68 S83C552-BA68 SOT188-2 –40 to +85,
Plastic Leaded Chip Carrier 24
P80C552IFB P83C552IFB/xxx S80C552-BB S83C552-BB SOT318-2 –40 to +85,
Plastic Quad Flat Pack 24
P80C552KBA P83C552KBA/xxx S80C552-CA68 S83C552-CA68 SOT188-2 0 to +70,
Plastic Leaded Chip Carrier 30
P80C552KBB P83C552KBB/xxx S80C552-CB S83C552-CB SOT318-2 0 to +70,
Plastic Quad Flat Pack 30
NOTE:
1. xxx denotes the ROM code number.
2. For EPROM device specification, refer to
87C552
datasheet.
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 7
PIN DESCRIPTION
PIN NO.
MNEMONIC PLCC QFP TYPE NAME AND FUNCTION
VDD 2 72 I Digital Power Supply: +5V power supply pin during normal operation, idle and
power-down mode.
STADC 3 74 I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also
be started by software). This pin must not float.
PWM0 4 75 O Pulse Width Modulation: Output 0.
PWM1 5 76 O Pulse Width Modulation: Output 1.
EW 6 77 I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
This pin must not float.
P0.0-P0.7 57-50 58-51 I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s.
P1.0-P1.7 16-23 10-17 I/O Port 1: 8-bit I/O port. Alternate functions include:
16-21 10-15 I/O (P1.0-P1.5): Quasi-bidirectional port pins.
22-23 16-17 I/O (P1.6, P1.7): Open drain port pins.
16-19 10-13 ICT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.
20 14 IT2 (P1.4): T2 event input.
21 15 IRT2 (P1.5): T2 timer reset signal. Rising edge triggered.
22 16 I/O SCL (P1.6): Serial port clock line I2C-bus.
23 17 I/O SDA (P1.7): Serial port data line I2C-bus.
Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
P2.0-P2.7 39-46 38-42,
45-47 I/O Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08-A15).
P3.0-P3.7 24-31 18-20,
23-27 I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:
24 18 RxD(P3.0): Serial input port.
25 19 TxD (P3.1): Serial output port.
26 20 INT0 (P3.2): External interrupt.
27 23 INT1 (P3.3): External interrupt.
28 24 T0 (P3.4): Timer 0 external input.
29 25 T1 (P3.5): Timer 1 external input.
30 26 WR (P3.6): External data memory write strobe.
31 27 RD (P3.7): External data memory read strobe.
P4.0-P4.7 7-14 80, 1-2
4-8 I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
7-12 80, 1-2
4-6 OCMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with
timer T2.
13, 14 7, 8 OCMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
P5.0-P5.7 68-62, 71-64, IPort 5: 8-bit input port.
1ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.
RST 15 9 I/O Reset: Input to reset the 8XC552. It also provides a reset pulse as output when timer T3
overflows.
XTAL1 35 32 ICrystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the
internal clock generator. Receives the external clock signal when an external oscillator is
used.
XTAL2 34 31 OCrystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit
when an external clock is used.
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 8
PIN DESCRIPTION (Continued)
PIN NO.
MNEMONIC PLCC QFP TYPE NAME AND FUNCTION
VSS 36, 37 34-36 ITwo Digital ground pins.
PSEN 47 48 OProgram Store Enable: Active-low read strobe to external program memory.
ALE 48 49 OAddress Latch Enable: Latches the low byte of the address during accesses to external
memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up.
EA 49 50 IExternal Access: When EA is held at TTL level high, the CPU executes out of the internal
program ROM provided the program counter is less than 8192. When EA is held at TTL
low level, the CPU executes out of external program memory. EA is not allowed to float.
AVREF– 58 59 IAnalog to Digital Conversion Reference Resistor: Low-end.
AVREF+ 59 60 IAnalog to Digital Conversion Reference Resistor: High-end.
AVSS 60 61 IAnalog Ground
AVDD 61 63 IAnalog Power Supply
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5V or VSS – 0.5V,
respectively.
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol,
page 2.
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
power-on, the voltage on VDD and RST must
come up at the same time for a proper
start-up.
IDLE MODE
In the idle mode, the CPU puts itself to sleep
while some of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 1
shows the state of the I/O ports during low
current operating modes.
ROM CODE PROTECTION
(83C552)
The 83C552 has an additional security
feature. ROM code protection may be
selected by setting a mask–programmable
security bit (i.e., user dependent). This
feature may be requested during ROM code
submission. When selected, the ROM code
is protected and cannot be read out at any
time by any test mode or by any instruction in
the external program memory space.
The MOVC instructions are the only
instructions that have access to program
code in the internal or external program
memory. The EA input is latched during
RESET and is “don’t care” after RESET
(also if the security bit is not set). This
implementation prevents reading internal
program code by switching from external
program memory to internal program memory
during a MOVC instruction or any other
instruction that uses immediate data.
Table 1. External Pin Status During Idle and Power-Down Modes
MODE PROGRAM
MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PWM0/
PWM1
Idle Internal 1 1 Data Data Data Data Data 1
Idle External 1 1 Float Data Address Data Data 1
Power-down Internal 0 0 Data Data Data Data Data 1
Power-down External 0 0 Float Data Data Data Data 1
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 9
Serial Control Register (S1CON) – See Table 2
CR2 ENS1 STA STO SI AA CR1 CR0
S1CON (D8H)
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 2. Serial Clock Rates
BIT FREQUENCY (kHz) AT fOSC
CR2 CR1 CR0 6MHz 12MHz 16MHz 24MHz230MHz2fOSC DIVIDED BY
0 0 0 23 47 62.5 94 117 1 256
0 0 1 27 54 71 107 1134 1224
0 1 0 31 63 83.3 125 1156 1192
0 1 1 37 75 100 150 1188 1160
100 6.25 12.5 17 25 31 960
1 0 1 50 100 133 1200 1250 1120
1 1 0 100 200 267 1400 1500 160
1110.24 < 62.5 0.49 < 62.5 0.65 < 55.6 0.98 < 50.0 1.22 < 52.1 96 × (256 – (reload value T imer 1))
0 < 255 0 < 254 0 < 253 0 <251 0 < 250 reload value T imer 1 in Mode 2.
NOTES:
1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application.
2. At fOSC = 24MHz/ 30MHz the maximum I2C bus rate of 100kHz cannot be realized due to the fixed divider rates.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER RATING UNIT
Storage temperature range –65 to +150 °C
Voltage on any other pin to VSS –0.5 to +6.5 V
Input, output DC current on any single I/O pin 5.0 mA
Power dissipation
(based on package heat transfer limitations, not device power consumption) 1.0 W
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
DEVICE SPECIFICATIONS
SUPPLY VOLTAGE (V) FREQUENCY (MHz)
TYPE MIN MAX MIN MAX TEMPERATURE RANGE (°C)
P83(0)C552EBx 4.5 5.5 3.5 16 0 to +70
P83(0)C552EFx 4.5 5.5 3.5 16 –40 to +85
P83(0)C552EHx 4.5 5.5 3.5 16 –40 to +125
P83(0)C552IBx 4.5 5.5 3.5 24 0 to +70
P83(0)C552IFx 4.5 5.5 3.5 24 –40 to +85
P83(0)C552KBx 4.5 5.5 3.5 30 0 to +70
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 10
DC ELECTRICAL CHARACTERISTICS
VSS, AVSS = 0V; VDD, AVDD = 5V ± 10%
TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
IDD Supply current operating: See notes 1 and 2
P83(0)C552EBx fOSC = 16MHz 45 mA
P83(0)C552EFx fOSC = 16MHz 45 mA
P83(0)C552EHx fOSC = 16MHz 40 mA
P83(0)C552IBx fOSC = 24MHz 55 mA
P83(0)C552IFx fOSC = 24MHz 55 mA
P83(0)C552KBx fOSC = 30MHz 68 mA
IID Idle mode: See notes 1 and 3
P83(0)C552EBx fOSC = 16MHz 10 mA
P83(0)C552EFx fOSC = 16MHz 10 mA
P83(0)C552EHx fOSC = 16MHz 9 mA
P83(0)C552IBx fOSC = 24MHz 12.5 mA
P83(0)C552IFx fOSC = 24MHz 12.5 mA
P83(0)C552KBx fOSC = 30MHz 15 mA
IPD Power-down current: See notes 1 and 4;
2V < VPD < VDD max
P83(0)C552xBx 50 µA
P83(0)C552xFx 50 µA
P83(0)C552xHx 150 µA
Inputs
VIL Input low voltage, except EA, P1.6, P1.7 –0.5 0.2VDD–0.1 V
VIL1 Input low voltage to EA –0.5 0.2VDD–0.3 V
VIL2 Input low voltage to P1.6/SCL, P1.7/SDA5–0.5 0.3VDD V
VIH Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA 0.2VDD+0.9 VDD+0.5 V
VIH1 Input high voltage, XTAL1, RST 0.7VDD VDD+0.5 V
VIH2 Input high voltage, P1.6/SCL, P1.7/SDA50.7VDD 6.0 V
IIL Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7 VIN = 0.45V –50 µA
ITL Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7 See note 6 –650 µA
±IIL1 Input leakage current, port 0, EA, STADC, EW 0.45V < VI < VDD 10 µA
±IIL2 Input leakage current, P1.6/SCL, P1.7/SDA 0V < VI < 6V
0V < VDD < 5.5V 10 µA
±IIL3 Input leakage current, port 5 0.45V < VI < VDD 1µA
Outputs
VOL Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 IOL = 1.6mA70.45 V
VOL1 Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 IOL = 3.2mA70.45 V
VOL2 Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA70.4 V
VOH Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA –IOH = 60µA 2.4 V
–IOH = 25µA 0.75VDD V
–IOH = 10µA 0.9VDD V
VOH1 Output high voltage (port 0 in external bus mode, ALE,
PSEN PWM0 PWM1)8
–IOH = 400µA2.4 V
PSEN, PWM0, PWM1)
8
–IOH = 150µA 0.75VDD V
–IOH = 40µA 0.9VDD V
VOH2 Output high voltage (RST) –IOH = 400µA 2.4 V
–IOH = 120µA 0.8VDD V
RRST Internal reset pull-down resistor 50 150 kΩ
CIO Pin capacitance Test freq = 1MHz,
Tamb = 25°C10 pF
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 11
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
Analog Inputs
AIDD Analog supply current: operating: (16MHz) Port 5 = 0 to AVDD 1.2 mA
Analog supply current: operating: (24MHz, 30MHz) Port 5 = 0 to AVDD 1.0 mA
AIID Idle mode:
P83(0)C552EBx 50 µA
P83(0)C552EFx 50 µA
P83(0)C552EHx 100 µA
P83(0)C552IBx 50 µA
P83(0)C552IFx 50 µA
P83(0)C552KBx 50 µA
AIPD Power-down mode: 2V < AVPD < AVDD max
P83(0)C552xBx 50 µA
P83(0)C552xFx 50 µA
P83(0)C552xHx 100 µA
AVIN Analog input voltage AVSS–0.2 AVDD+0.2 V
AVREF Reference voltage:
AVREF– AVSS–0.2 V
AVREF+ AVDD+0.2 V
RREF Resistance between AVREF+ and AVREF– 10 50 kΩ
CIA Analog input capacitance 15 pF
tADS Sampling time 8tCY µs
tADC Conversion time (including sampling time) 50tCY µs
DLeDifferential non-linearity10, 11, 12 ±1 LSB
ILeIntegral non-linearity10, 13 ±2 LSB
OSeOffset error10, 14 ±2 LSB
GeGain error10, 15 ±0.4 %
AeAbsolute voltage error10, 16 ±3 LSB
MCTC Channel to channel matching ±1 LSB
CtCrosstalk between inputs of port 517 0–100kHz –60 dB
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for IDD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V;
VIH = VDD – 0.5V ; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V;
VIH = VDD – 0.5V ; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD;
EA = RST = STADC = XTAL1 = VSS.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5V will be recognized as a logic
0 while an input voltage above 3.0V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when VIN is approximately 2V.
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt T rigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the
address bits are stabilizing.
9. The following condition must not be exceeded: VDD – 0.2V < AVDD < VDD + 0.2V.
10.Conditions: A VREF– = 0V; AVDD = 5.0V, AVREF+ (80C552, 83C552) = 5.12V. ADC is monotonic with no missing codes. Measurement by
continuous conversion of AVIN = –20mV to 5.12V in steps of 0.5mV.
11.The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 1.)
12.The ADC is monotonic; there are no missing codes.
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 12
13.The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset error. (See Figure 1.)
14.The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
a straight line which fits the ideal transfer curve. (See Figure 1.)
15.The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)
16.The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
17.This should be considered when both analog and digital signals are simultaneously input to port 5.
Figure 1. ADC Conversion Characteristic
1
0
2
3
4
5
6
7
1018
1019
1020
1021
1022
1023
1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024
Code
Out
(2)
(1)
(5)
(4)
(3)
1 LSB
(ideal)
Offset
error
OSe
Offset
error
OSe
Gain
error
Ge
AVIN (LSBideal)
1 LSB = AVREF+ – AVREF–
1024
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DLe).
(4) Integral non-linearity (ILe).
(5) Center of a step of the actual transfer curve.
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 13
AC ELECTRICAL CHARACTERISTICS1, 2
16 MHz version
16MHz CLOCK VARIABLE CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
1/tCLCL 2Oscillator frequency 3.5 16 MHz
tLHLL 2ALE pulse width 85 2tCLCL–40 ns
tAVLL 2Address valid to ALE low 8 tCLCL–55 ns
tLLAX 2Address hold after ALE low 28 tCLCL–35 ns
tLLIV 2ALE low to valid instruction in 150 4tCLCL–100 ns
tLLPL 2ALE low to PSEN low 23 tCLCL–40 ns
tPLPH 2 PSEN pulse width 143 3tCLCL–45 ns
tPLIV 2 PSEN low to valid instruction in 83 3tCLCL–105 ns
tPXIX 2Input instruction hold after PSEN 0 0 ns
tPXIZ 2Input instruction float after PSEN 38 tCLCL–25 ns
tAVIV 2Address to valid instruction in 208 5tCLCL–105 ns
tPLAZ 2 PSEN low to address float 10 10 ns
Data Memory
tRLRH 3 RD pulse width 275 6tCLCL–100 ns
tWLWH 4 WR pulse width 275 6tCLCL–100 ns
tRLDV 3 RD low to valid data in 148 5tCLCL–165 ns
tRHDX 3Data hold after RD 0 0 ns
tRHDZ 3Data float after RD 55 2tCLCL–70 ns
tLLDV 3ALE low to valid data in 350 8tCLCL–150 ns
tAVDV 3Address to valid data in 398 9tCLCL–165 ns
tLLWL 3, 4 ALE low to RD or WR low 138 238 3tCLCL–50 3tCLCL+50 ns
tAVWL 3, 4 Address valid to WR low or RD low 120 4tCLCL–130 ns
tQVWX 4Data valid to WR transition 3 tCLCL–60 ns
tDW 4Data before WR 288 7tCLCL–150 ns
tWHQX 4Data hold after WR 13 tCLCL–50 ns
tRLAZ 3 RD low to address float 0 0 ns
tWHLH 3, 4 RD or WR high to ALE high 23 103 tCLCL–40 tCLCL+40 ns
External Clock
tCHCX 5High time420 20 ns
tCLCX 5Low time420 20 ns
tCLCH 5Rise time420 20 ns
tCHCL 5Fall time420 20 ns
Serial Timing – Shift Register Mode4 (Test Conditions: Tamb = 0°C to +70°C; VSS = 0V; Load Capacitance = 80pF)
tXLXL 6Serial port clock cycle time 0.75 12tCLCL µs
tQVXH 6Output data setup to clock rising edge 492 10tCLCL–133 ns
tXHQX 6Output data hold after clock rising edge 8 2tCLCL–117 ns
tXHDX 6Input data hold after clock rising edge 0 0 ns
tXHDV 6Clock rising edge to input data valid 492 10tCLCL–133 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. tCLCL = 1/fOSC = one oscillator clock period.
tCLCL = 83.3ns at fOSC = 12MHz.
tCLCL = 62.5ns at fOSC = 16MHz.
4. These values are characterized but not 100% production tested.
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 14
AC ELECTRICAL CHARACTERISTICS (Continued)1, 2
24/30 MHz version
24MHz CLOCK 30MHz CLOCK VARIABLE CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT
1/tCLCL 2Oscillator frequency 3.5 24 MHz
tLHLL 2ALE pulse width 43 27 2tCLCL–40 ns
tAVLL 2Address valid to ALE low 17 8 tCLCL–25 ns
tLLAX 2Address hold after ALE low 17 8 tCLCL–25 ns
tLLIV 2ALE low to valid instruction in 102 68 4tCLCL–65 ns
tLLPL 2ALE low to PSEN low 17 8 tCLCL–25 ns
tPLPH 2 PSEN pulse width 80 55 3tCLCL–45 ns
tPLIV 2 PSEN low to valid instruction in 65 40 3tCLCL–60 ns
tPXIX 2Input instruction hold after PSEN 0 0 0 ns
tPXIZ 2Input instruction float after PSEN 17 8 tCLCL–25 ns
tAVIV 2Address to valid instruction in 128 87 5tCLCL–80 ns
tPLAZ 2 PSEN low to address float 10 10 10 ns
Data Memory
tRLRH 3 RD pulse width 150 100 6tCLCL–100 ns
tWLWH 4 WR pulse width 150 100 6tCLCL–100 ns
tRLDV 3 RD low to valid data in 118 77 5tCLCL–90 ns
tRHDX 3Data hold after RD 0 0 0 ns
tRHDZ 3Data float after RD 55 39 2tCLCL–28 ns
tLLDV 3ALE low to valid data in 183 117 8tCLCL–150 ns
tAVDV 3Address to valid data in 210 135 9tCLCL–165 ns
tLLWL 3, 4 ALE low to RD or WR low 75 175 50 150 3tCLCL–50 3tCLCL+50 ns
tAVWL 3, 4 Address valid to WR low or RD low 92 58 4tCLCL–75 ns
tQVWX 4Data valid to WR transition 12 3 tCLCL–30 ns
tDW 4Data before WR 162 103 7tCLCL–130 ns
tWHQX 4Data hold after WR 17 8 tCLCL–25 ns
tRLAZ 3 RD low to address float 0 0 0 ns
tWHLH 3, 4 RD or WR high to ALE high 17 67 8 58 tCLCL–25 tCLCL+25 ns
External Clock
tCHCX 5High time317 15 17 ns
tCLCX 5Low time317 15 17 ns
tCLCH 5Rise time35 3 20 ns
tCHCL 5Fall time35 3 20 ns
Serial Timing – Shift Register Mode3 (Test Conditions: Tamb = 0°C to +70°C; VSS = 0V; Load Capacitance = 80pF)
tXLXL 6Serial port clock cycle time 0.5 0.4 12tCLCL µs
tQVXH 6Output data setup to clock rising edge 283 200 10tCLCL–133 ns
tXHQX 6Output data hold after clock rising edge 23 6.6 2tCLCL–60 ns
tXHDX 6Input data hold after clock rising edge 0 0 0 ns
tXHDV 6Clock rising edge to input data valid 283 200 10tCLCL–133 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
4. tCLCL = 1/fOSC = one oscillator clock period.
tCLCL = 41.7ns at fOSC = 24MHz.
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 15
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER INPUT OUTPUT
I2C Interface (Refer to Figure 9)
tHD;STA START condition hold time ≥ 14 tCLCL > 4.0µs 1
tLOW SCL low time ≥ 16 tCLCL > 4.7µs 1
tHIGH SCL high time ≥ 14 tCLCL > 4.0µs 1
tRC SCL rise time ≤ 1µs – 2
tFC SCL fall time ≤ 0.3µs< 0.3µs 3
tSU;DAT1 Data set-up time ≥ 250ns > 20 tCLCL – tRD
tSU;DAT2 SDA set-up time (before rep. START cond.) ≥ 250ns > 1µs 1
tSU;DAT3 SDA set-up time (before STOP cond.) ≥ 250ns > 8 tCLCL
tHD;DAT Data hold time ≥ 0ns > 8 tCLCL – tFC
tSU;STA Repeated START set-up time ≥ 14 tCLCL > 4.7µs 1
tSU;STO ST OP condition set-up time ≥ 14 tCLCL > 4.0µs 1
tBUF Bus free time ≥ 14 tCLCL > 4.7µs 1
tRD SDA rise time ≤ 1µs – 2
tFD SDA fall time ≤ 0.3µs< 0.3µs 3
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400pF.
4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 62ns, 42ns, 33.3ns < tCLCL < 285ns (16MHz, 24MHz, 30MHz > fOSC >
1.2MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s.
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 16
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN
Q – Output data
R–RD
signal
t – Time
V – Valid
W– WR
signal
X – No longer a valid logic level
Z – Float
Examples: tAVLL = T ime for address valid to
ALE low.
tLLPL = Time for ALE low to
PSEN low.
tPXIZ
Figure 2. External Program Memory Read Cycle
ALE
PSEN
PORT 0
PORT 2 A8–A15 A8–A15
A0–A7 A0–A7
tAVLL
tPXIX
tLLAX
INSTR IN
tPLIV
tLHLL
tPLPH
tLLIV
tPLAZ
tLLPL
tAVIV
ALE
PSEN
PORT 0
PORT 2
Figure 3. External Data Memory Read Cycle
RD
A0–A7
FROM RI OR DPL DATA IN A0–A7 FROM PCL INSTR IN
P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH
tWHLH
tLLDV
tLLWL tRLRH
tLLAX
tRLAZ
tAVLL tRHDX
tRHDZ
tAVWL
tAVDV
tRLDV
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 17
tLLAX
ALE
PSEN
PORT 0
PORT 2
Figure 4. External Data Memory Write Cycle
WR
A0–A7
FROM RI OR DPL DATA OUT A0–A7 FROM PCL INSTR IN
P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH
tWHLH
tLLWL tWLWH
tAVLL
tAVWL
tQVWX tWHQX
tDW
0.8V
tLOW
tHIGH
Figure 5. External Clock Drive XTAL1
VIH1 VIH1
0.8V
tCLCL
trtf
VIH1 VIH1
0.8V 0.8V
Figure 6. Shift Register Mode Timing
012345678
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
CLEAR RI
VALID VALID VALID VALID VALID VALID VALID VALID
SET TI
SET RI
tXLXL
tQVXH tXHQX
tXHDX
tXHDV
01234567
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 18
VDD–0.5
0.45V
0.2VDD+0.9
0.2VDD–0.1
NOTE:
AC INPUTS DURING TESTING ARE DRIVEN AT VDD–0.5 FOR A LOGIC ‘1’ AND
0.45V FOR A LOGIC ‘0’. TIMING MEASUREMENTS ARE MADE AT V IH MIN FOR A
LOGIC ‘1’ AND VIL MAX FOR A LOGIC ‘0’.
Figure 7. AC Testing Input/Output
VLOAD
VLOAD+0.1V
VLOAD–0.1V
VOH–0.1V
VOL+0.1V
NOTE:
FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV
CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A
100mV CHANGE FROM THE LOADED VOH/VOL LEVEL OCCURS. IOH/IOL > +
20mA.
Figure 8. Float W aveform
TIMING
REFERENCE
POINTS
Figure 9. Timing SIO1 (I2C) Interface
tRD
tSU;STA
tBUF
tSU;STO
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tFD tRC tFC
tHIGH
tLOW
tHD;STA tSU;DAT1 tHD;DAT tSU;DAT2
tSU;DAT3
START condition
repeated START condition
SDA
(INPUT/OUTPUT)
SCL
(INPUT/OUTPUT)
STOP condition
START or repeated START condition
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 19
40
30
20
10
124168
f (MHz)
(1)
Figure 10. 16MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC)
NOTE:
These values are valid only within the frequency specifications of the device under test.
IDD, ID mA
50
0
0
(2)
(3)
(4)
(1) Maximum operating mode; VDD = 6V
(2) Maximum operating mode; VDD = 4V
(3) Maximum idle mode; VDD = 6V
(4) Maximum idle mode; VDD = 4V
40
30
20
10
124168
f (MHz)
(1)
Figure 11. 24MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC)
NOTE:
These values are valid only within the frequency specifications of the device under test.
50
0
0
(2)
(3)
(4)
(1) Maximum operating mode; VDD = 5.5V
(2) Maximum operating mode; VDD = 4.5V
(3) Maximum idle mode; VDD = 5.5V
(4) Maximum idle mode; VDD = 4.5V
60
20 24
IDD, ID mA
Philips Semiconductors Product specification
80C552/83C552
Single-chip 8-bit microcontroller
1998 Aug 13 20
VDD
P0
EA
RST
XTAL1
XTAL2
VSS
VDD
VDD
VDD
IDD
(NC)
CLOCK SIGNAL
Figure 12. IDD Test Condition, Active Mode
All other pins are disconnected1
VDD
P0
EA
RST
XTAL1
XTAL2
VSS
VDD
VDD
IDD
(NC)
CLOCK SIGNAL
Figure 13. IDD Test Condition, Idle Mode
All other pins are disconnected2
VDD
P1.6
P1.7
STADC
AVSS
AVref–
EW
VDD
P1.6
P1.7
STADC
EW
AVSS
AVref–
VDD–0.5
0.5V 0.7VDD
0.2VDD–0.1
tCHCL
tCLCL
tCLCH
tCLCX tCHCX
Figure 14. Clock Signal W aveform for IDD Tests in Active
and Idle Modes tCLCH = tCHCL = 5ns
VDD
P0
RST
XTAL1
XTAL2
VSS
VDD
VDD
IDD
(NC)
Figure 15. IDD Test Condition, Power Down Mode
All other pins are disconnected. VDD = 2V to 5.5V3
VDD
P1.6
P1.7
STADC
EA
EW
AVSS
AVref–
NOTES:
1. Active Mode:
a. The following pins must be forced to VDD: EA, RST, Port 0, and EW.
b. The following pins must be forced to VSS: STADC, AVss, and AVref–.
c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the IOL1 spec of these pins.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
2. Idle Mode:
a. The following pins must be forced to VDD: Port 0 and EW.
b. The following pins must be forced to VSS: RST, STADC, AVss,, AVref–, and EA.
c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
3. Power Down Mode:
a. The following pins must be forced to VDD: Port 0 and EW.
b. The following pins must be forced to VSS: RST, STADC, XTAL1, AVss,, AVref–, and EA.
c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Philips Semiconductors Product specification
80C552/83C552Single-chip 8-bit microcontroller
1998 Aug 13 21
PLCC68: plastic leaded chip carrier; 68 leads SOT188-2
Philips Semiconductors Product specification
80C552/83C552Single-chip 8-bit microcontroller
1998 Aug 13 22
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT318-2
Philips Semiconductors Product specification
80C552/83C552Single-chip 8-bit microcontroller
1998 Aug 13 23
NOTES
Philips Semiconductors Product specification
80C552/83C552Single-chip 8-bit microcontroller
1998 Aug 13 24
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Date of release: 08-98
Document order number: 9397 750 04289
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
