© Freescale Semiconductor, Inc., 2005. All rights reserved.
Freescale Semiconductor
Technical Data
This document contains detailed information on power
considerations, AC/DC electrical characteristics, and AC
timing specifications for revision A,B, and C of the MPC850
Family.
1Overview
The MPC850 is a ve rsatile, one-chip integrated
microprocessor and peripheral combination that can be used
in a variety of controller applications, excelling particularly
in comm unicati ons and networking products. The MPC850,
which includes support for Ethernet, is specifically designed
for cost-sensitive, remote-access, and telecommunications
applications. It is provides functions similar to the MPC860,
with system enhancements such as universal serial bus
(USB) support and a larger (8-Kbyte) dual-port RAM.
In addition to a high-performance embedded MPC8xx core,
the MP C850 integrates s yst em f unctions, such as a versatile
memory contr oller and a communications processor module
(CPM) that incorporates a specialized, independent RISC
communications processor (ref erred to as the CP). This
separate processor off-loads peripheral tasks from the
embedded MPC8xx core .
Document Number: MPC850EC
Rev. 2, 07/2005
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Electrical and Thermal Characteristics . . . . . . . . . . . . 7
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8
5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 9
6. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 39
8. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 41
9. M echani cal Data and O rdering I nfor m ation . . . . . . . 63
10. Document Revision History . . . . . . . . . . . . . . . . . . . 68
MPC850
PowerQUICC™ Integrated
Communications Processor
Hardware Specifications
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
2Freescale Semiconductor
Overview
The CPM of the MPC850 supports up to seven serial channels, as follows:
• One or two serial communications controllers (SCCs). The SCCs support Ethernet , ATM
(MPC850SR and MPC850DSL), HDLC and a number of other protocols, along with a transparent
mode of opera tion.
• One USB channel
• Two serial management controllers (SMCs)
• One I2C port
• One serial peripheral interface (SPI).
Table 1 shows the functionality supported by the members of the MPC850 famil y.
Additional documentation may be provided for parts listed in Table 1.
Table 1. MPC850 Functionality Matrix
Part
Number of
SCCs
Supported
Ethernet
Support ATM Support USB Support
Multi-channel
HDLC
Support
Number of
PCMCIA Slots
Supported
MPC850 1 Yes - Yes - 1
MPC850DE 2 Yes - Yes - 1
MPC850SR 2 Yes Yes Yes Yes 1
MPC850DSL 2 Yes Yes Yes No 1
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 3
Features
2Features
Figure 1 is a block diagram of the MPC850, showing its major components and the relationships among
those components:
Figure 1. MPC850 Microprocessor Block Diagram
The following list summarizes the main features of the MPC850:
• Embedded single-issue, 32-bi t MPC8xx core (implementing the Power PC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— Performs branch folding and branch prediction with conditional prefetch, but without
conditional execution
System Interface Unit
Memory Cont roll er
Bu s In te rfa ce Un it
System Functions
Re al-Ti me Clock
PCMCIA Interf ace
Bus
Embedded
2-Kbyte
I-Cache
MMU
1-Kbyte
D-Cache
Data
MMU
Load/Store
Instruction
Bus
Pa ra llel I/ O
Baud Rate
Generators Dual-Port
RAM
Interrupt
Controller
Four
Timers 20 Virtual
2 Virtual
32-Bit RISC Communic ations
Pro cessor (CP) and Prog ram R OM
SCC2 USB SPI
Timer
Non-Multiplexed Serial Interface
MPC8xx
Core
Instruction
IDMA
Channels
Serial DMA
and
Channels
Unified Bus
Communications
Processor
Module
Pe riphera l B u s
SCC3 I2C
—
UTOPIA
Ports
(850SR & DSL)
SMC1 SMC2
Time Slot Assigner
TDMa
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
4Freescale Semiconductor
Features
— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)
– Caches are two-way, set- ass o ciat iv e
– Physically addre ssed
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity
— Memory management units (MM Us) with 8-entry translation lookaside buffers (TLBs) and
fully-associative instruction and data TLBs
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and
8 Mbytes; 16 virtual address spaces and eight protection groups
• Advanced on-chip emulation debug mode
• Data bus dynamic bus sizing for 8, 16, and 32-bit buses
— Supports traditional 68000 big-endian, tra ditional x86 little-endian and modified little-endian
memory systems
— Twenty-six external address lines
• Completely static design (0–80 MHz operation)
• System inte gration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test acces s port (JTAG)
• Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM
(SDRAM), static random-access memory (SRAM ), electrically programmable read-only
memory (EP RO M), fla sh EPR O M, etc.
— Memory controller programmable to support most size and speed memory interfaces
— Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
— Variable block sizes, 32 Kbytes to 256 Mbytes
— Selectable write protection
— On-c hip bus arbiter supports one external bus master
— Special features for burst mode support
• Genera l-pur pose timers
— F our 16-bit timers or two 32-bit timers
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 5
Features
— Gate mode can enable/disable counting
— Interr upt can be masked on reference match and event capture
• Interrupts
— Eight exter nal interr upt request (IR Q) lines
— Twelve port pins with interrupt capability
— F ifteen internal interrupt sources
— Programmable priority among SCCs and USB
— Programmable highest-priority request
• S ingl e so cke t P CMC I A -ATA in t erface
— Master (socket) interface, release 2.1 complian t
— Si n g l e P C MCIA so c k et
— Supports eight memory or I/O windows
• Communications processor module (CPM)
— 32- bit, Harvard architecture, scalar RISC communications processor (CP)
— P rotocol-specific command sets (for example, GRACEFUL STOP TRANSMIT stops transmission
aft er the current frame is finishe d or immediately if no frame is being sent and CLOSE RXBD
closes the recei ve buffer descriptor)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— Twenty serial DMA (SDMA) channels for the serial controllers , including eight for the four
USB endpoints
— Three parallel I/O registers with open-drain capability
• Four independent baud-rate generators (BRGs)
— Can be connected to any SCC, SMC, or USB
— Allow changes during opera tion
— Autobaud support option
• Two SCCs (serial communica tions controllers)
— E thernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC™ (a ll channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk®
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (I rDA)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
6Freescale Semiconductor
Features
• QUICC multichannel controller (QMC) microcode features
— Up to 64 independent communication channels on a single SCC
— Arbitrary mapping of 0–31 cha nnels to any of 0–31 TDM time slots
— Supports either transparent or HDLC protocols for each channel
— I ndependent TxBDs/Rx and event/interr upt reporting for each channel
• One universal serial bus controller (USB )
— Supports host controller and slave modes a t 1.5 Mbps and 12 Mbps
• Two serial management controllers (SMCs)
— UART
— Transparent
— General circuit inte rface ( GCI ) controller
— Can be c onnected to the time-division-multiplexed (TDM) channel
• One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multimaster operation on the same bus
• One I2C® (interprocessor -integr ated circuit) port
— Supports master and slave modes
— Supports multimaster environment
• T ime slot assigner
— Allows SCCs and SMCs to run in multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN bas ic rate, ISDN primary rate, user-defined
— 1- or 8-bit resolution
— Allows independent transmit and r ece ive routing, frame syncs, clocking
— Allows dynamic cha nges
— Can be i nt er nall y connect ed to four serial channels (two SCCs and two SM Cs)
• Low-power support
— Ful l high: all units fully powered at high clock frequency
— Full low: all units fully powered at low clock frequency
— Doze : core functional units disabled except time base, decrementer, PLL, memor y controller,
real-time clock, and CPM in low-power standby
— Sl eep: all units disabled except rea l-time c lock and periodic interrupt timer. PLL i s active for
fast wake-up
— Dee p slee p: all units disabled including PLL, except the re al-time clock and periodic interr upt
timer
— Low-power stop: to provide lower power dissipation
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 7
Electrical and Thermal Characteristics
— Separate power supply input to operate internal logic at 2.2 V when operating at or below
25 MHz
— Can be dynamically s hifted between high frequency (3.3 V internal) and low frequency (2.2 V
internal) opera tion
• Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— The MPC850 can compare using the =, ≠, <, and > conditions to generate watchpoints
— Each watc hpoint can generate a breakpoint internally
• 3.3-V operation with 5-V TTL com pat ibility on all general purpose I/O pins.
3 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC850.
Table 2 provides the maximum ratings.
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an a ppropriate logic voltage level (for example, either GND or VCC). Table 3 provides
the package thermal characteristics for the M P C850.
Table 2. Maximum Ratings
(GND = 0V)
Rating Symbol Value Unit
Supply voltage VDDH -0.3 to 4.0 V
VDDL -0.3 to 4.0 V
KAPWR -0.3 to 4.0 V
VDDSYN -0.3 to 4.0 V
Input voltage 1
1
Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
CAUTION: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction
applies to power-up and normal operation (that is, if the MPC850 is unpowered, voltage greater than 2.5 V must not
be applied to its inputs).
Vin GND-0.3 to VDDH + 2.5 V V
Junction temperature 2
2
The MPC850, a high-frequency device in a BGA package, does not provide a guaranteed maximum ambient
temperature. Only maximum junction temperature is guaranteed. It is the responsibility of the user to consider power
dissipation and thermal management. Junction temperature ratings are the same regardless of frequency rating of
the device.
Tj0 to 95 (standard)
-40 to 95 (extended)
°C
Storage temperature range Tstg -55 to +150 °C
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
8Freescale Semiconductor
Thermal Characteristics
4 Thermal Characteristics
Table 3 shows the thermal characteristics for the MPC850.
Table 4 provides power dissipation information.
Table 5 provides the DC electrical characteristics for the MPC850.
Table 3. Thermal Characteristics
Characteristic Symbol Value Unit
Thermal resistance for BGA 1
1
For more information on the design of thermal vias on multilayer boards and BGA layout considerations in
general, refer to AN-1231/D, Plasti c Ball Gr id Array Applica ti on Note available from your local Freescale sales
office.
θJA 40 2
2 Assumes natural convection and a single layer board (no thermal vias).
°C/W
θJA 31 3
3
Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board
temperature rise of 20°C above ambient.
°C/W
θJA 24 4
4 Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board
temperature rise of 13°C above ambient.
TJ = TA + (PD •θJA)
PD = (VDD • IDD) + PI/O
where:
PI/O is the power dissipation on pins
°C/W
Thermal Resistance for BGA (junction-to-case) θJC 8°C/W
Table 4. Power Dissipation (PD)
Characteristic Frequency (MHz) Typical 1
1
Typical power dissipation is measured at 3.3V
Maximum 2
2
Maximum power dissipation is measured at 3.65 V
Unit
Power Dissipation
All Revisions
(1:1) Mode
33 TBD 515 mW
40 TBD 590 mW
50 TBD 725 mW
Table 5. DC Electrical Specifications
Characteristic Symbol Min Max Unit
Operating voltage at 40 MHz or less VDDH, VDDL,
KAPWR, VDDSYN
3.0 3.6 V
Operating voltage at 40 MHz or higher VDDH, VDDL,
KAPWR, VDDSYN
3.135 3.465 V
Input high voltage (address bus, data bus, EXTAL, EXTCLK,
and all bus control/status signals)
VIH 2.0 3.6 V
Input high voltage (all general purpose I/O and peripheral pins) VIH 2.0 5.5 V
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 9
Power Considerations
5 Power Considerations
The average chip-junction temper at ure , TJ, in °C can be obtained from the equation:
TJ = TA + (PD • θJA)(1)
where
TA = Ambient temperature, °C
Input low voltage VIL GND 0.8 V
EXTAL, EXTCLK input high voltage VIHC 0.7*(VCC) VCC+0.3 V
Input leakage current, Vin = 5.5 V (Except TMS, TRST, DSCK
and DSDI pins)
Iin — 100 µA
Input leakage current, Vin = 3.6V (Except TMS, TRST, DSCK
and DSDI pins)
IIn —10µA
Input leakage current, Vin = 0V (Except TMS, TRST, DSCK
and DSDI pins)
IIn —10µA
Input capacitance Cin —20pF
Output high voltage, IOH = -2.0 mA, VDDH = 3.0V
except XTAL, XFC, and open-drain pins
VOH 2.4 — V
Output low voltage
CLKOUT 3
IOL = 3.2 mA 1
IOL = 5.3 mA 2
IOL = 7.0 mA PA[14]/USBOE, PA[12]/TXD2
IOL = 8.9 mA TS, TA, TEA, BI, BB, HRESET, SRESET
VOL — 0.5 V
1
A[6:31], TSIZ0/REG, TSIZ1, D[0:31], DP[0:3]/IRQ[3:6], RD/WR, BURST, RSV/IRQ2, IP_B[0:1]/IWP[0:1]/VFLS[0:1],
IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3,
PA[15]/USBRXD, PA[13]/RXD2, PA[9]/L1TXDA/SMRXD2, PA[8]/L1RXDA/SMTXD2,
PA[7]/CLK1/TIN1/L1RCLKA/BRGO1, PA[6]/CLK2/TOUT1/TIN3, PA[5]/CLK3/TIN2/L1TCLKA/BRGO2,
PA[4]/CLK4/TOUT2/TIN4, PB[31]/SPISEL, PB[30]/SPICLK/TXD3, PB[29]/SPIMOSI /RXD3,
PB[28]/SPIMISO/BRGO3, PB[27]/I2CSDA/BRGO1, PB[26]/I2CSCL/BRGO2, PB[25]/SMTXD1/TXD3,
PB[24]/SMRXD1/RXD3, PB[23]/SMSYN1/SDACK1, PB[22]/SMSYN2/SDACK2, PB[19]/L1ST1,
PB[18]/RTS2/L1ST2, PB[17]/L1ST3, PB[16]/L1RQa/L1ST4, PC[15]/DREQ0/L1ST5, PC[14]/DREQ1/RTS2/L1ST6,
PC[13]/L1ST7/RTS3, PC[12]/L1RQa/L1ST8, PC[11]/USBRXP, PC[10]/TGATE1/USBRXN, PC[9]/CTS2,
PC[8]/CD2/TGATE1, PC[7]/USBTXP, PC[6]/USBTXN, PC[5]/CTS3/L1TSYNCA/SDACK1, PC[4]/CD3/L1RSYNCA,
PD[15], PD[14], PD[13], PD[12], PD[11], PD[10], PD[9], PD[8], PD[7], PD[6], PD[5], PD[4], PD[3]
2
BDIP/GPL_B5, BR, BG, FRZ/IRQ6, CS[0:5], CS6/CE1_B, CS7/CE2_B, WE0/BS_AB0/IORD, WE1/BS_AB1/IOWR,
WE2/BS_AB2/PCOE, WE3/BS_AB3/PCWE, GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A[2:3]/GPL_B[2:3]/CS[2:3], UPWAITA/GPL_A4/AS, UPWAITB/GPL_B4, GPL_A5, ALE_B/DSCK/AT1,
OP2/MODCK1/STS, OP3/MODCK2/DSDO
3 The MPC850 IBIS model must be used to accurately model the behavior of the Clkout output driver for the full and
half drive setting. Due to the nature of the Clkout output buffer, IOH and IOL for Clkout should be extracted from the
IBIS model at any output voltage level.
Table 5. DC Electrical Specifications (continued)
Characteristic Symbol Min Max Unit
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
10 Freescale Semiconductor
Bus Signal Timing
θJA = Package therma l resis ta nce, junction to ambient, °C/W
PD = PINT + PI/O
PINT = I DD x VDD, watts—chip internal power
PI/O = Power dissipation on input and output pins—user determined
For most applications PI/O < 0.3 • PINT and can be neglected. If PI/O is neglected, an approximate
relationship between PD and TJ is :
PD = K ÷ (TJ + 273 °C)(2)
Solving equations (1) and (2) for K gives:
K = PD • (TA + 273°C) + θJA • PD2(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving equations (1) and (2) iteratively for any value of TA.
5.1 Layout Practices
Each VCC pin on the MPC850 should be provided with a low-i mpedance path to the board’s supply. Each
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four
0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit t races connecting to chip VCC and GND should be kept to less t han half an
inch per capacitor lead. A f our-layer board is recommended, employi ng two inner layers as V CC and GND
planes.
All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in or der to minimize undershoot a nd reflections caused by these fast output
switching time s. This re comme ndation partic ularly applie s to the addre s s and data busses. Maximum PC
trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as
well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especi all y criti cal in sys tem s with higher capacitive loads because t hese l oads cr eat e higher tra nsi ent
curr e nts in the V CC and GND circuits. Pull up all unus ed inputs or signals that will be inputs during reset.
Special care should be ta ken to minimize the noise levels on the PL L supply pins.
6 Bus Signal Timing
Table 6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timing
information for other bus speeds can be interpolated by equation using the MPC850 Electrical
Specifications Spreadsheet found at http://www.mot.com/netcomm.
The maximum bus speed supported by the MPC850 is 50 MHz. Higher- speed parts must be operated in
half-speed bus mode (for example, an MPC850 used at 66 MHz must be configured for a 33 MHz bus).
The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated by 1 ns per 10
pF. Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet.
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 11
Bus Signal Timing
Table 6. Bus Operation Timing 1
Num Characteristic
50 MHz 66 MHz 80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min Max Min Max Min Max
B1 CLKOUT period 20 — 30.30 — 25 — — — ns
B1a EXTCLK to CLKOUT phase
skew (EXTCLK > 15 MHz and
MF <= 2)
-0.90 0.90 -0.90 0.90 -0.90 0.90 — 50.00 ns
B1b EXTCLK to CLKOUT phase
skew (EXTCLK > 10 MHz and
MF < 10)
-2.30 2.30 -2.30 2.30 -2.30 2.30 — 50.00 ns
B1c CLKOUT phase jitter (EXTCLK
> 15 MHz and MF <= 2) 2
-0.60 0.60 -0.60 0.60 -0.60 0.60 — 50.00 ns
B1d CLKOUT phase jitter 2-2.00 2.00 -2.00 2.00 -2.00 2.00 — 50.00 ns
B1e CLKOUT frequency jitter (MF <
10) 2
— 0.50 — 0.50 — 0.50 — 50.00 %
B1f CLKOUT frequency jitter (10 <
MF < 500) 2— 2.00 — 2.00 — 2.00 — 50.00 %
B1g CLKOUT frequency jitter (MF >
500) 2
— 3.00 — 3.00 — 3.00 — 50.00 %
B1h Frequency jitter on EXTCLK 3 — 0.50 — 0.50 — 0.50 — 50.00 %
B2 CLKOUT pulse width low 8.00 — 12.12 — 10.00 — — 50.00 ns
B3 CLKOUT width high 8.00 — 12.12 — 10.00 — — 50.00 ns
B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 50.00 ns
B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 50.00 ns
B7 CLKOUT to A[6–31],
RD/WR, BURST, D[0–31],
DP[0–3] invalid
5.00 — 7.58 — 6.25 — 0.250 50.00 ns
B7a CLKOUT to TSIZ[0–1], REG,
RSV, AT[0–3], BDIP, PTR
invalid
5.00 — 7.58 — 6.25 — 0.250 50.00 ns
B7b CLKOUT to BR, BG, FRZ,
VFLS[0–1], VF[0–2] IWP[0–2],
LWP[0–1], STS invalid 4
5.00 — 7.58 — 6.25 — 0.250 50.00 ns
B8 CLKOUT to A[6–31],
RD/WR, BURST, D[0–31],
DP[0–3] valid
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
B8a CLKOUT to TSIZ[0–1], REG,
RSV, AT[0–3] BDIP, PTR valid
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
B8b CLKOUT to BR, BG,
VFLS[0–1], VF[0–2], IWP[0–2],
FRZ, LWP[0–1], STS valid 4
5.00 11.74 7.58 14.33 6.25 13.00 0.250 50.00 ns
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
12 Freescale Semiconductor
Bus Signal Timing
B9 CLKOUT to A[6–31] RD/WR,
BURST
, D[0–31], DP[0–3],
TSIZ[0–1], REG
, RSV, AT[0–3],
PTR high-Z
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
B11 CLKOUT to TS, BB assertion 5.00 11.00 7.58 13.58 6.25 12.25 0.250 50.00 ns
B11a CLKOUT to TA, BI assertion,
(When driven by the memory
controller or PCMCIA interface)
2.50 9.25 2.50 9.25 2.50 9.25 — 50.00 ns
B12 CLKOUT to TS, BB negation 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
B12a CLKOUT to TA, BI negation
(when driven by the memory
controller or PCMCIA interface)
2.50 11.00 2.50 11.00 2.50 11.00 — 50.00 ns
B13 CLKOUT to TS, BB high-Z 5.00 19.00 7.58 21.58 6.25 20.25 0.250 50.00 ns
B13a CLKOUT to TA, BI high-Z,
(when driven by the memory
controller or PCMCIA interface)
2.50 15.00 2.50 15.00 2.50 15.00 — 50.00 ns
B14 CLKOUT to TEA assertion 2.50 10.00 2.50 10.00 2.50 10.00 — 50.00 ns
B15 CLKOUT to TEA high-Z 2.50 15.00 2.50 15.00 2.50 15.00 — 50.00 ns
B16 TA, BI valid to CLKOUT(setup
time) 5
9.75 — 9.75 — 9.75 — — 50.00 ns
B16a TEA, KR, RETRY, valid to
CLKOUT (setup time) 5
10.00 — 10.00 — 10.00 — — 50.00 ns
B16b BB, BG, BR valid to CLKOUT
(setup time) 6 8.50 — 8.50 — 8.50 — — 50.00 ns
B17 CLKOUT to TA, TEA, BI, BB,
BG, BR valid (Hold time).5
1.00 — 1.00 — 1.00 — — 50.00 ns
B17a CLKOUT to KR, RETRY, except
TEA valid (hold time)
2.00 — 2.00 — 2.00 — — 50.00 ns
B18 D[0–31], DP[0–3] valid to
CLKOUT rising edge (setup
time) 7
6.00 — 6.00 — 6.00 — — 50.00 ns
B19 CLKOUT rising edge to
D[0–31], DP[0–3] valid (hold
time) 7
1.00 — 1.00 — 1.00 — — 50.00 ns
B20 D[0–31], DP[0–3] valid to
CLKOUT falling edge (setup
time) 8
4.00 — 4.00 — 4.00 — — 50.00 ns
B21 CLKOUT falling edge to
D[0–31], DP[0–3] valid (hold
time) 8
2.00 — 2.00 — 2.00 — — — —
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
50 MHz 66 MHz 80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min Max Min Max Min Max
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 13
Bus Signal Timing
B22 CLKOUT rising edge to CS
asserted GPCM ACS = 00
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
B22a CLKOUT falling edge to CS
asserted GPCM ACS = 10,
TRLX = 0,1
— 8.00 — 8.00 — 8.00 — 50.00 ns
B22b CLKOUT falling edge to CS
asserted GPCM ACS = 11,
TRLX = 0, EBDF = 0
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
B22c CLKOUT falling edge to CS
asserted GPCM ACS = 11,
TRLX = 0, EBDF = 1
7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns
B23 CLKOUT rising edge to CS
negated GPCM read access,
GPCM write access ACS = 00,
TRLX = 0 & CSNT = 0
2.00 8.00 2.00 8.00 2.00 8.00 — 50.00 ns
B24 A[6–31] to CS asserted GPCM
ACS = 10, TRLX = 0.
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
B24a A[6–31] to CS asserted GPCM
ACS = 11, TRLX = 0
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
B25 CLKOUT rising edge to OE,
WE[0–3] asserted
— 9.00 — 9.00 — 9.00 — 50.00 ns
B26 CLKOUT rising edge to OE
negated
2.00 9.00 2.00 9.00 2.00 9.00 — 50.00 ns
B27 A[6–31] to CS asserted GPCM
ACS = 10, TRLX = 1
23.00 — 36.00 — 29.00 — 1.250 50.00 ns
B27a A[6–31] to CS asserted GPCM
ACS = 11, TRLX = 1
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
B28 CLKOUT rising edge to
WE[0–3] negated GPCM write
access CSNT = 0
— 9.00 — 9.00 — 9.00 — 50.00 ns
B28a CLKOUT falling edge to
WE[0–3] negated GPCM write
access TRLX = 0,1 CSNT = 1,
EBDF = 0
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
B28b CLKOUT falling edge to CS
negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS =
10 or ACS = 11, EBDF = 0
— 12.00 — 14.00 — 13.00 0.250 50.00 ns
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
50 MHz 66 MHz 80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min Max Min Max Min Max
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
14 Freescale Semiconductor
Bus Signal Timing
B28c CLKOUT falling edge to
WE[0–3] negated GPCM write
access TRLX = 0,1 CSNT = 1
write access TRLX = 0, CSNT =
1, EBDF = 1
7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns
B28d CLKOUT falling edge to CS
negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS =
10 or ACS = 11, EBDF = 1
— 14.00 — 18.00 — 16.00 0.375 50.00 ns
B29 WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, CSNT = 0
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
B29a WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 0 CSNT = 1,
EBDF = 0
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
B29b CS negated to D[0–31],
DP[0–3], high-Z GPCM write
access, ACS = 00, TRLX = 0 &
CSNT = 0
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
B29c CS negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
B29d WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
EBDF = 0
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
B29e CS negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
B29f WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1
5.00 — 9.00 — 7.00 — 0.375 50.00 ns
B29g CS negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1
5.00 — 9.00 — 7.00 — 0.375 50.00 ns
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
50 MHz 66 MHz 80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min Max Min Max Min Max
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 15
Bus Signal Timing
B29h WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1
25.00 — 39.00 — 31.00 — 1.375 50.00 ns
B29i CS negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1
25.00 — 39.00 — 31.00 — 1.375 50.00 ns
B30 CS, WE[0–3] negated to
A[6–31] invalid
GPCM write access 9
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
B30a WE[0–3] negated to A[6–31]
invalid
GPCM write access, TRLX = 0,
CSNT = 1, CS negated to
A[6–31] invalid GPCM write
access TRLX = 0, CSNT =1,
ACS = 10 or ACS = 11, EBDF =
0
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
B30b WE[0–3] negated to A[6–31]
invalid
GPCM write access, TRLX = 1,
CSNT = 1. CS negated to
A[6–31] Invalid GPCM write
access TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
B30c WE[0–3] negated to A[6–31]
invalid
GPCM write access, TRLX = 0,
CSNT = 1. CS negated to
A[6–31] invalid GPCM write
access, TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1
5.00 — 8.00 — 6.00 — 0.375 50.00 ns
B30d WE[0–3] negated to A[6–31]
invalid GPCM write access
TRLX = 1, CSNT =1, CS
negated to A[6–31] invalid
GPCM write access TRLX = 1,
CSNT = 1, ACS = 10 or ACS =
11, EBDF = 1
25.00 — 39.00 — 31.00 — 1.375 50.00 ns
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
50 MHz 66 MHz 80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min Max Min Max Min Max
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
16 Freescale Semiconductor
Bus Signal Timing
B31 CLKOUT falling edge to CS
valid - as requested by control
bit CST4 in the corresponding
word in the UPM
1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns
B31a CLKOUT falling edge to CS
valid - as requested by control
bit CST1 in the corresponding
word in the UPM
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
B31b CLKOUT rising edge to CS valid
- as requested by control bit
CST2 in the corresponding
word in the UPM
1.50 8.00 1.50 8.00 1.50 8.00 — 50.00 ns
B31c CLKOUT rising edge to CS valid
- as requested by control bit
CST3 in the corresponding
word in the UPM
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
B31d CLKOUT falling edge to CS
valid - as requested by control
bit CST1 in the corresponding
word in the UPM EBDF = 1
9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns
B32 CLKOUT falling edge to BS
valid - as requested by control
bit BST4 in the corresponding
word in the UPM
1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns
B32a CLKOUT falling edge to BS
valid - as requested by control
bit BST1 in the corresponding
word in the UPM, EBDF = 0
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
B32b CLKOUT rising edge to BS valid
- as requested by control bit
BST2 in the corresponding
word in the UPM
1.50 8.00 1.50 8.00 1.50 8.00 — 50.00 ns
B32c CLKOUT rising edge to BS valid
- as requested by control bit
BST3 in the corresponding
word in the UPM
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
B32d CLKOUT falling edge to BS
valid - as requested by control
bit BST1 in the corresponding
word in the UPM, EBDF = 1
9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns
B33 CLKOUT falling edge to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
50 MHz 66 MHz 80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min Max Min Max Min Max
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 17
Bus Signal Timing
B33a CLKOUT rising edge to GPL
valid - as requested by control
bit GxT3 in the corresponding
word in the UPM
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
B34 A[6–31] and D[0–31] to CS valid
- as requested by control bit
CST4 in the corresponding
word in the UPM
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
B34a A[6–31] and D[0–31] to CS valid
- as requested by control bit
CST1 in the corresponding
word in the UPM
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
B34b A[6–31] and D[0–31] to CS valid
- as requested by CST2 in the
corresponding word in UPM
13.00 — 21.00 — 17.00 — 0.750 50.00 ns
B35 A[6–31] to CS valid - as
requested by control bit BST4 in
the corresponding word in UPM
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
B35a A[6–31] and D[0–31] to BS valid
- as requested by BST1 in the
corresponding word in the UPM
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
B35b A[6–31] and D[0–31] to BS valid
- as requested by control bit
BST2 in the corresponding
word in the UPM
13.00 — 21.00 — 17.00 — 0.750 50.00 ns
B36 A[6–31] and D[0–31] to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
B37 UPWAIT valid to CLKOUT
falling edge 10
6.00 — 6.00 — 6.00 — — 50.00 ns
B38 CLKOUT falling edge to
UPWAIT valid 10
1.00 — 1.00 — 1.00 — — 50.00 ns
B39 AS valid to CLKOUT rising edge
11 7.00 — 7.00 — 7.00 — — 50.00 ns
B40 A[6–31], TSIZ[0–1], RD/WR,
BURST
, valid to CLKOUT rising
edge.
7.00 — 7.00 — 7.00 — — 50.00 ns
B41 TS valid to CLKOUT rising edge
(setup time)
7.00 — 7.00 — 7.00 — — 50.00 ns
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
50 MHz 66 MHz 80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min Max Min Max Min Max
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
18 Freescale Semiconductor
Bus Signal Timing
B42 CLKOUT rising edge to TS valid
(hold time)
2.00 — 2.00 — 2.00 — — 50.00 ns
B43 AS negation to memory
controller signals negation
—TBD—TBDTBD— — 50.00 ns
1
The minima provided assume a 0 pF load, whereas maxima assume a 50pF load. For frequencies not marked on
the part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC
parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to
be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the
part. The following equations should be used in these calculations.
For a frequency F, the following equations should be applied to each one of the above parameters:
For minima:
For maxima:
where:
D is the parameter value to the frequency required in ns
F is the operation frequency in MHz
D50 is the parameter value defined for 50 MHz
CAP LOAD is the capacitance load on the signal in question.
FFACTOR is the one defined for each of the parameters in the table.
2
Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value.
3
If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.
4
The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter. The timing for
BG output is relevant when the MPC850 is selected to work with internal bus arbiter.
5
The setup times required for TA, TEA, and BI are relevant only when they are supplied by an external device (and
not when the memory controller or the PCMCIA interface drives them).
6
The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter. The
timing for BG input is relevant when the MPC850 is selected to work with the external bus arbiter.
7
The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input
signal is asserted.
8
The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data beats where DLT3
= 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.
9
The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'.
10 The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in
B37 and B38 are specified to enable the freeze of the UPM output signals.
11 The AS signal is considered asynchronous to CLKOUT.
Table 6. Bus Operation Timing 1 (continued)
Num Characteristic
50 MHz 66 MHz 80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min Max Min Max Min Max
D =FFACTOR x 1000
F(D50 - 2 0 x F FA C TO R )
+
D =FFACTOR x 1000
F(D50 - 20 x FFACTOR)
++
1ns(CAP LOAD - 50) / 10
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 19
Bus Signal Timing
Figure 2 is the control timing diagra m.
Figure 2. Control Timing
Figure 3 provide s the timing for the external clock.
Figure 3. External Clock Timing
CLKOUT
Outputs
A
B
2.0 V 0.8 V 0.8 V 2. 0 V
2.0 V
0.8 V 2. 0 V
0. 8 V
Outputs 2.0 V
0.8 V 2.0 V
0.8 V
B
A
Inputs 2.0 V
0.8 V 2.0 V
0.8 V
D
C
Inputs 2. 0 V
0. 8 V 2.0 V
0.8 V
C
D
A Maximum output delay specification
B Minimum output hold time
C Minimum input setup time specification
D Minimum input hold time specification
CLKOUT
B1
B5
B3
B4
B1
B2
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
20 Freescale Semiconductor
Bus Signal Timing
Figure 4 provides the timing for the synchronous output signals.
Figure 4. Synchronous Output Signals Timing
Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals.
Figure 5. Synchronous Active Pullup and Open-Drain Outputs Signals Timing
CLKOUT
Output
Signals
Output
Signals
Output
Signals
B8
B7 B9
B8a
B9B7a
B8b
B7b
CLKOUT
TS, BB
TA, BI
TEA
B13
B12B11
B11a B12a
B13a
B15
B14
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 21
Bus Signal Timing
Figure 6 provides the timing for the synchronous input signals.
Figure 6. Synchronous Input Signals Timing
Figure 7 provides normal case timing for input dat a.
Figure 7. Input Data Timing in Normal Case
CLKOUT
TA, BI
TEA, KR,
RETRY
BB, BG, BR
B16
B17
B16a
B17a
B16b
B17
CLKOUT
TA
D[0:31],
DP[0:3]
B16
B17
B19
B18
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
22 Freescale Semiconductor
Bus Signal Timing
Figure 8 provides the timing for the input data controlled by the UPM in the memory controller.
Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller
Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM
factors.
Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00)
CLKOUT
TA
D[0:31],
DP[0:3]
B20
B21
CLKOUT
A[6:31]
CSx
OE
WE[0:3]
TS
D[0:31],
DP[0:3]
B11 B12
B23
B8
B22
B26
B19
B18
B25
B28
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 23
Bus Signal Timing
Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)
Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)
CLKOUT
A[6:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B8
B22a B23
B26
B19B18
B25B24
CLKOUT
A[6:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B22b
B8
B22c B23
B24a B25 B26
B19B18
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
24 Freescale Semiconductor
Bus Signal Timing
Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11)
CLKOUT
A[6:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B8
B22a
B27
B27a
B22bB22c B19B18
B26
B23
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 25
Bus Signal Timing
Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM
factors.
Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)
CLKOUT
A[6:31]
CSx
WE[0:3]
OE
TS
D[0:31],
DP[0:3]
B11
B8
B22 B23
B12
B30
B28B25
B26
B8 B9
B29a
B29b
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
26 Freescale Semiconductor
Bus Signal Timing
Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)
B23
B30aB30c
CLKOUT
A[6:31]
CSx
OE
WE[0:3]
TS
D[0:31],
DP[0:3]
B11
B8
B22
B12
B28bB28d
B25
B26
B8
B28a
B9
B28c
B29cB29g
B29aB29f
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 27
Bus Signal Timing
Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)
B23B22
B8
B12B11
CLKOUT
A[6:31]
CSx
WE[0:3]
TS
OE
D[0:31],
DP[0:3]
B30dB30b
B28bB28d
B25 B29e B29i
B26 B29d
B28aB28c B9B8
B29b
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
28 Freescale Semiconductor
Bus Signal Timing
Figure 16 provide s the timing for the external bus controlled by the UPM.
Figure 16. External Bus Timing (UPM Controlled Signals)
CLKOUT
CSx
B31d
B8
B31
B34
B32b
GPL_A[0–5],
GPL_B[0–5]
BS_A[0:3],
BS_B[0:3]
A[6:31]
B31c
B31b
B34a
B32
B32aB32d
B34b
B36
B35b
B35a
B35
B33
B32c
B33a
B31a
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 29
Bus Signal Timing
Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing
Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing
CLKOUT
CSx
UPWAIT
GPL_A[0–5],
GPL_B[0–5]
BS_A[0:3],
BS_B[0:3]
B37
B38
CLKOUT
CSx
UPWAIT
GPL_A[0–5],
GPL_B[0–5]
BS_A[0:3],
BS_B[0:3]
B37
B38
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
30 Freescale Semiconductor
Bus Signal Timing
Figure 19 provides the timing for the synchronous external master access controlled by the GPCM.
Figure 19. Synchronous External Master Access Timing (GPCM Handled ACS = 00)
Figure 20 provides the timing for the asynchronous external master memory access controlled by the
GPCM.
Figure 20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Figure 21 provides the timing for the asynchronous external master control signals negation.
Figure 21. Asynchronous External Master—Control Signals Negation Timing
CLKOUT
TS
A[6:31],
TSIZ[0:1],
R/W, BURST
CSx
B41 B42
B40
B22
CLKOUT
AS
A[6:31],
TSIZ[0:1],
R/W
CSx
B39
B40
B22
AS
CSx, WE [0:3],
OE, GPLx ,
BS[0:3]
B43
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 31
Bus Signal Timing
Table 7 provides interrupt timing for the MPC850.
Figure 22 provide s the interrupt detection timing for the external level-sens itive lines.
Figure 22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 23 provide s the interrupt detection timing for the external edge-sensi tive lines.
Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines
Table 7. Interrupt Timing
Num Characteristic 1
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no
direct relation with the total system interrupt latency that the MPC850 is able to support
50 MHz 66MHz 80 MHz
Unit
Min Max Min Max Min Max
I39 IRQx valid to CLKOUT rising edge (set up time) 6.00 — 6.00 — 6.00 — ns
I40 IRQx hold time after CLKOUT. 2.00 — 2.00 — 2.00 — ns
I41 IRQx pulse width low 3.00 — 3.00 — 3.00 — ns
I42 IRQx pulse width high 3.00 — 3.00 — 3.00 — ns
I43 IRQx edge-to-edge time 80.00 — 121.0 — 100.0 — ns
CLKOUT
IRQx
I39
I40
CLKOUT
IRQx
I39
I41 I42
I43
I43
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
32 Freescale Semiconductor
Bus Signal Timing
Table 8 shows the PCMCIA timing for the MPC850.
Table 8. PCMCIA Timing
Num Characteristic
50MHz 66MHz 80 MHz
FFACTOR Unit
Min Max Min Max Min Max
P44 A[6–31], REG valid to PCMCIA strobe
asserted. 1
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAIT_B signal is detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.
See PCMCIA Interface in the MPC850 PowerQUICC User’s Manual.
13.00 — 21.00 — 17.00 — 0.750 ns
P45 A[6–31], REG valid to ALE negation.118.00 — 28.00 — 23.00 — 1.000 ns
P46 CLKOUT to REG valid 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns
P47 CLKOUT to REG Invalid. 6.00 — 9.00 — 7.00 — 0.250 ns
P48 CLKOUT to CE1, CE2 asserted. 5.00 13.00 8.00 16.00 6.00 14.00 0.250
P49 CLKOUT to CE1, CE2 negated. 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns
P50 CLKOUT to PCOE, IORD, PCWE,
IOWR assert time.
— 11.00 — 11.00 — 11.00 — ns
P51 CLKOUT to PCOE, IORD, PCWE,
IOWR negate time.
2.00 11.00 2.00 11.00 2.00 11.00 — ns
P52 CLKOUT to ALE assert time 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns
P53 CLKOUT to ALE negate time — 13.00 — 16.00 — 14.00 0.250 ns
P54 PCWE, IOWR negated to D[0–31]
invalid.1
3.00 — 6.00 — 4.00 — 0.250 ns
P55 WAIT_B valid to CLKOUT rising edge.18.00 — 8.00 — 8.00 — — ns
P56 CLKOUT rising edge to WAIT_B
invalid.1
2.00 — 2.00 — 2.00 — — ns
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 33
Bus Signal Timing
Figure 24 provides the PCMCIA access cycle timing for the external bus read.
Figure 24. PCMCIA Access Cycles Timing External Bus Read
CLKOUT
A[6:31]
REG
CE1/CE2
PCOE, IOR D
TS
D[0:31]
ALE
B19B18
P53P52 P52
P51P50
P48 P49
P46 P45
P44
P47
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
34 Freescale Semiconductor
Bus Signal Timing
Figure 25 provides the PCMCIA access cycle timing for the external bus write.
Figure 25. PCMCIA Access Cycles Timing External Bus Write
Figure 26 provide s the PCMCIA WAIT signals detection timing.
Figure 26. PCMCIA WAIT Signal Detection Timing
CLKOUT
A[6:31]
REG
CE1/CE2
PCWE, I OWR
TS
D[0:31]
ALE
B9B8
P53P52 P52
P51P50
P48 P49
P46 P45
P44
P47
P54
CLKOUT
WAIT_B
P55
P56
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 35
Bus Signal Timing
Table 9 shows the PCMCIA port timing for the MPC850.
Figure 27 provides the PCMCIA output port timing for the MPC850.
Figure 27. PCMCIA Output Port Timing
Figure 28 provides the PCMCIA output port timing for the MPC850.
Figure 28. PCMCIA Input Port Timing
Table 9. PCMCIA Port Timing
Num Characteristic
50 MHz 66 MHz 80 MHz
Unit
Min Max Min Max Min Max
P57 CLKOUT to OPx valid — 19.00 — 19.00 — 19.00 ns
P58 HRESET negated to OPx drive 1
1
OP2 and OP3 only.
18.00 — 26.00 — 22.00 — ns
P59 IP_Xx valid to CLKOUT rising edge 5.00 — 5.00 — 5.00 — ns
P60 CLKOUT rising edge to IP_Xx invalid 1.00 — 1.00 — 1.00 — ns
CLKOUT
HRESET
Output
Signals
OP2, OP3
P57
P58
CLKOUT
Input
Signals
P59
P60
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
36 Freescale Semiconductor
Bus Signal Timing
Table 10 shows the debug port timing for the MPC850.
Figure 29 provides the input timing for the debug port clock.
Figure 29. Debug Port Clock Input Timing
Figure 30 provides the timing for the debug port.
Figure 30. Debug Port Timings
Table 10. Debug Port Timing
Num Characteristic
50 MHz 66 MHz 80 MHz
Unit
Min Max Min Max Min Max
D61 DSCK cycle time 60.00 — 91.00 — 75.00 — ns
D62 DSCK clock pulse width 25.00 — 38.00 — 31.00 — ns
D63 DSCK rise and fall times 0.00 3.00 0.00 3.00 0.00 3.00 ns
D64 DSDI input data setup time 8.00 — 8.00 — 8.00 — ns
D65 DSDI data hold time 5.00 — 5.00 — 5.00 — ns
D66 DSCK low to DSDO data valid 0.00 15.00 0.00 15.00 0.00 15.00 ns
D67 DSCK low to DSDO invalid 0.00 2.00 0.00 2.00 0.00 2.00 ns
DSCK
D61
D63
D62
D62
D63
DSCK
DSDI
DSDO
D64
D65
D66
D67
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 37
Bus Signal Timing
Table 11 shows the reset timing for the MPC850.
Table 11. Reset Timing
Num Characteristic
50 MHz 66MHz 80 MHz
FFACTOR Unit
MinMaxMinMaxMinMax
R69 CLKOUT to HRESET high impedance — 20.00 — 20.00 — 20.00 — ns
R70 CLKOUT to SRESET high impedance — 20.00 — 20.00 — 20.00 — ns
R71 RSTCONF pulse width 340.00 — 515.00 — 425.00 — 17.000 ns
R72 —————— —
R73 Configuration data to HRESET rising
edge set up time
350.00 — 505.00 — 425.00 — 15.000 ns
R74 Configuration data to RSTCONF rising
edge set up time
350.00 — 350.00 — 350.00 — — ns
R75 Configuration data hold time after
RSTCONF negation
0.00 — 0.00 — 0.00 — — ns
R76 Configuration data hold time after
HRESET negation
0.00 — 0.00 — 0.00 — — ns
R77 HRESET and RSTCONF asserted to
data out drive
— 25.00 — 25.00 — 25.00 — ns
R78 RSTCONF negated to data out high
impedance.
— 25.00 — 25.00 — 25.00 — ns
R79 CLKOUT of last rising edge before chip
tristates HRESET to data out high
impedance.
— 25.00 — 25.00 — 25.00 — ns
R80 DSDI, DSCK set up 60.00 — 90.00 — 75.00 — 3.000 ns
R81 DSDI, DSCK hold time 0.00 — 0.00 — 0.00 — — ns
R82 SRESET negated to CLKOUT rising
edge for DSDI and DSCK sample
160.00 — 242.00 — 200.00 — 8.000 ns
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
38 Freescale Semiconductor
Bus Signal Timing
Figure 31 shows the reset timing for the data bus configuration.
Figure 31. Reset Timing—Configuration from Data Bus
Figure 32 provide s the reset timing for the data bus weak drive during configuration.
Figure 32. Reset Timing—Data Bus Weak Drive during Configuration
HRESET
RSTCONF
D[0:31] (IN)
R71
R74
R73
R75
R76
CLKOUT
HRESET
D[ 0:31] (OUT)
(Weak)
RSTCONF
R69
R79
R77 R78
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 39
IEEE 1149.1 Electrical Specifications
Figure 33 provides the reset timing for the debug port configuration.
Figure 33. Reset Timing—Debug Port Configuration
7 IEEE 1149.1 Electrical Specifications
Table 12 provides the JTAG timings for the MPC850 as shown in Figure 34 to Figure 37.
Table 12. JTAG Timing
Num Characteristic
50 MHz 66MHz 80 MHz
Unit
Min Max Min Max Min Max
J82 TCK cycle time 100.00 — 100.00 — 100.00 — ns
J83 TCK clock pulse width measured at 1.5 V 40.00 — 40.00 — 40.00 — ns
J84 TCK rise and fall times 0.00 10.00 0.00 10.00 0.00 10.00 ns
J85 TMS, TDI data setup time 5.00 — 5.00 — 5.00 — ns
J86 TMS, TDI data hold time 25.00 — 25.00 — 25.00 — ns
J87 TCK low to TDO data valid — 27.00 — 27.00 — 27.00 ns
J88 TCK low to TDO data invalid 0.00 — 0.00 — 0.00 — ns
J89 TCK low to TDO high impedance — 20.00 — 20.00 — 20.00 ns
J90 TRST assert time 100.00 — 100.00 — 100.00 — ns
J91 TRST setup time to TCK low 40.00 — 40.00 — 40.00 — ns
J92 TCK falling edge to output valid — 50.00 — 50.00 — 50.00 ns
J93 TCK falling edge to output valid out of high
impedance
— 50.00 — 50.00 — 50.00 ns
J94 TCK falling edge to output high impedance — 50.00 — 50.00 — 50.00 ns
J95 Boundary scan input valid to TCK rising edge 50.00 — 50.00 — 50.00 — ns
J96 TCK rising edge to boundary scan input invalid 50.00 — 50.00 — 50.00 — ns
CLKOUT
SRESET
DSCK, DSDI
R70
R82
R80R80
R81 R81
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
40 Freescale Semiconductor
IEEE 1149.1 Electrical Specifications
Figure 34. JTAG Test Clock Input Timing
Figure 35. JTAG Test Access Port Timing Diagram
Figure 36. JTAG TRST Timing Diagram
TCK
J82 J83
J82 J83
J84 J84
TCK
TMS, TDI
TDO
J85
J86
J87
J88 J89
TCK
TRST
J91
J90
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 41
CPM Electrical Characteristics
Figure 37. Boundary Scan (JTAG) Timing Diagram
8 CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications processor module
(CPM) of the MPC850.
8.1 PIO AC Electrical Specifications
Table 13 provides the parallel I/O timings for the MPC850 as shown in Figure 38.
Table 13. Parallel I/O Timing
Num Characteristic
All Frequencies
Unit
Min Max
29 Data-in setup time to clock high 15 — ns
30 Data-in hold time from clock high 7.5 — ns
31 Clock low to data-out valid (CPU writes data, control, or direction) — 25 ns
TCK
Output
Signals
Output
Signals
Input
Signals
J92 J94
J93
J95 J96
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
42 Freescale Semiconductor
CPM Electrical Characteristics
Figure 38. Parallel I/O Data-In/Data-Out Timing Diagram
8.2 IDMA Controller AC Electrical Specifications
Table 14 provides the IDMA controller timings as shown in Figure 39 to Figure 42.
Figure 39. IDMA External Requests Timing Diagram
Table 14. IDMA Controller Timing
Num Characteristic
All Frequencies
Unit
Min Max
40 DREQ setup time to clock high 7.00 — ns
41 DREQ hold time from clock high 3.00 — ns
42 SDACK assertion delay from clock high — 12.00 ns
43 SDACK negation delay from clock low — 12.00 ns
44 SDACK negation delay from TA low — 20.00 ns
45 SDACK negation delay from clock high — 15.00 ns
46 TA assertion to falling edge of the clock setup time (applies to external TA)7.00 — ns
CLKOUT
DATA-IN
29
31
30
DATA-OUT
41
40
DREQ
(Input)
CLKOUT
(Output)
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 43
CPM Electrical Characteristics
Figure 40. SDACK Timing Diagram—Peripheral Write, TA Sampled Low at the Falling Edge
of the Clock
DATA
42
46
43
CLKOUT
(Output)
TS
(Output)
R/W
(Output)
TA
(Output)
SDACK
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
44 Freescale Semiconductor
CPM Electrical Characteristics
Figure 41. SDACK Timing Diagram—Peripheral Write, TA Sampled High at the Falling Edge
of the Clock
Figure 42. SDACK Timing Diagram—Peripheral Read
DATA
42 44
CLKOUT
(Output)
TS
(Output)
R/W
(Output)
TA
(Output)
SDACK
DATA
42 45
CLKOUT
(Output)
TS
(Output)
R/W
(Output)
TA
(Output)
SDACK
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 45
CPM Electrical Characteristics
8.3 Baud Rate Generator AC Electrical Specifications
Table 15 provid es the baud rate genera tor timings as shown in Figure 43.
Figure 43. Baud Rate Generator Timing Diagram
8.4 Timer AC Electrical Specifications
Table 16 provid es the baud rate genera tor timings as shown in Figure 44.
Table 15. Baud Rate Generator Timing
Num Characteristic
All Frequencies
Unit
Min Max
50 BRGO rise and fall time — 10.00 ns
51 BRGO duty cycle 40.00 60.00 %
52 BRGO cycle 40.00 — ns
Table 16. Timer Timing
Num Characteristic
All Frequencies
Unit
Min Max
61 TIN/TGATE rise and fall time 10.00 — ns
62 TIN/TGATE low time 1.00 — clk
63 TIN/TGATE high time 2.00 — clk
64 TIN/TGATE cycle time 3.00 — clk
65 CLKO high to TOUT valid 3.00 25.00 ns
52
50
51
BRGOn
50
51
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
46 Freescale Semiconductor
CPM Electrical Characteristics
Figure 44. CPM General-Purpose Timers Timing Diagram
8.5 Serial Interface AC Electrical Specifications
Table 17 provides the serial interface timings as shown in Figure 45 to Figure 49.
Table 17. SI Timing
Num Characteristic
All Frequencies
Unit
Min Max
70 L1RCLK, L1TCLK frequency (DSC = 0) 1, 2 — SYNCCLK/2.
5
MHz
71 L1RCLK, L1TCLK width low (DSC = 0) 2P + 10 — ns
71a L1RCLK, L1TCLK width high (DSC = 0) 3 P + 10 — ns
72 L1TXD, L1ST
n
, L1RQ, L1xCLKO rise/fall time — 15.00 ns
73 L1RSYNC, L1TSYNC valid to L1xCLK edge Edge
(SYNC setup time)
20.00 — ns
74 L1xCLK edge to L1RSYNC, L1TSYNC, invalid
(SYNC hold time)
35.00 — ns
75 L1RSYNC, L1TSYNC rise/fall time — 15.00 ns
76 L1RXD valid to L1xCLK edge (L1RXD setup time) 17.00 — ns
77 L1xCLK edge to L1RXD invalid (L1RXD hold time) 13.00 — ns
78 L1xCLK edge to L1ST
n
valid 4 10.00 45.00 ns
78A L1SYNC valid to L1ST
n
valid 10.00 45.00 ns
79 L1xCLK edge to L1ST
n
invalid 10.00 45.00 ns
80 L1xCLK edge to L1TXD valid 10.00 55.00 ns
80A L1TSYNC valid to L1TXD valid 410.00 55.00 ns
81 L1xCLK edge to L1TXD high impedance 0.00 42.00 ns
CLKOUT
TIN/TGATE
(Input)
TOUT
(Output)
64
65
61
626361
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 47
CPM Electrical Characteristics
Figure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
82 L1RCLK, L1TCLK frequency (DSC =1) — 16.00 or
SYNCCLK/2
MHz
83 L1RCLK, L1TCLK width low (DSC =1) P + 10 — ns
83A L1RCLK, L1TCLK width high (DSC = 1)3P + 10 — ns
84 L1CLK edge to L1CLKO valid (DSC = 1) — 30.00 ns
85 L1RQ valid before falling edge of L1TSYNC41.00 — L1TCLK
86 L1GR setup time242.00 — ns
87 L1GR hold time 42.00 — ns
88 L1xCLK edge to L1SYNC valid (FSD = 00) CNT =
0000, BYT = 0, DSC = 0)
—0.00ns
1
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
2
These specs are valid for IDL mode only.
3
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
4
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC,
whichever is later.
Table 17. SI Timing (continued)
Num Characteristic
All Frequencies
Unit
Min Max
L1RxD
(Input)
79
76
7774
L1RCLK
(FE=0, CE=0)
(Input)
L1RCLK
(FE=1, CE=1)
(Input)
L1RSYNC
(Input)
L1ST
n
(Output)
71 70
RFSD=1
75
72
73
78
BIT0
71a
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
48 Freescale Semiconductor
CPM Electrical Characteristics
Figure 46. SI Receive Timing with Double-Speed Clocking (DSC = 1)
L1RXD
(Input)
L1RCLK
(FE=1, CE=1)
(Input)
L1RCLK
(FE=0, CE=0)
(Input)
L1RSYNC
(Input)
L1ST(4-1)
(Output)
72
RFSD=1
75
73
74 77
78
76
79
83a
82
L1CLKO
(Output)
84
BIT0
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 49
CPM Electrical Characteristics
Figure 47. SI Transmit Timing Diagram
L1TxD
(Output)
79
8180a
L1TCLK
(FE=0, CE=0)
(Input)
L1TCLK
(FE=1, CE=1)
(Input)
L1TSYNC
(Input)
L1ST
n
(Output)
70
TFSD=0
75
72
74
80
BIT0
71
73
78
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
50 Freescale Semiconductor
CPM Electrical Characteristics
Figure 48. SI Transmit Timing with Double Speed Clocking (DSC = 1)
L1TXD
(Output)
L1RCLK
(FE=0, CE=0)
(Input)
L1RCLK
(FE=1, CE=1)
(Input)
L1RSYNC
(Input)
L1ST(4-1)
(Output)
72
TFSD=0
75
73
74
78a
80
79
83a
82
L1CLKO
(Output)
84
BIT0
78
81
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 51
CPM Electrical Characteristics
Figure 49. IDL Timing
B17 B16 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 MB15
L1RXD
(Input)
L1TXD
(Output)
L1ST(4-1)
(Output)
L1RQ
(Output)
73
77
12345678910 11 12 13 14 15 16 17 18 19 20
74
80
B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M
71
71
L1GR
(Input)
78
85
72
76
87
86
L1RSYNC
(Input)
L1RCLK
(Input)
81
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
52 Freescale Semiconductor
CPM Electrical Characteristics
8.6 SCC in NMSI Mode Electrical Specifications
Table 18 provides the NMSI external clock timing.
Table 19 provides the NMSI internal clock timing.
Table 18. NMSI External Clock Timing
Num Characteristic
All Frequencies
Unit
Min Max
100 RCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this
table)
1
The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater than or equal to 2.25/1.
1/SYNCCLK — ns
101 RCLKx and TCLKx width low 1/SYNCCLK +5 — ns
102 RCLKx and TCLKx rise/fall time — 15.00 ns
103 TXDx active delay (from TCLKx falling edge) 0.00 50.00 ns
104 RTSx active/inactive delay (from TCLKx falling edge) 0.00 50.00 ns
105 CTSx setup time to TCLKx rising edge 5.00 — ns
106 RXDx setup time to RCLKx rising edge 5.00 — ns
107 RXDx hold time from RCLKx rising edge 2
2
Also applies to CD and CTS hold time when they are used as an external sync signal.
5.00 — ns
108 CDx setup time to RCLKx rising edge 5.00 — ns
Table 19. NMSI Internal Clock Timing
Num Characteristic
All Frequencies
Unit
Min Max
100 RCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this table)
1
The ratios SyncCLK/RCLKx and SyncCLK/TCLK1x must be greater or equal to 3/1.
0.00 SYNCCLK/3 MHz
102 RCLKx and TCLKx rise/fall time — — ns
103 TXDx active delay (from TCLKx falling edge) 0.00 30.00 ns
104 RTSx active/inactive delay (from TCLKx falling edge) 0.00 30.00 ns
105 CTSx setup time to TCLKx rising edge 40.00 — ns
106 RXDx setup time to RCLKx rising edge 40.00 — ns
107 RXDx hold time from RCLKx rising edge 2
2
Also applies to CD and CTS hold time when they are used as an external sync signals.
0.00 — ns
108 CDx setup time to RCLKx rising edge 40.00 — ns
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 53
CPM Electrical Characteristics
Figure 50 through Figure 52 show the NMSI timings.
Figure 50. SCC NMSI Receive Timing Diagram
Figure 51. SCC NMSI Transmit Timing Diagram
RCLKx
CDx
(Input)
102
100
107
108
107
RXDx
(Input)
CDx
(SYNC Input)
102 101
106
TCLKx
CTSx
(Input)
102
100
104
107
TXDx
(Output)
CTSx
(SYNC Input)
102 101
RTSx
(Out put)
105
103
104
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
54 Freescale Semiconductor
CPM Electrical Characteristics
Figure 52. HDLC Bus Timing Diagram
8.7 Ethernet Electrical Specifications
Table 20 provides the Et hernet timings as shown in Figure 53 to Figure 55.
Table 20. Ethernet Timing
Num Characteristic
All Frequencies
Unit
Min Max
120 CLSN width high 40.00 — ns
121 RCLKx rise/fall time (x = 2, 3 for all specs in this table) — 15.00 ns
122 RCLKx width low 40.00 — ns
123 RCLKx clock period 1 80.00 120.00 ns
124 RXDx setup time 20.00 — ns
125 RXDx hold time 5.00 — ns
126 RENA active delay (from RCLKx rising edge of the last data bit) 10.00 — ns
127 RENA width low 100.00 — ns
128 TCLKx rise/fall time — 15.00 ns
129 TCLKx width low 40.00 — ns
130 TCLKx clock period199.00 101.00 ns
131 TXDx active delay (from TCLKx rising edge) 10.00 50.00 ns
132 TXDx inactive delay (from TCLKx rising edge) 10.00 50.00 ns
133 TENA active delay (from TCLKx rising edge) 10.00 50.00 ns
TCLKx
CTSx
(Echo Input)
102
100
104
TXDx
(Output)
102 101
RTSx
(Output)
103
104107
105
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 55
CPM Electrical Characteristics
Figure 53. Ethernet Collision Timing Diagram
Figure 54. Ethernet Receive Timing Diagram
134 TENA inactive delay (from TCLKx rising edge) 10.00 50.00 ns
138 CLKOUT low to SDACK asserted 2 — 20.00 ns
139 CLKOUT low to SDACK negated 2— 20.00 ns
1
The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame destination address into memory.
Table 20. Ethernet Timing (continued)
Num Characteristic
All Frequencies
Unit
Min Max
CLSN(CTSx)
120
(Input)
RCLKx
121
RXDx
(Input)
121
RENA(CDx)
(Input)
125
124 123
127
126
Last Bit
122
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
56 Freescale Semiconductor
CPM Electrical Characteristics
Figure 55. Ethernet Transmit Timing Diagram
8.8 SMC Transparent AC Electrical Specifications
Figure 21 provide s the SMC transparent timings as shown in Figure 56.
Table 21. Serial Management Controller Timing
Num Characteristic
All Frequencies
Unit
Min Max
150 SMCLKx clock period 1
1
The ratio SyncCLK/SMCLKx must be greater or equal to 2/1.
100.00 — ns
151 SMCLKx width low 50.00 — ns
151a SMCLKx width high 50.00 — ns
152 SMCLKx rise/fall time — 15.00 ns
153 SMTXDx active delay (from SMCLKx falling edge) 10.00 50.00 ns
154 SMRXDx/SMSYNx setup time 20.00 — ns
155 SMRXDx/SMSYNx hold time 5.00 — ns
TCLKx
128
TxDx
(Output)
128
TENA(RTSx)
(Input)
NOTES:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not assert ed at all du ring transmit, then the
CSL bi t i s set in the buffer descriptor at the end of the frame trans mission.
1.
2.
RENA(CDx)
(Input)
133 134
132
131 130
129
(NOTE 2)
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 57
CPM Electrical Characteristics
Figure 56. SMC Transparent Timing Diagram
8.9 SPI Master AC Electrical Specifications
Table 22 provides the SPI master timings as shown in Figure 57 and Figure 58.
Table 22. SPI Master Timing
Num Characteristic
All Frequencies
Unit
Min Max
160 MASTER cycle time 4 1024 tcyc
161 MASTER clock (SCK) high or low time 2 512 tcyc
162 MASTER data setup time (inputs) 50.00 — ns
163 Master data hold time (inputs) 0.00 — ns
164 Master data valid (after SCK edge) — 20.00 ns
165 Master data hold time (outputs) 0.00 — ns
166 Rise time output — 15.00 ns
167 Fall time output — 15.00 ns
SMCLKx
SMRXDx
(Input)
152
150
SMTXDx
(Output)
152 151 151a
154 153
155
154
155
NOTE
NOTE:
Th is dela y i s eq ua l to an in t e ge r nu mb er of cha r a c t e r -l e n gth cloc ks .1.
SMSYNx
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
58 Freescale Semiconductor
CPM Electrical Characteristics
Figure 57. SPI Master (CP = 0) Timing Diagram
Figure 58. SPI Master (CP = 1) Timing Diagram
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
162
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164
162
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 59
CPM Electrical Characteristics
8.10 SPI Slave AC Electrical Specifications
Table 23 provides the SPI slave timings as shown in Figure 59 and Figure 60.
Table 23. SPI Slave Timing
Num Characteristic
All Frequencies
Unit
Min Max
170 Slave cycle time 2 — tcyc
171 Slave enable lead time 15.00 — ns
172 Slave enable lag time 15.00 — ns
173 Slave clock (SPICLK) high or low time 1 — tcyc
174 Slave sequential transfer delay (does not require deselect) 1 — tcyc
175 Slave data setup time (inputs) 20.00 — ns
176 Slave data hold time (inputs) 20.00 — ns
177 Slave access time — 50.00 ns
178 Slave SPI MISO disable time — 50.00 ns
179 Slave data valid (after SPICLK edge) — 50.00 ns
180 Slave data hold time (outputs) 0.00 — ns
181 Rise time (input) — 15.00 ns
182 Fall time (input) — 15.00 ns
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
60 Freescale Semiconductor
CPM Electrical Characteristics
Figure 59. SPI Slave (CP = 0) Timing Diagram
SPIMOSI
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
SPIMISO
(Output)
180
Data
181182173
173 170
msb lsb msb
181
177 182
175 179
SPISEL
(Input)
171172
174
Datamsb lsb msbUndef
181
178
176 182
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 61
CPM Electrical Characteristics
Figure 60. SPI Slave (CP = 1) Timing Diagram
8.11 I2C AC Electrical Specifications
Table 24 provides the I2C (SCL < 100 KHz) timings.
Table 24. I2C Timing (SCL < 100 KHZ)
Num Characteristic
All Frequencies
Unit
Min Max
200 SCL clock frequency (slave) 0.00 100.00 KHz
200 SCL clock frequency (master) 1 1.50 100.00 KHz
202 Bus free time between transmissions 4.70 — µs
203 Low period of SCL 4.70 — µs
204 High period of SCL 4.00 — µs
205 Start condition setup time 4.70 — µs
206 Start condition hold time 4.00 — µs
207 Data hold time 0.00 — µs
208 Data setup time 250.00 — ns
209 SDL/SCL rise time — 1.00 µs
SPIMOSI
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
SPIMISO
(Output)
180
Data
181182
msb lsb
181
177 182
175 179
SPISEL
(Input)
174
Data
msb lsbUndef
178
176 182
msb
msb
172
173
173
171 170
181
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
62 Freescale Semiconductor
CPM Electrical Characteristics
Table 25 provides the I2C (SCL > 100 KHz) timings.
Figure 61 shows the I2C bus timing.
Figure 61. I2C Bus Timing Diagram
210 SDL/SCL fall time — 300.00 ns
211 Stop condition setup time 4.70 — µs
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
Table 25. I2C Timing (SCL > 100 KHZ)
Num Characteristic Expression
All Frequencies
Unit
Min Max
200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz
200 SCL clock frequency (master) 1
1
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
fSCL BRGCLK/16512 BRGCLK/48 Hz
202 Bus free time between transmissions 1/(2.2 * fSCL) — s
203 Low period of SCL 1/(2.2 * fSCL) — s
204 High period of SCL 1/(2.2 * fSCL) — s
205 Start condition setup time 1/(2.2 * fSCL) — s
206 Start condition hold time 1/(2.2 * fSCL) — s
207 Data hold time 0 — s
208 Data setup time 1/(40 * fSCL) — s
209 SDL/SCL rise time — 1/(10 * fSCL) s
210 SDL/SCL fall time — 1/(33 * fSCL) s
211 Stop condition setup time 1/2(2.2 * fSCL) — s
Table 24. I2C Timing (SCL < 100 KHZ) (CONTINUED)
Num Characteristic
All Frequencies
Unit
Min Max
SCL
202
205
203
207
204
208
206 209 211210
SDA
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 63
Mechanical Data and Ordering Information
9 Mechanical Data and Ordering Information
Table 26 provides information on t he MPC850 derivative devices.
Table 27 identifies the packages and opera ting frequencies available for the MPC850.
9.1 Pin Assignments and Mechanical Dimensions of the PBGA
The original pin numbering of the MPC850 conformed to a Freescale proprietary pin numbering scheme
that has since been replaced by the JEDEC pin numbering standard for this package type. To support
Table 26. MPC850 Family Derivatives
Device Ethernet Support Number of SCCs 1
1
Serial Communication Controller (SCC)
32-Channel HDLC
Support
64-Channel HDLC
Support 2
2
50 MHz version supports 64 time slots on a time division multiplexed line using one SCC
MPC850 N/A One N/A N/A
MPC850DE Yes Two N/A N/A
MPC850SR Yes Two N/A Yes
MPC850DSL Yes Two No No
Table 27. MPC850 Package/Frequency/Availability
Package Type Frequency (MHz) Temperature (Tj) Order Number
256-Lead Plastic Ball Grid Array
(ZT suffix)
50 0°C to 95°C XPC850ZT50BU
XPC850DEZT50BU
XPC850SRZT50BU
XPC850DSLZT50BU
66 0°C to 95°C XPC850ZT66BU
XPC850DEZT66BU
XPC850SRZT66BU
80 0°C to 95°C XPC850ZT80BU
XPC850DEZT80BU
XPC850SRZT80BU
256-Lead Plastic Ball Grid Array
(CZT suffix)
50 -40°C to 95°C XPC850CZT50BU
XPC850DECZT50BU
XPC850SRCZT50BU
XPC850DSLCZT50BU
66 XPC850CZT66BU
XPC850DECZT66BU
XPC850SRCZT66BU
80 XPC850CZT80B
XPC850DECZT80B
XPC850SRCZT80B
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
64 Freescale Semiconductor
Mechanical Data and Ordering Information
customers that are currently using the non-JEDEC pin numbering scheme, two sets of pinouts, JEDEC and
non-JEDEC, are pre sented in this document.
Figure 62 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface.
Figure 62. Pin Assignments for the PBGA (Top View)—non-JEDEC Standard
PC14 PB28 PB27 PC12 TCK PB24 PB23 PA8 PA7 VDDL PA5 PC7 PC4 PD14 PD10 PD8
PC15 PA14 PA13 PA12 TMS
PB26
PA15 PB30 PB29 PC13 TRST N/C PC10 PA6 PB18 PC5 PD13 PD9 PD4 PD5
A8 A7 PB31 TDO
TDI PC11 PB22 PC9
PB25 PA9 PC8
A11 A9 A12
PB19 PA4 PB16 PD15 PD12 PD7 PD6
PB17 PC6 PD11 PD3 IRQ7 IRQ1 IRQ0
T
R
P
N
M
A15 A14 A13
A27 A19 A16
VDDL A20 A21
A29 A23 A25
A28 A30 A22
A31 TSIZ0 A26
WE1 TSIZ1
WE0 WE2 GPLA3
GPLA1 GPLA2 CS6
D8 D0
D4 D1
D9 D11
D2 D3
K
J
H
L
D16 D5
D19 VDDL
D21 D6
D29 D7
D30 CLKOUT
DP3 N/C
GND
G
F
VDDH
E
D
CS4 CS7 CS2 XFC VDDSYN
BI
N/C CS3 CS1 BDIP
BURST IPB4 ALEB IRQ4 MODCK2HRESET
SRESET
PORESET
VSSSYN1VSSSYN
BR
BB IRQ6 IPB3 IPB0 VDDLEXTCLKEXTAL XTAL KAPWR
C
B
A
TA
16 15 14 13 12 11 10 9 87654321
A6
A10
A17
A24
A18
WE3
GPLA0
CS5
WR
GPLB4
CS0 TS IRQ2 IPB7 IPB2 MODCK1 TEXP DP1 DP2
GPLA4
TEA BG IPB5 IPB1 IPB6 RSTCONFWAITB DP0
GPLA5
D12 D13
D23 D27
D17 D10
D15 D14
D22 D18
D25 D20
D28 D24
D26 D31
N/CN/C
N/C
N/C
N/C
N/C
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 65
Mechanical Data and Ordering Information
Figure 63 s hows the JEDEC pinout of the PBGA package as viewed fr om the top surface.
Figure 63. Pin Assignments for the PBGA (Top View)—JEDEC Standard
For more information on the printed circuit board layout of the PBGA package, including thermal via
design and suggeste d pad layout, please refer to AN-1231/D, Plastic Ball Grid Array Application Note
available from your local Freescale sales offi ce.
PC14 PB28 PB27 PC12 TCK PB24 PB23 PA8 PA7 VDDL PA5 PC7 PC4 PD14 PD10 PD8
PC15 PA14 PA13 PA12 TMS
PB26
PA15 PB30 PB29 PC13 TRST N/C PC10 PA6 PB18 PC5 PD13 PD9 PD4 PD5
A8 A7 PB31 TDO
TDI PC11 PB22 PC9
PB25 PA9 PC8
A11 A9 A12
PB19 PA4 PB16 PD15 PD12 PD7 PD6
PB17 PC6 PD11 PD3 IRQ7 IRQ1 IRQ0
U
T
R
P
N
A15 A14 A13
A27 A19 A16
VDDL A20 A21
A29 A23 A25
A28 A30 A22
A31 TSIZ0 A26
WE1 TSIZ1
WE0 WE2 GPLA3
GPLA1 GPLA2 CS6
D8 D0
D4 D1
D9 D11
D2 D3
L
K
J
M
D16 D5
D19 VDDL
D21 D6
D29 D7
D30 CLKOUT
DP3 N/C
GND
H
G
VDDH
F
E
CS4 CS7 CS2 XFC VDDSYN
BI
N/C CS3 CS1 BDIP
BURST IPB4 ALEB IRQ4 MODCK2
HRESET
SRESETPORESET
VSSSYN1VSSSYN
BR
BB IRQ6 IPB3 IPB0 VDDLEXTCLKEXTAL XTAL KAPWR
D
C
B
TA
17 16 15 14 13 12 11 10 98765432
A6
A10
A17
A24
A18
WE3
GPLA0
CS5
WR
GPLB4
CS0 TS IRQ2 IPB7 IPB2 MODCK1 TEXP DP1 DP2
GPLA4
TEA BG IPB5 IPB1 IPB6 RSTCONF
WAITB DP0
GPLA5
D12 D13
D23 D27
D17 D10
D15 D14
D22 D18
D25 D20
D28 D24
D26 D31
N/CN/C
N/C
N/C
N/C
N/C
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
66 Freescale Semiconductor
Mechanical Data and Ordering Information
Figure 64 shows the non-JEDEC package dimensions of the PBGA.
Figure 64. Package Dimensions for the Plastic Ball Grid Array (PBGA)—non-JEDEC Standard
T
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
256X
BOTTOM VIEW
E
0.20
654321
b
0.15 C
D
D2
E2
A
B
0.30 C AB
SIDE VIEW
DIM MIN MAX
MILLIMETERS
A1.91 2.35
A1 0.50 0.70
A2 1.12 1.22
A3 0.29 0.43
b0.60 0.90
D23.00 BSC
D1 19.05 REF
D2
E23.00 BSC
E1 19.05 REF
E2 19.00 20.00
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO PRIMARY
DATUM C.
4. PRIMARY DATUM C AND THE SEATING PLANE ARE
4X
7 8 9 10 11 12 13 14 15
M
M
TOP VIEW
(D1)
15X e
15X e
(E1)
4X e/2
0.20 C
0.35 C
A3
256X
C
A
A1
A2
SEATING
PLANE
e1.27 BSC
19.00 20.00
16
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 67
Mechanical Data and Ordering Information
Figure 65 shows the JEDEC package dimensions of the PBGA.
Figure 65. Package Dimensions for the Plastic Ball Grid Array (PBGA)—JEDEC Standard
U
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
256X
BOTTOM VIEW
E
0.20
765432
b
0.15 C
D
D2
E2
A
B
0.30 C AB
SIDE VIEW
DIM MIN MAX
MILLIMETERS
A1.91 2.35
A1 0.50 0.70
A2 1.12 1.22
A3 0.29 0.43
b0.60 0.90
D23.00 BSC
D1 19.05 REF
D2
E23.00 BSC
E1 19.05 REF
E2 19.00 20.00
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO PRIMARY
DATUM C.
4. PRIMARY DATUM C AND THE SEATING PLANE ARE
4X
8 9 10 11 12 13 14 15 16
M
M
TOP VIEW
(D1)
15X e
15X e
(E1)
4X e/2
0.20 C
0.35 C
A3
256X
C
A
A1
A2
SEATING
PLANE
e1.27 BSC
19.00 20.00
17
CASE 1130-01
ISSUE B
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
68 Freescale Semiconductor
Document Revision History
10 Document Revision History
Table 28 lists significant changes between revisions of this document.
Table 28. Document Revision History
Revision Date Change
2 7/2005 Added footnote 3 to Table 5 (previously Table 4.5) and deleted IOL limit.
1 10/2002 Added MPC850DSL. Corrected Figure 25 on page 34.
0.2 04/2002 Updated power numbers and added Rev. C
0.1 11/2001 Removed reference to 5 Volt tolerance capability on peripheral interface pins.
Replaced SI and IDL timing diagrams with better images. Updated to new
template, added this revision table.
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 69
Document Revision History
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70 Freescale Semiconductor
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MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor 71
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
Document Number: MPC850EC
Rev. 2
07/2005
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