LINEAR TECHNOLOGY
LINEAR TECHNOLOGY
LINEAR TECHNOLOGY
IN THIS ISSUE…
COVER ARTICLE
Third-Generation DC/DC Controller
Reduces Size and Cost .................. 1
Randy G. Flatness
Issue Highlights ............................ 2
LTC
®
in the News........................... 2
DESIGN FEATURES
New Universal Continuous-Time Filter
with Extended Frequency Range ... 7
Max W. Hauser
SOT-23 Switching Regulators
Deliver Low Noise Outputs
in a Small Footprint ................... 11
Steve Pietkiewicz
Versatile New Switching Regulator
Fits in SO-8 ................................. 14
Craig Varga
16-Bit Parallel DAC Has 1LSB
Linearity, Ultralow Glitch and
Accurate 4-Quadrant Resistors ... 18
Patrick Copley
Fast Rate Li-Ion Battery Charger
................................................... 24
Goran Perica
DESIGN IDEAS
No R
SENSE
Controller Delivers 12V and
100W at 97% Efficiency .............. 26
Christopher B. Umminger
Generating Low Cost, Low Noise,
Dual-Voltage Supplies ................. 27
Ajmal Godil
Switched Capacitor Voltage Regulator
Provides Current Gain ................. 28
Jeff Witt
High Current Step-Down Conversion
from Low Input Voltages ............. 30
Dave Dwelley
How to Design High Order Filters with
Stopband Notches Using the LTC1562
Operational Filter (Part 2) ........... 31
Nello Sevastopoulos
DESIGN INFORMATION
The LTC1658 and LTC1655: Smallest
Rail-to-Rail 14-Bit and 16-Bit DACs
................................................... 36
Hassan Malik
New Device Cameos ..................... 37
Design Tools................................ 39
Sales Offices ............................... 40
FEBRUARY 1999 VOLUME IX NUMBER 1
, LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load,
FilterCAD, Hot Swap, Linear View, Micropower SwitcherCAD, No R
SENSE
, Operational Filter, OPTI-LOOP, PolyPhase,
SwitcherCAD and UltraFast are trademarks of Linear Technology Corporation. Other product names may be trademarks
of the companies that manufacture the products.
Thir d-Generation DC/DC
Controllers Reduce
Size and Cost
Introduction
The LTC1735 and LTC1736 are the
newest members of Linear Tech-
nology’s third generation of DC/DC
controllers. These controllers use the
same constant frequency, current
mode architecture and Burst Mode™
operation as the previous generation
LTC1435–LTC1437 controllers but
with improved features. With
OPTI-LOOP™ compensation, new
protection circuitry, tighter load regu-
lation and strong MOSFET drivers,
these controllers are ideal for the
current and future generations of CPU
power applications.
The LTC1735 is pin compatible with
the previous generation LTC1435/
LTC1435A controllers with only mi-
nor external component changes.
Protection features include internal
foldback current limiting, output ov-
ervoltage crowbar and optional
short-circuit shutdown. The 0.8V ±1%
reference allows the low output volt-
ages and 1% accuracy that will be
demanded by future microprocessors.
The operating frequency (synchroniz-
able up to 500kHz) is set by an external
capacitor , allowing maximum flexibil-
ity in optimizing efficiency.
The LTC1736 has all of the fea-
tures of the LTC1735, plus voltage
programming for CPU power , in a 24-
lead SSOP package. The output voltage
in LTC1736 applications is pro-
grammed by a 5-bit digital-to-analog
converter (DAC) that adjusts the out-
continued on page 3
Figure 1. LTC1736 evaluation circuit: a complete 5V–24V to 0.9V–2V/12A converter
in 2.15in
2
of PC board space
by Randy G. Flatness
Linear Technology Magazine • February 1999
2
EDITOR’S PAGE
Issue Highlights
Happy New Year and welcome to
the ninth volume of Linear Technol-
ogy magazine.
This issue is heavy on power prod-
ucts: our cover article introduces the
LTC1735 and LTC1736, the newest
members of Linear Technology’s third
generation of DC/DC controllers.
These controllers use the same cur -
rent mode architecture with constant
frequency and Burst Mode operation
as the LTC1435–LTC1437 controllers
but with improved features. With
OPTI-LOOP compensation, new
protection circuitry, tighter load regu-
lation and strong MOSFET drivers,
these controllers are ideal for the cur-
rent and future generations of CPU
power applications.
This issue debuts the L TC1530, a
synchronous buck regulator control-
ler in the SO-8 package. The LTC1530
is a small, versatile controller that is
usable in numerous topologies and
over a wide range of power levels. In
basic buck applications, the LTC1530
permits the designer to realize very
simple, low parts count designs that
require minimal real estate. With a
little ingenuity, it is possible to de-
velop circuits different than those that
the part’s designers intended, but
which give excellent performance
nonetheless.
The LT
®
1505 is a constant-cur-
rent, constant-voltage, current mode
switching battery charger using the
synchronous buck topology. Its out-
put voltage is preset for 3–4 Li-Ion
cells, but can be programmed from 1V
to 21V. It features a 0.5% voltage
reference, low dropout operation, pro-
grammable wall adapter current
limiting and ef ficiencies to 94%.
Rounding out our selection of
switchers are the LT1611 and LT1613.
These current mode, constant fre-
quency devices contain inter nal 36V
switches capable of generating out-
put power in the range of 400mW to
2W , in a 5-lead SOT-23 package. The
LT1613 has a standard positive feed-
back pin and is designed to regulate
positive voltages. The LT1611 has a
novel feedback scheme designed to
directly regulate negative output volt-
ages without the use of level-shifting
circuitry.
In the filter arena, we premier the
LTC1562-2, an extended-frequency
version of the LTC1562 quadruple
2nd order, universal, continuous-time
filter , described in the February 1998
issue. The LTC1562 introduced
Operational Filter™ building blocks,
which satisfy diverse filter
requirements and applications
compactly
. The
LTC1562-2 has the
same block diagram, pinout and pack-
aging as the original LTC1562, but is
optimized for higher filter frequen-
cies: 20kHz to 300kHz. Besides
covering a full octave of frequencies
(150kHz–300kHz) above the range of
the LTC1562, the LTC1562-2 also
overlaps the LTC1562’s utility in the
range 20kHz to 150kHz. In this
frequency range, the LTC1562-2 typi-
cally shows reduced large-signal
distortion at a cost of slightly more
noise than with the L TC1562.
We also introduce a new data con-
verter: the LTC1597 16-bit parallel,
current output, low glitch, multiplying
DAC. The LTC1597 has outstanding
1LSB linearity over temperature,
ultralow glitch impulse, on-chip 4-
quadrant feedback resistors, low power
consumption, asynchronous clear and
a versatile parallel interface. For 14-
bit systems, its pin compatible
counterpart, the LTC1591, is an ideal
solution. Combined with the LT1468
op amp (introduced in the November
1998 issue), the LTC1597 provides the
best in its class, 1.7µs settling time to
0.0015%, while maintaining superb
DC linearity specifications. Two rail-
to-rail, voltage output DACs can be
found in the Design Information sec-
tion: the 14-bit LTC1658 and the 16-bit
LTC1655; these DACs have a flexible
3-wire serial interface that is SPI/
QSPI and MICROWIRE™ compatible.
They provide a convenient upgrade
path for users of LTC’s 12-bit voltage
output
DAC family.
This issue features a rich selection
of Design Ideas, including four dif-
ferent power conversion circuits and
the second in a series of articles on
designing high order filters with stop-
band notches using the LTC1562
filter ICs.
The issue concludes with six New
Device Cameos.
LTC in the News…
On January 12, 1999, Linear Tech-
nology announced its financial
results for the second quarter of FY
1999, reporting increased sales and
profits compared to the second
quarter of the previous year. Net
sales and net income for the quar-
ter ended December 27, 1998, were
$120,020,000 and $45,904,000,
respectively.
Reporting the results, Linear
Technology President and CEO Rob-
ert H. Swanson said, “This quarter
proved to be stronger than we
initially expected, as the general
worldwide economic climate
improved. We grew sales and prof-
its 3% sequentially from the
previous quarter and added $35.6
million to our cash balance. Our
return on sales is an industry
leading 38.2%.”
Prior to the announcement, Lin-
ear Technology was named a top
stock pick for 1999 in a December
17, 1998 article in USA Today. Jim
Craig, manager of the $21 billion
Janus fund and one of several
financial analysts surveyed inter-
viewed by USA Today, listed Linear
Technology among his top picks for
the coming year.
The December 28 issue of EE
Times named Linear Technology
Staf f Scientist Jim Williams one of
nineteen “Times People 98.” The
issue included a full-page profile on
Jim, emphasizing the changes he
has seen in analog design over the
past two decades.
The December 7 issues of both
Electronic News and Electronic
Buyers’ News reported Linear
Technology’s December announce-
ment of the addition of Wyle
Electronics as an authorized
distributor.
MICROWIRE is a trademark of National Semiconductor Corp.
Linear Technology Magazine • February 1999
3
DESIGN FEATURES
put voltage from 0.925V to 2.00V,
according to Intel mobile VID
specifications.
Details
The LTC1735 and LTC1736 are syn-
chronous step-down switching
regulator controllers that drive exter-
nal N-Channel power MOSFETs using
a programmable fixed frequency OPTI-
LOOP architecture. OPTI-LOOP
compensation effectively removes the
constraints placed on C
OUT
by other
controllers for proper operation (such
as limits on low ESRs). A maximum
duty cycle limit of 99% provides low
dropout operation, which extends
operating time in battery operated
systems. A forced-continuous con-
trol pin reduces noise and RF
interference and can assist second-
ary winding regulation by disabling
Burst Mode when the main output is
lightly loaded. Soft-start is provided
by an exter nal capacitor that can be
used to properly sequence supplies.
The operating current level is user-
programmable via an external current
sense resistor. A wide input-supply
range allows operation from 3.5V to
30V (36V maximum).
Protection
New internal protection features in
the LTC1735 and LTC1736 control-
lers include foldback current limiting,
short circuit detection, short-circuit
latch-off and overvoltage protection.
These features protect the PC board,
the MOSFETs and the load itself (the
CPU) against faults.
Fault Protection:
Overcurrent Latch-Off
The RUN/SS pin, in addition to pro-
viding soft-start capability, also
provides the ability to shut off the
controller and latch off when an over-
current condition is detected. The
RUN/SS capacitor, C
SS
,
(refer to Fig-
ure 5) is used initially to turn on and
limit the inrush current of the con-
troller. After the controller has been
started and given adequate time to
charge the output capacitor and pro-
vide full load current, C
SS
is used as
a short-circuit timer. If the output
voltage falls to less than 70% of its
nominal output voltage after C
SS
reaches 4.2V, it is assumed that the
output is in a severe overcurrent
and/or short-circuit condition and
C
SS
begins discharging. If the condi-
tion lasts for a long enough period, as
determined by the size of C
SS
, the
controller will be shut down until the
RUN/SS pin voltage is recycled.
This built-in latch-off can be over-
ridden by providing >5µA at a
compliance of 4V to the RUN/SS pin
(refer to the LTC1735/LTC1736 Data
Sheet for details). This exter nal cur-
rent shortens the soft-start period
but also prevents net discharge of the
RUN/SS capacitor during a severe
overcurrent and/or short-circuit
condition.
Why should you defeat overcur-
rent latch-off? During the prototyping
stage of a design, there may be a
problem with noise pickup or poor
layout causing the protection circuit
to latch off. Defeating this feature will
allow easy troubleshooting of the cir-
cuit and PC layout. The internal
short-circuit detection and foldback
current limiting still remain active,
thereby protecting the power supply
system from failure. After the design
is complete, you can decide whether
to enable the latch-of f feature.
Fault Protection: Current Limit
and Current Foldback
The LTC1735/LTC1736 current com-
parator has a maximum sense voltage
of 75mV, resulting in a maximum
MOSFET current of 75mV/R
SENSE
.
The LTC1735/LTC1736 includes cur-
rent foldback to help further limit
load current when the output is
shorted to ground. If the output falls
by more than one-half, the maximum
sense voltage is progressively lowered
from 75mV to 30mV. Under short-
circuit conditions with very low duty
cycle, the LTC1735/LTC1736 will
begin cycle skipping in order to limit
the short-circuit current. In this situ-
ation, the bottom MOSFET will be on
most of the time, conducting the cur-
rent. The average short-circuit current
will be approximately 30mV/ R
SENSE.
Note that this function is always active
and is independent of the short cir -
cuit latch-off.
Fault Protection: Output
Overvoltage Protection (OVP)
An output overvoltage crowbar turns
on the synchronous MOSFET to blow
a system fuse in the input lead when
noitidnoCgnitarepOhctaLtfoShctaLdraH
stneisnarTtsaFtoohsrevOslortnoCffOsehctaL
V5otdetrohStuptuOPVOtadepmalCtuptuOffOsehctaL
esaerceDegatloVDIVegatloVweNsetalugeRffOsehctaL
esioNtuptuOslortnoCffOsehctaL
TEFSOMpoTdetrohSsdaolrevOTEFSOMmottoBsdaolrevOTEFSOMmottoB
naCegatloVtuptuO
esreveR
oNseY
devomeRsidaolrevOnehWnoitarepOlamroNsemuseRffOdehctaLsniameR
stluaFgnitoohselbuorTstnemerusaeMCDysaE
eriuqeRyaM;tluciffiD
sepocsollicsOlatigiD
Table 1. Overvoltage protection comparison
OPERATING FREQUENCY (kHz)
0 100 200 300 400 500 600
C
OSC
VALUE (pF)
100.0
87.5
75.0
62.5
50.0
37.5
25.0
12.5
0
LTC1735/
LTC1736
LTC1435/
LTC1436
Figure 2. C
OSC
value vs frequency for the
LTC1435/36 and the LTC1735/36
LTC1735/LTC1736, continued from page 1
Linear Technology Magazine • February 1999
4
DESIGN FEATURES
the output of the regulator rises much
higher than nominal levels. The crow-
bar can cause huge currents to flow,
greater than in normal operation. This
feature is designed to protect against
a shorted top MOSFET or short cir -
cuits to higher supply rails; it does
not protect against a failure of the
controller itself.
Previous latching crowbar schemes
for overvoltage protection have a num-
ber of problems (see T able 1). One of
the most obvious, not to mention
most annoying, is nuisance trips
caused by noise or transients
momentarily exceeding the OVP
threshold. Each time that this occurs
with latching OVP, a manual reset is
required to restart the regulator. Far
more subtle is the resulting output
voltage reversal. When the synchro-
nous MOSFET latches on, a large
reverse current is loaded into the
inductor while the output capacitor is
discharging. When the output voltage
reaches zero, it does not stop there,
but rather continues to go negative
until the reverse inductor current is
depleted. This requires a sizable
Schottky diode across the output to
prevent excessive negative voltage on
the output capacitor and load.
A further problem on the horizon
for latching OVP circuits is their
incompatibility with on-the-fly CPU
core voltage changes. If an output
voltage is reprogrammed from a higher
voltage to a lower voltage, the OVP
will temporarily indicate a fault, since
the output capacitor will momentarily
hold the previous, higher output volt-
age. With latching OVP, the result will
be another latch-off, with a manual
reset required to attain the new out-
put voltage. To prevent this problem,
the OVP threshold must be set above
the maximum programmable output
voltage, which would do little good
when the output voltage was pro-
grammed near the bottom of its range.
In order to avoid these problems
with traditional latching OVP circuits,
the LTC1735 and LTC1736 use a new
“soft latch” OVP circuit. Regardless of
operating mode, the synchronous
MOSFET is forced on whenever the
output voltage exceeds the regulation
point by more than 7.5%. However , if
the voltage then returns to a safe
level, nor mal operation is allowed to
resume, thereby preventing latch-off
caused by noise or voltage repro-
gramming. Only in the case of a true
fault, such as a shorted top MOSFET,
will the synchronous MOSFET remain
latched on until the input voltage
collapses or the system fuse blows.
The new soft latch OVP also pro-
vides protection and easy diagnosis
of other overvoltage faults, such as a
lower supply rail shorted to a higher
voltage. In this scenario, the output
voltage of the higher regulator is pulled
down to the OVP voltage of the
soft-latched regulator, allowing the
problem to be easily diagnosed with
DC measurements. On the other
hand, latching OVP provides only a
millisecond glimpse of the fault as it
latches off, forcing the use of expensive
digital oscilloscopes for trouble-
shooting.
Three Operating Modes/One
Pin: Sync, Burst Disable and
Secondary Regulation
The FCB pin is a multifunction pin
that controls the operation of the
synchronous MOSFET and is an input
for external clock synchronization.
When the FCB pin drops below its
0.8V threshold, continuous mode
operation is forced. In this case, the
top and bottom MOSFETs continue
to be driven synchronously regard-
less of the load on the main output.
Burst Mode operation is disabled and
current reversal is allowed in the
inductor.
In addition to providing a logic
input to force continuous syn-
chronous operation and external
niPBCFnoitidnoC
:egatloVCD
V7.0–V0
/delbasiDtsruB
,suounitnoCdecroF
lasreveRtnerruC
delbanE
V9.0>:egatloVCD oN,edoMtsruB
lasreveRtnerruC
srotsiseRkcabdeeF agnitalugeR
gnidniWyradnoceS
V(
CNYSBCF
)V5.1>
edoMtsruB
oN,delbasiD
lasreveRtnerruC
Table 2. FCB possible states
retemaraP6371/5371CTLLLP-A6341/A5341CTL
ecnerefeRV8.0V91.1
noitalugeRdaoLxaM%2.0,pyT%1.0xaM%8.0pyT%5.0
esneStnerruCxaMVm57Vm051
emiT-nOmuminiMsn002sn003
elbazinorhcnySseYylnOLLP-A6341CTL
VtnI
CC
egatloV)xaMV7(V2.5)xaMV01(V5
tuptuOdooGrewoPylnO6371CTLylnOLLP-6A3/6A341CTL
kcabdloFtnerruClanretnIlanretxE
noitcetorPVOtuptuOseYoN
ffO-hctaLIOtuptuOlanoitpOoN
segakcaP42G/61NG,61OS42NG/61G,61OS
srevirDTEFSOM3×1×
Table 3. Comparison of LTC1735/36 controllers with LTC1435A/36A-PLL controllers
BURST
SYNC
CONTINUOUS
100%
90%
80%
70%
60%
50%
40%
30%
20%
0.001 0.01 0.1 1.0 10.0
LOAD CURRENT (A)
EFFICIENCY (%)
Figure 3. Efficiency vs load current for three
modes of operation
Linear Technology Magazine • February 1999
5
DESIGN FEATURES
synchronization, the FCB pin pro-
vides a means to regulate a flyback
winding output. It can force continu-
ous synchronous operation when
needed by the flyback winding,
regardless of the primary output load.
In order to prevent erratic operation if
Table 4. VID output voltage programming
4B3B2B1B0BV
TUO
)V(
00000 V000.2
00001 V059.1
00010 V009.1
00011 V058.1
00100 V008.1
00101 V057.1
00110 V007.1
00111 V056.1
01000 V006.1
01001 V055.1
01010 V005.1
01011 V054.1
01100 V004.1
01101 V053.1
01110 V003.1
01111 *
10000 V572.1
10001 V052.1
10010 V522.1
10011 V002.1
10100 V571.1
10101 V051.1
10110 V521.1
10111 V001.1
11000 V570.1
11001 V050.1
11010 V520.1
11011 V000.1
11100 V579.0
11101 V059.0
11110 V529.0
11111 **
denifedatuohtiwsedoctneserpe r**,*:etoN .snoitacificepsletnInideificepssaegatlovtuptuo dilavasasedocesehtsterpretni6371CTLehT :swollofsaegatlovtuptuosecudorpdnastupni .V009.0=]11111[,V052.1=]11110[
no external connections are made,
the FCB pin is pulled high by a 0.25µA
inter nal current source.
The LTC1735 internal oscillator
can be synchronized to an external
oscillator by applying a clock signal of
at least 1.5V
P-P
to the FCB pin. When
synchronized to an external fre-
quency, Burst Mode operation is
disabled but cycle skipping occurs at
low load currents since current
reversal is inhibited. The bottom gate
will come on every 10 clock cycles to
ensure that the bootstrap cap is kept
refreshed and to keep the frequency
above the audio range. The rising
edge of an external clock applied to
the FCB pin starts a new cycle.
The range of synchronization is
from 0.9 × f
O
to 1.3 × f
O
, with f
O
set by
C
OSC
. Attempting to synchronize to a
higher frequency than 1.3 × f
O
can
result in inadequate slope compensa-
tion and cause loop instability with
high duty cycles. If loop instability is
observed while synchronized, addi-
tional slope compensation can be
obtained by simply decreasing C
OSC
.
A plot of operating frequency versus
C
OSC
value is shown in Figure 2.
Table 2 summarizes the possible
states available on the FCB pin.
Figure 3 gives a comparison of effi-
ciencies in a regulator for the three
operating modes: forced continuous
operation, pulse skipping mode (syn-
chronized at f = f
O
) and Burst Mode
operation.
Converting to the LTC1735
The LTC1735 is pin compatible with
the LTC1435/LTC1435A, with minor
component changes. Table 3 shows
the differences between the two con-
trollers. The important items to note
are:
1. The L TC1735 has a 0.8V refer-
ence (versus 1.19V for the
L TC1435) that allows lower
output voltage operation (down to
0.8V). Thus, the output feedback
divider will have to be recalcu-
lated for the same output voltage.
2. The L TC1735’s maximum
current sense voltage is half that
of the LTC1435. This r educes the
power lost in the sense resistor
by half. Hence, for the same
maximum output current, the
current sense resistor must be
cut in half.
0.005Ω
M2
FDS6680A
0.22µF
C2
4.7µF
2µH
MBRS340T3
22µF
30V
V
OUT
1.6V/9A
+V
IN
C
IN1
R
CS1
C
O3*
820µF
4V
C
O1
180µF
4V
FDS6680A
+
+
M1
R3
R7
10k
1%
10k
1%
L1
†
BOOST
PGND
BG
INT V
CC
SW
TG
RUN/SS
C
OSC
SGND
SENSE
+
V
IN
EXT V
CC
I
TH
FCB
V
OSENSE
SENSE
–
LTC1735
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
OSC1
47pF
C
C1
C1
47pF
C
C2
100pF
C
S1
, 1000pF
C
SS
0.1µF
R
C1
33k
330pF D1
CMDSH-3
C
B1
R5 10Ω
R2 10Ω
C3
47pF
EXT V
CC
R
F1
4.7Ω
C
F1
0.1µF
JP2
LATCH-OFF
(DISABLED)
R6, 1M
INT V
CC
ON
JP1
BURST MODE FCB/SYNCRUN
R
S1
10Ω
22µF
30V
C
IN3
+
+
D2
GND
V
O
C4
1µF
PANASONIC ETQP6F2R0HFA (201) 348-7522
SANYO OSCON 4SP820M (619) 661-6835
†
*
OFF
30
25
20
15
10
5
0
100 200 300 400 500 600
FREQUENCY (kHz)
GATE-CHARGE CURRENT (mA)
TOP AND BOTTOM MOSFETS
= FAIRCHILD NDS6680A
Figure 4. MOSFET gate-charge current vs
frequency
Figure 5. High efficiency 1.6V/9A CPU power supply
Linear Technology Magazine • February 1999
6
DESIGN FEATURES
3. The gate drivers of the L TC1735
are 3× the strength of those in
the L TC1435. This equates to
faster rise and fall times for
driving the same MOSFETs plus
the capability to drive larger
MOSFET s with less efficiency
loss due to transition losses.
Speed
The LTC1735/LTC1736 are designed
to be used in higher current applica-
tions than the LTC1435 family.
Stronger gate drives allow paralleling
multiple MOSFETs or higher operat-
ing frequencies. The LTC1735 has
been optimized for low output voltage
operation by reducing the minimum
on-time to less than 200ns. Remem-
ber, though, that transition losses
can still impose significant efficiency
penalties at high input voltages and
high frequencies. Just because the
LTC1735 can operate at frequencies
above 300kHz doesn’t mean it should.
Figure 4 shows a plot of MOSFET
charge current versus frequency.
Linear Current
Comparator Operation
Since the trend in the marketplace
has forced output voltages to lower
and lower values, the current sense
inputs have been optimized for low
voltage operation. The current sense
comparator has a linear response
characteristic, without discon-
tinuities, from 0V to 6V output
voltages. In the LTC1435/LTC1435A,
two input stages are used to cover
this range, so an overlap exists
together with a transition region. The
LTC1735/LTC1736 uses only one
input stage and includes slope com-
pensation that operates over the full
output voltage range. This allows the
LTC1735/LTC1736 to be operated in
grounded R
SENSE
applications as well.
LTC1736 Additional Features
The LTC1736 includes all the fea-
tures of the LTC1735, plus 5-bit
mobile VID control and a power-good
comparator in a 24-lead SSOP pack-
age. The window comparator monitors
the output voltage and its open-drain
output is pulled low when the divided
voltage is not within ±7.5% of the 0.8V
reference voltage.
The output voltage is digitally set
to levels between 0.925V and 2.00V
using the voltage identification (VID)
inputs B0–B4. The internal 5-bit DAC
configured as a precision resistive
voltage divider sets the output volt-
age in 50mV or 25mV increments
according to Table 4. The VID codes
(00000–11110) are compatible with
the Intel mobile Pentium
®
II
proces-
sor. The LSB (B0) represents 50mV
increments in the upper voltage range
(2.00V–1.30V) and 25mV increments
in the lower voltage range (1.275V–
0.925V). The MSB is B4. When all bits
are low or grounded, the output volt-
age is 2.00V.
The LTC1736 also has remote sense
capability. The top of the internal
resistive divider is connected to
V
OSENSE
and is referenced to the SGND
pin. This allows a Kelvin connection
for remotely sensing the output voltage
directly across the load, eliminating
any PC board trace resistance errors.
Applications
Figure 5 shows a 1.6V/9A applica-
tion using the LTC1735. The input
voltage can range from 6V to 26V.
Figure 6 shows a VID application
using the LTC1736 optimized for out-
put voltages of 1.6V to 1.3V with a 5V
to 24V input voltage range.
0.004Ω
C
B1
0.22µF
C2
4.7µF
D2 MBRS-
340T3
V
OUT
0.9V–2.0V
/12A
+V
IN
C
IN1
22µF
30V
R
CS1
C
O3
*
820µF
4V
+
+
M2
FDS6680A
M1, M3
FDS6680A
×2
L1
†
1.2µH
BOOST
PGND
BG
INT V
CC
SW
TG
RUN/SS
C
OSC
SGND
SENSE
+
V
IN
EXT V
CC
I
TH
FCB
V
OSENSE
SENSE
–
LTC1736
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
C
OSC1
47pF
C
C1
330pF
C1
47pF
C
C2
C
S1
, 1000pF
R
C1
33k
100pF D1
CMDSH-3
R5 10Ω
R2 10Ω
EXT V
CC
R
F1
4.7Ω
C
F1
0.1µF
JP2
LATCH-OFF
(DISABLED)
R6, 680k
INT V
CC
ON
OFF
JP1
BURST MODE FCB/SYNCRUN
R
S1
10Ω
C
IN3
22µF
30V
+
+
V
O
PGOOD
B0
B1 B2
B3
B4
VID V
CC
V
FB
C3
47pF
R1
100k
INT V
CC
PGOOD C4
1µF
JP4 ABCDE
LSB MSB
9
10
11
12
16
15
14
13
PANASONIC ETQP6F2R0HFA (201) 348-7522
PANASONIC EEFVEOG181R
†
*
Figure 6. High efficiency, VID programmable, 0.9V–2.0V/12A CPU power supply
Authors can be contacted
at (408) 432-1900
Pentium is a registered trademark of Intel Corp.
continued on page 35
Linear Technology Magazine • February 1999
7
DESIGN FEATURES
New Universal Continuous-Time Filter
with Extended Frequency Range
by Max W. Hauser
Introduction
The original LTC1562, described in
the February 1998 issue of this maga-
zine, is a compact, quadruple 2nd
order , universal, continuous-time fil-
ter that is DC accurate and user
programmable for the 10kHz–150kHz
frequency range. The LTC1562 intro-
duced Operational Filter building
blocks, whose virtual-ground input,
rail-to-rail outputs and precision
internal R and C components satisfy
diverse filter requirements and appli-
cations compactly.
1, 2, 3
The design of the LTC1562 entailed
choices in the internal R and C values
and internal amplifiers, and these
elements were optimized to minimize
wideband noise. The LTC1562-2 is a
new product with the same block
diagram, pinout and packaging, but
optimized for higher filter frequen-
cies: 20kHz to 300kHz. The inter nal
precision R and C components and
amplifiers are different in the
LTC1562-2. Besides covering a full
octave of frequencies (150kHz–
300kHz) above the range of the
LTC1562, the LTC1562-2 also over -
laps the LTC1562’s utility in the range
20kHz to 150kHz. In this frequency
range, the LTC1562-2 typically shows
reduced large-signal distortion at a
cost of slightly more noise than with
the LTC1562. For example, a 100kHz
dual 4th order Butterworth lowpass
filter with a ±5V supply, built with the
LTC1562-2 and lightly loaded, exhib-
ited 2nd-harmonic distortion of
–103dB and 3rd-harmonic distortion
of –112dB at 20kHz with an output of
1V
RMS
(2.8V
P-P
), and maintained low
distortion even with output swings
approaching the full supply voltage
(–83dB total harmonic distortion, or
THD, at 9.7V
P-P
output).
The LTC1562-2 is, therefore, the
product of choice for applications
above 150kHz as well as for applica-
tions in the 20kHz–150kHz range that
are especially distortion sensitive.
Both the LTC1562 and the LTC1562-2
can replace LC filters or filters built
from high performance op amps and
precision capacitors and resistors,
with a total surface mount board area
of 155mm
2
(0.24in
2
)—smaller than a
dime (the smallest US coin).
Comparison to the LTC1562
The LTC1562-2 both resembles and
differs fr om the L TC1562 as follows:
❏ The parts have identical pin
configurations and block
diagrams (four independently
programmable 2nd order
Operational Filter blocks with
virtual-ground inputs and rail-to-
rail outputs).
❏ In both products, the user can
program the filter’s center-
frequency parameter (f
0
) over a
wide range, using resistor values
that vary as the desired f
0
changes up or down from a
design-center value. In the
L TC1562, this design-center f
0
is
100kHz; for the LTC1562-2, the
value is 200kHz.
❏ The L TC1562 is optimized for
lower noise, the LTC1562-2 for
higher frequencies. Thus, a
single LTC1562 section can
deliver 103dB SNR in 200kHz
bandwidth (Q = 1), whereas a
single L TC1562-2 section
supports 99dB SNR in 400kHz.
V
+
V
–
SHDN
1562 F02
2ND ORDER SECTIONS
A
INV V1 V2
B
DC
INV V1 V2
INV V1 V2 INV V1 V2
SHUTDOWN
SWITCH
SHUTDOWN
SWITCH AGND
V
+
V
–
–
+
+
–
R2 R
Q
V
IN
V2 INV V1
1562 F01
C
1
sR1C*
*R1 AND C ARE PRECISION
INTERNAL COMPONENTS
Z
IN
Figure 1. LTC1562-2 block diagram
Figure 2. Single 2nd order Operational Filter section (inside
dashed line) with external components added: resistor for
Z
IN
gives lowpass at V2, bandpass at V1; capacitor for Z
IN
gives bandpass at V2, highpass at V1.
Linear Technology Magazine • February 1999
8
DESIGN FEATURES
❏ Each chip contains precision R
and C components equivalent to
eight 0.25% tolerance capacitors
and four 0.5% tolerance
resistors, as well as twelve op
amps with rail-to-rail outputs
and excellent high frequency
linearity.
❏ Both circuits operate from
nominal 5V to 10V total supplies
(single or split). Single-supply
applications can use a half-
supply, ground-reference voltage
generated on the chip.
❏ Both chips feature a power-down
mode that drops the power
supply current to zero, except for
reverse junction leakages (on the
order of 1µA total).
What the LTC1562-2 Can Do
Figure 1 is an overall diagram and
Figure 2 a per-section diagram for the
LTC1562-2. These are identical to the
diagrams for the LTC1562, except for
the values of the internal precision
components in Figure 2. In the
LTC1562-2, R1 is 7958Ω and C is
100pF. External resistors can be com-
bined with an LTC1562-2 section, as
shown in Figure 2, to define a second
order filter response with standard-
ized parameters f
0
, Q and gain. Design
equations and procedures appear in
the LTC1562-2 data sheet. For
example, in Figure 2, R2 sets f
0
; R
Q
, a
multiple of R2, sets Q; and Z
IN
sets
both the gain and the block’s func-
tion. The 3-terminal blocks minimize
the number of external parts neces-
sary for complete 2nd order sections
with programmable f
0
, Q and gain.
A resistor for Z
IN
in Figure 2 gives
simultaneous lowpass (at V3) and
bandpass (at V1) responses. The data
sheet describes other ways to exploit
the virtual ground INV input. For
example, because the V1 output in
Figure 2 shows a phase shift of 180°
at the user-set center frequency, f
0
,
summing a V1 output with a feedfor-
ward path from the signal source
yields a notch response,
2
or with dif-
ferent weighting, allpass (phase
equalization), as used in Figure 5
later in this article. Using capacitors
together with the INV input’s sum-
ming capability provides further
powerful techniques for zero and
notch responses (which, in turn,
enable elliptic highpass and lowpass
filtering). For example, the two out-
puts of each 2nd order section have a
90° phase difference, so summing V1
through a capacitor and V2 through a
resistor, into another section’s vir-
tual-ground input, gives the same
notch or allpass option mentioned
above but without devoting an addi-
tional section for phase shift.
4
Figures
5 and 9, described later, use this RC
notch method. Moreover, a capacitor
for Z
IN
in Figure 2 yields simulta-
neous highpass and bandpass
responses; the capacitor sets voltage
gain, not critical frequencies, with a
relationship of the for m Gain = C
IN
/
100pF in the LTC1562-2. Low level
signals can exploit the built-in gain
capability, which raises filter SNR
with low input voltage amplitudes.
Such abilities to tailor the use of each
block and its built-in time constants
are reminiscent of an operational
amplifier—whence the term “opera-
tional filter.”
DC performance includes a typical
lowpass input-to-output offset of 3mV
and outputs that swing (under load)
to within approximately 100mV of
each supply rail. An internal half-
supply reference point (the AGND pin)
generates a reference voltage for the
inputs and outputs in single-supply
applications. The shutdown (SHDN)
pin accepts CMOS logic levels and in
20µs puts the LTC1562-2 into a
“sleep” mode, in which the chip con-
sumes approximately 1µA (the part
will default to this state if the pin is
left open). The 16-pin dies is pack-
aged in a 20-pin SSOP (the extra pins
in the SSOP are substrate connec-
tions, to be retur ned to the negative
supply for best per for mance).
The following application examples
are tailored for specific corner fre-
quencies, which can be modified by
properly scaling the external com-
ponents, as described in the data
sheet and in LTC1562 application
articles.
2, 3
Expert application assis-
tance can be obtained by calling us at
408-954-8400, x3761. Pin numbers
in the figures that follow are for the
20-pin SSOP package, where pins 4,
7, 14 and 17 (not shown) are always
tied to the negative power supply rail.
As with other filters, achieving low
noise and distortion levels requires
electrically clean construction (as well
as equipment that can measure such
performance).
Dual 4th Order 200kHz
Butterworth Lowpass Filter
Each half of the circuit in Figure 3
provides a classic 4th order lowpass
gain roll-off (24dB per octave) with a
maximally flat passband. This schematic
includes power supply connections for a
split ±5V supply, one of the options
available for any LTC1562-2
20
19
18
16
15
13
12
11
1
2
3
5
6
8
9
10
INV C
V1 C
V2 C
V
–
AGND
V2 D
V1 D
INV D
INV B
V1 B
V2 B
V
+
SHDN
V2 A
V1 A
INV A
R
IN2
7.87k
R
Q2
10.2k
R22 7.87k
R24 7.87k
R
Q4
10.2k
R
IN4
7.87k
R
Q3
4.22k
R23 7.87k
R
IN3
7.87k
R
Q1
4.22k
R21 7.87k
R
IN1
7.87k
V
IN2
V
IN1
5V 0.1µF0.1µF–5V*
V
OUT1
V
OUT2
*V
–
ALSO AT PINS 4, 7, 14 & 17
ALL RESISTORS 1% METAL FILM
LTC1562-2
20-PIN
SSOP
Figure 3. Dual 4th order 200kHz Butterworth lowpass filter
Linear Technology Magazine • February 1999
9
DESIGN FEATURES
application (Figure 5, in a different
application, illustrates connections
for a single 5V supply). The circuit of
Figure 3 is a higher frequency varia-
tion of a 100kHz dual 4th order
Butterworth lowpass filter using the
LTC1562, which appeared in the
February 1998 Linear Technology
magazine,
1
as well as in the LTC1562
data sheet. Figure 4 shows the mea-
sured frequency response for one of
the two filters in Figure 3. This ±5V
circuit supports rail-to-rail inputs and
outputs, with output noise of
approximately 60µV
RMS
, for a maxi-
mum SNR of 95dB (compared to
100dB with the L TC1562 equivalent
at half as much bandwidth). THD in a
1V
RMS
output (2.8V
P-P
) was measured
as –87dB at 50kHz and –72dB at
100kHz.
256kHz Phase-Linearized
6th Order Lowpass Filter
Data communication and some sig-
nal antialiasing and reconstruction
applications demand filters with con-
trolled phase (or time-domain)
responses. The circuit in Figure 5
realizes a root-raised-cosine lowpass
gain response (Figure 6). For data
communications, this filter’s time-
domain pulse response (Figure 7)
approximates, in continuous time, the
ideal Nyquist-type property of cross-
ing zero at a time interval that is
equal to 1/(2f
C
). When used as a
pulse-shaping filter, this response has
the special property of producing mini-
mal intersymbol interference (ISI)
among successive data pulses at a
data rate of 2f
C
(512 kbits/second or
ksymbols/second for Figure 5) while
simultaneously limiting the trans-
mitted spectrum to a bandwidth
approaching the theoretical mini-
mum, which is f
C
.
5
Also, data or signal
acquisition (before A/D conversion)
or reconstruction (after D/A conver-
sion) can benefit from the linear-phase
(that is, constant-group-delay)
response (typically ±300ns group
delay variation over the passband from
0 to f
C
, evident in Figure 8).
The filter in Figure 5 achieves these
properties by preceding a 6th order
lowpass section (the C, A, and D quar-
ters of the LTC1562-2 chip, in that
sequence) with a 2nd order allpass
response to linearize the phase. This
combination illustrates two practical
uses of the virtual-ground inputs in
the LTC1562-2. Combining two feed-
forward paths (R
FF1
from the input
and R
B1
from a bandpass section in
the “B” quarter of the LTC1562-2)
yields the allpass equalization. Sub-
sequently, R
IN4
and C
IN4
sum together
two signals with 90° phase difference
from the two outputs of the “A” quar-
ter, with an additional 90° phase
difference caused by the capacitor , to
achieve a stopband notch at a desired
frequency.
4
Figure 5 operates from a
single supply voltage from 5V to 10V
(the AGND pin furnishes a built-in
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–8050k 1.5M
FREQUENCY (Hz)
100k
20
19
18
16*
15
13
12
11
1
2
3
5
6
8
9
10
INV C
V1 C
V2 C
V
–
AGND
V2 D
V1 D
INV D
INV B
V1 B
V2 B
V
+
SHDN
V2 A
V1 A
INV A
LTC1562-2
20-PIN
SSOP
R
B1
1.54k
R
FF1
6.19k
R
Q2
4.12k
R22 6.19k
R24 4.12k
R
Q4
7.32k
R
IN4
4.12k
R
Q3
7.32k
R23 4.12k
R
IN3
4.12k
R
IN1
7.5k
R
Q1
3.24k
R21 6.81k
V
IN
5V 0.1µF1µF
V
OUT
*V
–
ALSO AT PINS 4, 7, 14 & 17
ALL RESISTORS 1% METAL FILM
C
IN4
22pF 5%
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
10k 1M
FREQUENCY (Hz)
100k
INPUT
1V/DIV
OUTPUT
(INVERTED)
200mV/DIV
1.953µs/DIV (= 1/512kHz)
DELAY (µs)
8
7
6
5
4
3
2
1
0
FREQUENCY (kHz)
50 100 150 200 250 300 350 400
Figure 4. Frequency response of one of the
two filters in Figure 3
Figure 5. 256kHz linear-phase 6th order lowpass filter
Figure 6. Gain response of Figure 5’s circuit Figure 7. Time-domain response of Figure 5’s
circuit Figure 8. Group delay response of Figure 5’s
circuit
Linear Technology Magazine • February 1999
10
DESIGN FEATURES
half-supply ground reference) and
exhibits –80dB THD at 50kHz for a
500mV
RMS
output with a 5V supply.
175kHz 8th Order
Elliptic Highpass Filter
In Figure 9, three response notches
below the cutoff frequency suppress
the stopband and permit a narrow
transition band in a 175kHz high-
pass filter, whose measured frequency
response appears in Figure 10. Each
notch is produced by summing two
180°-different currents into a virtual-
ground “INV” summing input, one
current passing through an R
IN
and
the other (from a voltage 90° different
from the first) through a C
IN
.
4
This
circuit exhibits only 44µV
RMS
of out-
put noise over a 1MHz bandwidth and
THD of –70dB with a 200kHz signal,
0.5V
P-P
output, operating from a 5V
total supply.
400kHz Dual
6th Order Lowpass Filter
Although it is outside the 300kHz f
0
limit recommended for best accuracy,
this dual 6th order 400kHz Butter-
worth lowpass filter (Figure 11)
illustrates an extreme of bandwidth
available from the LTC1562-2 with
some compromises. The high f
0
requires unusually small resistor val-
ues, resulting in heavier loading and
an increase in distortion from the
L TC1562-2; it was also necessary to
adjust the R
Q
resistors in Figure 11
downwards to correct for Q enhance-
ment encountered when the designed
f
0
is very high.
The circuit of Figure 11 supple-
ments the eight poles of filtering in
the L TC1562-2 by driving all four of
the virtual-ground INV inputs from
R-C-R “T” networks (in place of resis-
tors) and thus obtaining additional
real poles (a method described in the
original LTC1562 application article
1
and data sheet). Two such real poles
replace the Q = 0.518 pole pair of a
conventional 6th order Butterworth
pole configuration, to good accuracy.
The measured frequency response of
one 6th order section appears in Fig-
ure 12. With ±5V power, this circuit
permits rail-to-rail inputs and out-
puts and exhibits THD, at 1V
RMS
(2.8V
P-P
) output, of –92dB at 50kHz
and –79dB at 100kHz. Output noise
20
19
18
16
15
13
12
11
1
2
3
5
6
8
9
10
INV C
V1 C
V2 C
V
–
AGND
V2 D
V1 D
INV D
INV B
V1 B
V2 B
V
+
SHDN
V2 A
V1 A
INV A
R
IN2
20.5k
R
Q2
26.7k
R22 10k
R24 4.02k
R
Q4
3.24k
R
IN4
40.2k
R
Q3
59k
R23 11.3k
R
Q1
9.09k
R21 7.15k
V
IN
5V 0.1µF0.1µF–5V*
V
OUT
*V
–
ALSO AT PINS 4, 7, 14 AND 17
ALL RESISTORS 1% METAL FILM
ALL CAPACITORS 5% STANDARD VALUES
LTC1562-2
20-PIN
SSOP
C
IN1
220pF
C
IN2
82pF
C
IN3
47pF
R
IN3
45.3k
C
IN4
100pF
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–9050k 900k
FREQUENCY (Hz)
200k
20
19
18
16
15
13
12
11
1
2
3
5
6
8
9
10
INV C
V1 C
V2 C
V
–
AGND
V2 D
V1 D
INV D
INV B
V1 B
V2 B
V
+
SHDN
V2 A
V1 A
INV A
LTC1562-2
20-PIN
SSOP
R
IN2A
1.43k R
IN2B
576Ω
R
Q2
2.26k
R22 2k
R24 2k
R
Q4
2.26k
R
IN4A
1.43k R
IN4B
576Ω
R
Q3
6.19k
R23 2k
R
IN3B
576Ω
R
IN1B
576Ω
R
IN3A
1.43k
R
IN1A
1.43k
R
Q1
6.19k
R21 2k
V
IN2
V
IN1
5V 0.1µF0.1µF–5V*
V
OUT1
V
OUT2
*V
–
ALSO AT PINS 4, 7, 14 & 17
ALL RESISTORS 1% METAL FILM
C1
1000pF
5% C2
1000pF
5%
C3
1000pF
5% C4
1000pF
5%
Figure 9. 175kHz 8th order elliptic highpass filter
Figure 10. Frequency response of Figure 9’s
circuit
Figure 11. 400kHz dual 6th order Butterworth lowpass filter
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
1M
FREQUENCY (Hz)
100k
Figure 12. Frequency response of
Figure 11’s circuit
continued on page 35
Linear Technology Magazine • February 1999
11
DESIGN FEATURES
SOT-23 Switching Regulators Deliver
Low Noise Out puts in a Small Footprint
by Steve Pietkiewicz
Introduction
As portable electronics designers con-
tinue to press for reduction in
component sizes, Linear Technology
introduces the LT1611 and LT1613
SOT -23 switching regulators. These
current mode, constant frequency
devices contain internal 36V switches
capable of generating output power
in the range of 400mW to 2W , in a 5-
lead SOT-23 package. The LT1613
has a standard positive feedback pin
and is designed to regulate positive
voltages. The LT1611 has a novel
feedback scheme designed to directly
regulate negative output voltages
without the use of level-shifting cir -
cuitry. Boost, single-ended primary
inductance converters (SEPIC) and
inverting configurations are possible
with the LT1613 and LT1611. The
high voltage switch allows hard-to-
do, yet popular DC/DC converter
functions like four cells to 5V, 5V to
–5V, 5V to –15V or 5V to 15V to be
easily realized.
Both devices switch at a frequency
of 1.4MHz, allowing the use of tiny
inductors and capacitors. Many of
the components specified for use with
the L T1613 and LT1611 are 2mm or
less in height, providing a low profile
solution. The input voltage range is
1V to 10V, with 2mA quiescent
current. In shutdown mode, the qui-
escent current drops to 0.5µA. The
constant frequency switching pro-
duces low amplitude output ripple
that is easy to filter, unlike the low
frequency ripple typical of pulse-
skipping or PFM type converters.
Internally compensated current mode
control provides good transient
response.
LT1613 Boost Converter
Provides a 5V Output
Figure 1’s circuit details a boost con-
verter that delivers 5V at 200mA from
a 3.3V input. The input can range
from 1.5V to 4.5V, making the circuit
usable from a variety of input sources,
such as a 2- or 3-cell battery, single
Li-Ion cell or 3.3V supply. Efficiency,
shown in Figure 2, reaches 88% from
a 4.2V input. Start-up waveforms from
a 3.3V input into a 47Ω load are
pictured in Figure 3; the converter
reaches regulation in approximately
250µs. The device requires some bulk
capacitance due to the internal com-
pensation network used. A 10µF
ceramic output capacitor can be used
with the addition of a phase-lead
capacitor paralleled with R1; this
capacitor is typically in the 10pF–
100pF range.
LT1613 5V to 15V
Boost Converter
By changing the value of the resistive
divider, a 15V supply can be gener-
ated in a similar manner to the 5V
converter shown in Figure 1. Figure 4
depicts the converter. L1’s value has
been changed to 10µH to provide the
same di/dt slope with a higher input
voltage. The converter delivers 15V at
60mA from a 5V input, at efficiencies
up to 85%, as shown in the efficiency
graph of Figure 5.
LT1613 4-Cell to 5V SEPIC
A 4-cell battery presents a unique
challenge to the DC/DC converter
designer. A fresh battery measures
about 6.5V, above the 5V output,
while at end of life the battery voltage
will measure 3.5V, below the 5V out-
put. Simple switching regulator
topologies like boost or buck can only
increase or decrease an input voltage,
V
IN
V
IN
3.3V
V
OUT
5V/200mA
1613 • TA01
SW
L1
4.7µHD1
GND
LT1613
L1: MURATA LQH3C4R7M24 (814) 237-1431
OR SUMIDA CD43-4R7 (847) 956-0666
C1, C2: AVX TAJA156M010R (803) 946-0362
D1: MOTOROLA MBR0520 (800) 441-2447
C1
15µFC2
15µF
R2
121k
R1
374k
FBSHDN SHDN
+ +
LOAD CURRENT (mA)
0 50 100 150 200 250 300 350 400
EFFICIENCY (%)
1613 TA01a
100
90
80
70
60
50
VIN = 4.2V
VIN = 3.5V
VIN = 2.8V
VIN = 1.5V
V
OUT
1V/DIV
I
L1
500mA/DIV
SHDN
5V/DIV
100µs/DIV
Figure 1. This boost converter steps up a 1.5V to 4.2V input to 5V.
It can deliver 250mA from a 3.3V input.
Figure 2. Efficiency of Figure 1’s boost
converter
Figure 3. Boost converter start-up with 3.3V input into a 50Ω load
Linear Technology Magazine • February 1999
12
DESIGN FEATURES
which will not do the trick in this
situation. The solution is a SEPIC. A
dual-winding inductor or two sepa-
rate inductors are required to make
this converter. Figure 6 details the
circuit. A Sumida CLS62-150 15µH
dual inductor is specified in the appli-
cation, although two 15µH units can
be used instead. Up to 125mA can be
generated from a 3.6V input. Figure
7’s graph shows converter efficiency,
which peaks at 77%. Transient
response with a 5mA to 105mA load
step is pictured in Figure 8. The con-
verter settles to final value inside
200µs, with a maximum perturba-
tion under 200mV. The double trace
of V
OUT
under load in Figure 8 is
actually switching ripple at 1.4MHz
caused by the ESR of output capaci-
tor C2. A better (lower ESR) output
capacitor will decrease the output
ripple.
LT1611 5V to –5V
Inverting Converter
A low noise –5V output can be gener-
ated using an inverting topology with
the LT1611. This circuit, shown in
Figure 9, bears some similarity to the
SEPIC described above, but the out-
put is in series with the second
inductor. This results in a very low
noise output. The circuit can deliver
–5V at up to 150mA from a 5V input,
or up to 100mA from a 3V input.
Efficiency, described in Figure 10,
peaks at 75%. Figure 11 illustrates
the start-up waveforms. During start-
up, the switch-current increases to
approximately 1A. At this current,
the inductance of the Sumida unit
decreases, resulting in the increased
V
IN
V
IN
3V–7V V
OUT
15V/50mA
1613 • TA01
SW
L1
10µHD1
GND
LT1613
L1: MURATA LQH3C100 (814) 237-1431
C1: AVX TAJB226M016 (803) 946-0362
C2: AVX TAJA475M025
D1: MOTOROLA MBR0520 (800) 441-2447
C1
15µFC2
22µF
R2
121k
R1
1.37M
1%
FBSHDN SHDN
+ +
1nF
LOAD CURRENT (mA)
EFFICIENCY (%)
85
80
75
70
65
60
55
50
1611 TA02
0 102030405060
V
IN
= 3.6V
V
IN
= 6.5V
V
IN
= 5V
70 10080 90
VIN
VIN
4V–7V
VOUT
5V/175mA
1613 • TA01
SW
L1A
15µH
D1
GND
LT1613
L1: SUMIDA CLS62-150 15µH (847) 956-0666
C1, C2: AVX TAJA156M016 (803) 946-0362
C3: X7R CERAMIC
D1: MOTOROLA MBR0520 (800) 441-2447
C1
15µF
C2
15µF
324k
FBSHDN SHDN
+
+
L1B
15µH
1M
C3
0.22µF
LOAD CURRENT (mA)
EFFICIENCY (%)
85
80
75
70
65
60
55
50
1611 TA02
0 25 50 75 100 125 150
V
IN
= 3.6V V
IN
= 5V
V
IN
= 6.5V
175 200 225 250
ripple current noticeable in the switch-
current trace of Figure 11. After the
circuit has reached regulation, the
ripple current decreases by about a
factor of two. Switching waveforms
with a 100mA load are shown in Fig-
ure 12. Output voltage ripple is caused
by ripple current in the inductor mul-
tiplied by output capacitor ESR.
Although the 20mV
P-P
ripple pic-
tured in Figure 12 is low, significant
improvement can be obtained by
judicious component selection. Fig-
ure 13 details the same 5 to –5V
V
OUT
100mV/DIV
AC COUPLED
105mA
5mA
I
LOAD
200µs/DIV
V
IN
V
IN
5V
V
OUT
–5V/150mA
1613 • TA01
SW
L1A
22µH
D1
GND
LT1611
L1: SUMIDA CLS62-220 22µH (847) 956-0666
C1, C2: AVX TAJB226010 (803) 946-0362
C3: X7R CERAMIC
D1: MOTOROLA MBR0520 (800) 441-2447
C1
22µF
C2
22µF
10k
NFBSHDN SHDN
+
+
L1B
22µH
29.4k
C3
0.22µF
Figure 4. This 4-cell to 15V boost converter can deliver 50mA
from a 3V input.
Figure 5. Efficiency of Figure 4’s circuit
Figure 6. This single-ended primary inductance converter (SEPIC)
generates 5V from an input voltage above or below 5V.
Figure 7. Efficiency of Figure 6’s SEPIC
reaches 77%.
Figure 9. This inverting converter delivers –5V at 150mA from
a 5V input.
Figure 8. SEPIC transient response at 5V input with a 5mA to 105mA
load step
Linear Technology Magazine • February 1999
13
DESIGN FEATURES
converter function with better output
capacitors. Now, output ripple mea-
sures just 4mV
P-P
. Additionally,
transient response is improved by the
addition of phase lead capacitor C5.
Figure 14 depicts load transient
response of a 25mA to 125mA load
step. Maximum perturbation is under
30mV and the converter reaches final
value in approximately 250µs.
It is important to take notice of how
Figures 9 and 13 are drawn. D1’s
cathode is returned to the LT1611’s
GND pin before both connect to the
ground plane. This connection com-
bines the current of the switch and
diode, which conduct on alternate
phases. The summation of both cur-
rents equals a current with no abrupt
changes, minimizing di/dt induced
voltages caused by the few nanohen-
ries of inductance in the ground plane.
This summed current is then depos-
ited into the ground plane. If this
technique is not followed, 100mV
spikes can appear at the converter
output (I speak from experience: my
first several breadboards had this
problem).
Many systems, such as personal
computers, have a 12V supply avail-
able. Although the LT1611 V
IN
pin
V
OUT
2V/DIV
I
SW
500mA/DIV
V
SHDN
5V/DIV
V
OUT
200mV/DIV
AC COUPLED
I
SW
100mA/DIV
V
SW
10V/DIV
100ns/DIV
V
OUT
20mV/DIV
AC COUPLED
125mA
25mA
I
LOAD
has a 10V maximum, the 36V switch
allows a 12V supply to be used for the
inductor while the LT1611’s V
IN
pin is
still driven from 5V, as indicated in
Figure 13. Significantly more output
power can be obtained in this man-
ner, as illustrated in the efficiency
graph of Figure 15.
Figure 10. 5V to –5V inverting converter
efficiency reaches 76%.
Figure 11. 5V to –5V inverting converter start-up into a 47Ω load
Figure 12. Switching waveforms of inverting converter with 100mA load
Figure 13. Low noise inverting converter; component selection and
feedforward capacitor C5 reduce noise to 4mV
P-P
.
Figure 14. Transient response of low noise inverting converter is
under 30mV for a 25mA to 125mA load step. Steady-state output
ripple is 4mV
P-P
.
200µs/DIV
200µs/DIV
LOAD CURRENT (mA)
EFFICIENCY (%)
85
80
75
70
65
60
55
50
1611 TA02
0 25 50 75 100 125 150
V
IN
= 3V
V
IN
= 5V
V
IN
V
IN
5V
V
OUT
–5V/150mA
1613 • TA01
SW
L1A
22µH
D1
GND
LT1611
L1: SUMIDA CLS62-220 22µH (847) 956-0666
C1: AVX TAJB226010 (803) 946-0362
C2: X7R CERAMIC
C3: Y5V CERAMIC
C4: SANYO POSCAP 10TPC68M (619) 661-6835
D1: MOTOROLA MBR0520 (800) 441-2447
C1
22µF
C3
4.7µF
C4
68µF
10k
NFBSHDN SHDN
+
+
L1B
22µH
29.4k
C2
0.22µF
C5
2.2nF
5V OR 12V
(SEE TEXT)
continued on page 23
Linear Technology Magazine • February 1999
14
DESIGN FEATURES
Versatile New Switching Regulator
Fits in SO-8 by Craig Varga
Introduction
Linear Technology recently introduced
the LTC1530 synchronous buck
regulator controller. Although pack-
aged in an 8-pin SO, it has proven to
be remarkably capable and versatile.
The part is loosely based on the
popular LTC1430, but with numerous
enhancements. Features include
current limiting that senses the volt-
age across the R
DS(ON)
of the high-side
MOSFET (no sense resistor required),
built in soft-start, 1% accurate refer-
ence, gate drivers capable of handling
large MOSFETs, and micropower
shutdown. The error amplifier trans-
conductance is higher than that of
previous generation parts and is
trimmed for accuracy and stabilized
over temperature. The I
MAX
current,
which programs current limit, has a
positive temperature coefficient to
help cancel the positive temperature
coefficient of the MOSFET’s R
DS(ON)
.
This allows for more consistent cur-
rent limit over temperature. Although
intended primarily for buck regulator
designs, the part has been successfully
designed into boost, positive-to-
negative and negative-to-positive
converters.
A Quick Look at the Insides
Figure 1 is the basic block diagram.
The L TC1530 is a voltage mode con-
trol, synchronous buck regulator
controller. An on-chip oscillator gen-
erates a 300kHz ramp waveform. The
output of the error amplifier is com-
pared to this ramp by the PWM
comparator. So far, nothing extraor -
dinary. Current-limit circuitry,
however, is a little more unusual.
Instead of the traditional current
sense resistor , the LTC1530 relies on
the R
DS(ON)
of the high-side MOSFET
as its source of load current informa-
tion. This saves the space, cost and
the power dissipation of an additional
resistor in the power path. The pro-
gramming current (I
MAX
) has a positive
temperature coefficient that approxi-
mates the positive TC of a MOSFET’s
R
DS(ON)
. This tends to flatten the cur-
rent-limit trip point as a function of
temperature. In a slight overload, the
LTC1530 provides “square current
limiting.” In other words, the regula-
tor starts to look like a current source.
In the event of a significant overload,
should the output fall to less than
one-half of the nominal output volt-
age, the soft-start capacitor will be
discharged very quickly. This forces
–
+
–
+
–
+
COMP
I
COMP
C
SS
I
SS
M
SS
DISDR
INTERNAL
OSCILLATOR
LOGIC AND
THERMAL SHUTDOWN
POWER DOWN
4
–
+
V
REF
V
REF
– 3%
I
FB
V
REF
+ 3%
ERR MIN
g
m
= 2m
PWM
–
+
MAX
PV
CC
FB
+
–
G2
G1
8
1
7
3V
SENSE
FB
FOR FIXED
VOLTAGE
VERSIONS
3V
OUT
V
REF
V
REF
V
REF
– 3%
V
REF
+ 3%
V
REF
/2
V
REF
/2
1530 BD
LVC
CC
6
I
MAX
I
MAX
5
HCL*
MONO
M
HCL
*HCL = HARD CURRENT LIMIT
Ω
Figure 1. LTC1530 block diagram
Linear Technology Magazine • February 1999
15
DESIGN FEATURES
the regulator into shutdown for a
period of time, typically a few milli-
seconds. After the time delay, the
supply attempts to restart. If the over-
load still exists, the hiccup mode
operation will continue. Once the short
is removed, the regulator will start
normally.
Unlike its predecessor, the
LTC1530’s soft-start capacitor is
internal. The start-up rise time was
chosen to satisfy the vast majority of
application requirements. Turn on is
clean, well controlled and monotonic.
Since dynamic performance is of
extreme importance in many of today’s
systems, the LTC1530 incorporates
several features to provide improved
response times to load transients.
First are the min/max comparators.
These are a pair of comparators that
continuously monitor the output volt-
age. If the output is more than 3% on
either side of nominal, the appropri-
ate comparator forces the duty factor
to maximum or zero in an attempt to
restore the output to the correct level
as quickly as possible. Eventually,
the error amplifier and main feed-
back loop will catch up and force the
output to settle nicely. The error am-
plifier is also an improvement over
earlier designs. The transconduct-
ance and output impedance have both
been increased substantially from the
LTC1430 values. This has the effect
of raising the DC open-loop gain of
the amplifier, resulting in better line
and load regulation. Transconduct-
ance is also trimmed to ensure
accuracy. The result is more predict-
able and repeatable loop response.
The amplifier g
m
is temperature com-
pensated so loop gain stays nearly
constant over temperature extremes.
The LTC1530 also has a low power
shutdown mode. If the Comp pin is
pulled to ground with an open collec-
tor or open drain transistor, the
LTC1530’s quiescent current will drop
to approximately 45µA.
Virtually all integrated circuits have
some quirks that will get you in trouble
if you don’t pay attention. The
LTC1530 is no exception. Care must
be taken in choosing the power MOS-
FETs used in circuits that depend on
a charge pump to supply gate-drive
power. It is essential to select a FET
for the upper device that will be almost
fully enhanced before the PV
CC
sup-
ply voltage reaches 8V with whatever
main input voltage happens to be
available. Failure to heed this
requirement can lead to a circuit that
may not start up properly at all times.
Standard logic-level FETs work fine.
Be sure V
TH
is less than 2V in the
worst case.
The cause of this start-up phe-
nomenon is related to the way the
current limit circuit behaves. Below a
PV
CC
level of 8V, current limit is dis-
abled. Assume for the sake of this
discussion that the main input sup-
ply is derived from 5V . At turn on, as
the charge pump gradually pushes
the PV
CC
supply upward, the current-
limit circuit wakes up at 8V on PV
CC
.
If the 5V supply is exactly 5V, the gate
drive available for the FET is only 3V
(8V – 5V). If the FET’s R
DS(ON)
is very
high relative to its nominal value at
this point, the current-limit circuit
may activate in a misguided attempt
to maintain control of the output cur-
rent. If, at the same time, the output
voltage has come up to less than one-
half of its final value, the LTC1530
will respond by discharging the soft-
1
4
3
2
5
8
6
7
PV
CC
COMP
V
FB
GND
I
MAX
G1
I
FB
G2
LTC1530S8
+
+
+
12V
V
IN
5V
ON/OFF
C1
1µF
16V
C4
1µF
16V
C11
4.7µF, 16V
KEMET Ta
C2–C3
330µF, 6.3V
KEMET Ta
×2
Q3
2N7002
R10
10k
C5
68pF
C6
1800pF
R5
10k
R4 750Ω
Q1
IRF7805
Q2
IRF7805
R3 100Ω
L1
3.5µH
ETQP6F3R5SFA
C13
2200pF
R6
1.0Ω
D1
MBRS-
130T3
C12
0.22µF
D2 BAT54S
OPTIONAL, INSTALL IF NO 12V
JP1 JP2 JP3
R7
75k
1%
1.5V
R8
68.1k
1%
1.8V
R9
20.5k
1%
2.5V
R2
11.3k
1%
3.3V
V
OUT
1.5V, 1.8V,
2.5V OR 3.3V
AT 6A
C7
270pF R1
16.5k
1%
C8–C10
330µF
6.3V
KEMET Ta
×3
V
REF
= 1.233V
Figure 2. 6A buck regulator; output voltage is jumper selectable for 1.5V, 1.8V, 2.5V or 3.3V.
Figure 3. Output voltage at turn-on for Figure
2’s circuit
Linear Technology Magazine • February 1999
16
DESIGN FEATURES
start capacitor and trying to initiate a
restart.
As long as the output voltage has
reached a level of greater than one-
half of its final value before the PV
CC
voltage reaches 8V, the output will
continue to rise in current limit. If the
output is below this level, start-up is
not ensured. If the PV
CC
supply is
derived from a 12V source instead of
charge pumped from the 5V supply,
this problem cannot occur.
A Few Circuit Examples
The LTC1530 turns out to be a rather
versatile device. Although intended
as a buck regulator, the part has been
successfully used in boost and buck-
boost designs. Figure 2 is a classic
buck topology. The circuit was
designed to handle approximately 6A
while maintaining a low profile. Input
and output capacitors are tantalum
devices. The inductor is a very low DC
resistance design for high efficiency.
The input is 5V, while the output
voltage can be jumper selected for
3.3V, 2.5V, 1.8V or 1.5V. The photo
in Figure 3 shows the output voltage
rise at turn on. A clean, monotonic
rise is evident.
Figure 4 is a 3A design that has a
total height of less than 2.4mm. The
inductor is a Gowanda part #50-324,
which mounts through a hole in the
PCB for a total height above the board
of approximately 1.5mm. Output
ripple voltage is approximately
10mV
P-P
at a 3A load with the specified
Panasonic SP series output capaci-
tors. There are several options for the
main inductor. The overall smallest
size available is an IHLP-2525 by
Dale Electronics. It’s 3mm tall but
only 6.4mm on a side. Output ripple
is about 50% higher with this inductor.
Figure 5 is an example of a syn-
chronous boost regulator. The input
is 3.3V and the output is 5V. The
circuit is rated for a maximum output
current of 6A. Since the output cur-
1
4
3
2
5
8
6
7
PV
CC
COMP
V
FB
GND
I
MAX
G1
I
FB
G2
LTC1530S8
+
+
V
IN
5V
C12
1µF
16V
C4
1µF
10V
C11
4.7µF
16V
C2–C3
47µF, 6.3V
×2
C7
68pF
C5
4700pF
R2
10k
R4 750Ω
Q1A
Si4936DY
Q1B
Si4936DY
R5 100Ω
L1
4.7µH
C11
0.1µF
D1 BAT54S
V
OUT
3.3V/3A
C8–C10
56µF
4V
×3
V
REF
= 1.233V
C6
470pF
R1
16.9k
1%
R7
10k
1%
C2, C3, C8–C10: PANASONIC SP TYPE
(201) 348-7522
L1: GOWANDA 50-324 (716) 532-2234
OR DALE IHLP2525 (605) 665-1627
(SEE TEXT)
+
5
4
3
2
1
7
6
8
IMAX
COMP
VFB
GND
PVCC
G2
IFB
G1
LTC1530S8
+
+
+
C3
1µF
16V
C1–C2
470µF
16V
×2
C15
100pF C14
0.022µF
R1
12k
Q1
IRF7801
Q2
IRF7801
L2**
10µHVOUT
5V/6A
C7, C8,
C11
470µF
6.3V
×3
C10
470µF
6.3V
VREF =
1.233V
R2
71.5k
1%
R3
23.2k
1%
L1*
2.5µH
+
LTC1517-5
VIN
GND
VOUT
C1–
C1+
1
2
3
5
4
D3
FMM914
C6
0.22µF
C12
10µF
16V
C13
1µF
16V
C4
1µF X7R
C9
1µF
X7R
VIN
3.3V
D1
MBR0530
D2
MBR0530 C5
0.22µF
L1: PULSE PE-53681 (619) 674-8100
L2: COILCRAFT DS3316P-102 (847) 639-6400
*
**
RS1
(OPTIONAL,
SEE TEXT)
Figure 4. 3.3V/3A regulator
Figure 5. 5V/6A synchronous boost regulator
Linear Technology Magazine • February 1999
17
DESIGN FEATURES
rent wavefor m is discontinuous, the
output ripple is inherently large in
any boost regulator. The second stage
LC filter is added to clean things up a
bit. The feedback divider connects to
the output before the LC filter for a
reason. If the divider is connected
after the LC filter, the extra 180° of
phase shift above the LC cor ner fre-
quency will make the regulator’s
feedback loop unstable. The DC re-
sistance of the inductor is small, so
the ef fect on load regulation is mini-
mal.
The LTC1517 charge pump is used
to generate a sufficiently high voltage
for the LTC1530 to function correctly
and also to ensure adequate gate
drive for the power MOSFETs. It runs
from the 3.3V input and delivers a
regulated 5V output. Once the main
output comes into regulation, charge
pump power is derived through D2.
This causes the LTC1517’s regulated
output voltage set-point to be exceeded
and D3 back biases, shutting the
LTC1517 down. Note that current
limit is disabled in this design by
grounding I
MAX
and connecting I
FB
to
V
IN
. Since in the boost topology there
is a direct DC path from input to
output, there is no point in using the
current limit feature except to protect
against inductor saturation. It is also
worth mentioning that the FET R
DS(ON)
cannot be used as the current sense
resistor in this application because
FET Q2’s drain is not common to V
IN
.
If inductor saturation protection is
desirable, it is possible to install a
small value current sense resistor
between C2 and L1. Install an appro-
priate value resistor (R
S1
) between C2
and L1; connect the I
MAX
pin to the C2
side of R
S1
(instead of ground) and
connect I
FB
directly to the input side
of L1. Just don’t expect the circuit to
limit current in the event of a short
circuit.
Figure 6 is a positive input to nega-
tive 5V output design. Since the
LTC1530 needs to be referenced to
the –5V output, the design requires
exter nal gate-drive circuitry for both
the main and synchronous FETs. The
absolute maximum voltage rating of
the LTC1530’s gate drive would be
exceeded if the high-side gate were
driven directly. Q3 and the associated
parts at the input to the LTC1693
gate driver provide the required level-
shift function. The synchronous FET
is driven by the other half of the
LTC1693. The driver is only required
at this location to match the propaga-
tion delay of the high-side drive.
Failure to pay attention to these details
will result in severely degraded effi-
ciency. Output currents of up to 4A
can be obtained from this circuit.
Like the boost regulator, the output
currents are discontinuous, so ripple
on the output is somewhat high. A
small, second-stage LC filter can eas-
ily remedy this if desired.
Conclusion
The LTC1530 is a small, versatile
controller that is usable in numerous
topologies and over a wide range of
power levels. In the basic buck appli-
cations for which it was designed, the
LTC1530 permits the designer to
realize very simple, low parts count
designs that require minimal real
estate. The part provides clean turn-
on and current-limit characteristics.
With a little ingenuity, it is possible to
develop circuits dif ferent than those
that the part’s designers intended,
but which give excellent performance
nonetheless.
1
4
3
2
5
8
6
7
PV
CC
COMP
V
SENSE
GND
I
MAX
G1
I
FB
G2
LTC1530-ADJ
+
+
+
+
+
+
+
R3
1.3k
C2
27µFR4
2.0k
C3
10µFC4
0.1µF
Q4
2N3906
C1
1000pF R
C
4.7k
C
C
0.22µF
R1
2.7k
R8
470Ω
1/4W
R9 1k
D2
MBR0530T1
D1
MBR0530T1
Q3
2N7002
C7
4.7µFC6
0.1µF
365
4Q1
Q2
CIN
V
OUT
–5V/5A
C
OUT
L1
2.5µH
87
2
1
C8
4.7µF
1/2 LTC1693-2
1/2
LTC1693-2
R10
47Ω
D3
1N4148
C5
6.8µF
R2
100Ω
D4
1N4148
R6
1k
R5
2.96k
VIN 5V
PANASONIC ETQP6F2R5FA
(201) 348-7522
3× SANYO 10MV1200GX
4× SANYO 6MV1500GX
(619) 661-6835
SUD50N03-10
L1:
C
IN
:
C
OUT
:
Q1, Q2:
R7 3.3Ω
Figure 6. 5V to –5V/4A synchronous switching, inverting polarity converter