UC1843A-SP www.ti.com............................................................................................................................................................................................... SLUS872 - JANUARY 2009 RAD-TOLERANT CLASS V, CURRENT-MODE PWM CONTROLLER FEATURES 1 * * * * * * * * * * * * * * (1) QML-V Qualified, SMD 5962-86704 Rad-Tolerant: 30 kRad (Si) TID (1) Optimized for Offline and DC-to-DC Converters Low Start-Up Current (<0.5 mA) Trimmed Oscillator Discharge Current Automatic Feed Forward Compensation Pulse-by-Pulse Current Limiting Enhanced Load Response Characteristics Undervoltage Lockout With Hysteresis Double-Pulse Suppression High-Current Totem-Pole Output Internally Trimmed Bandgap Reference 500-kHz Operation Low RO Error Amplifier Radiation tolerance is a typical value based upon initial device qualification with dose rate = 10 mrad/sec. Radiation Lot Acceptance Testing is available - contact factory for details. JG PACKAGE (TOP VIEW) Comp 1 8 VREF VFB 2 7 VCC ISENSE 3 6 Output RT/CT 4 5 Gnd DESCRIPTION The UC1843A control IC is a pin-for-pin compatible improved version of the UC1843. Providing the necessary features to control current-mode switched-mode power supplies, this device has the following improved features. Start up current is guaranteed to be less than 0.5 mA. Oscillator discharge is trimmed to 8.3 mA. During undervoltage lockout, the output stage can sink at least 10 mA at less than 1.2 V for VCC over 5 V. BLOCK DIAGRAM 7 8 5 7 4 6 5 2 1 3 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009, Texas Instruments Incorporated UC1843A-SP SLUS872 - JANUARY 2009............................................................................................................................................................................................... www.ti.com ORDERING INFORMATION (1) (1) (2) TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING -55C to 125C CDIP - JG 5962-8670409VPA UC1843A-SP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage, low-impedance source IO 30 V Supply current Self limiting Output current 1 A 5 J Output energy (capacitive load) VI Input voltage (VFB, ISENSE) -0.3 V to 6.3 V Error amplifier output sink current PD Power dissipation (TA = 25C) Tstg Storage temperature range Tlead Lead temperature (soldering, 10 seconds) (1) (2) 10 mA 1W -65C to 150C 300C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (TA = TJ = -55C to 125C), unless otherwise noted. MIN VCC Supply voltage MAX UNIT 12 25 V Sink/source output current (continuous or time average) 0 200 mA Reference load current 0 20 mA ELECTRICAL CHARACTERISTICS VCC = 15 V, RT = 10 k, CT = 3.3 nF, TA = TJ = -55C to 125C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 4.94 UNIT Reference Section Output voltage TJ = 25C, IO = 1 mA 5 5.06 Line regulation VCC = 12 V to 25 V 6 20 mV Load regulation IL = 1 mA to 20 mA 6 25 mV Total output variation Over line, load, and temperature Output noise voltage 10 Hz f 10 kHz, TJ = 25C Short-circuit output current 4.9 5.1 V V 50 -30 V -100 -180 mA 52 57 kHz 0.2 1 % Oscillator Section Initial accuracy TJ = 25C Voltage stability VCC = 12 V to 25 V Temperature stability TJ = -55C to 125C 5 Amplitude VRT/CT peak to peak 1.7 Discharge current (1) (1) 2 47 TJ = 25C, VRT/CT = 2 V 7.8 VRT/CT = 2 V 7.5 8.3 % V 8.8 8.8 mA This parameter is measured with RT = 10 k to VREF. This contributes approximately 300 A of current to the measurement. The total current flowing into the RT/CT pin will be approximately 300 A higher than the measured value. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843A-SP UC1843A-SP www.ti.com............................................................................................................................................................................................... SLUS872 - JANUARY 2009 ELECTRICAL CHARACTERISTICS (continued) VCC = 15 V, RT = 10 k, CT = 3.3 nF, TA = TJ = -55C to 125C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.45 2.50 2.55 mV -0.3 -1 A Error Amp Section Input voltage VComp = 2.5 V Input bias current Open-loop voltage gain VO = 2 V to 4 V 65 90 dB Unity-gain bandwidth TJ = 25C (2) 0.7 1 MHz PSRR VCC = 12 V to 25 V 60 70 dB Output sink current VFB = 2.7 V, VComp = 1.1 V 2 6 mA Output source current VFB = 2.3 V, VComp = 5 V -0.5 -0.8 mA High-level output voltage VFB = 2.3 V, RL = 15 k to ground Low-level output voltage VFB = 2.7 V, RL = 15 k to VREF 5 6 V 0.7 1.1 V 3 3.15 V/V 1 1.1 Current Sense Section Gain (3) (4) 2.85 (3) Maximum input signal VComp = 5 V PSRR VCC = 12 V to 25 V (3) 0.9 70 Input bias current Delay to output VISENSE = 0 to 2 V (2) V dB -2 -10 A 150 300 ns 0.1 0.4 V 1.5 2.2 V Output Section Output low-level voltage Output high-level voltage ISINK = 20 mA ISINK = 200 mA ISOURCE = 20 mA 13 13.5 ISOURCE = 200 mA 12 13.0 Rise time CL = 1 nF, TJ = 25C (2) Fall time UVLO saturation V V 50 150 ns CL = 1 nF, TJ = 25C (2) 50 150 ns VCC = 5 V, ISINK = 10 mA 0.7 1.2 V Undervoltage Lockout Section Start threshold Minimum operation voltage after turn-on 7.8 8.4 9 V 7 7.6 8.2 V 94 96 100 % 0 % 0.3 0.5 mA 11 17 mA PWM Section Maximum duty cycle Minimum duty cycle Total Standby Current Start-up current (2) (3) (4) Operating supply current VFB = VISENSE = 0 V VCC zener voltage ICC = 25 mA 30 34 V Parameters ensured by design and/or characterization, if not production tested. Parameter measured at trip point of latch with VFB = 0 V. Gain defined as: G = VComp/VISENSE; VISENSE = 0 to 0.8 V. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843A-SP 3 UC1843A-SP SLUS872 - JANUARY 2009............................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION Amp can Source and Sink up to 0.5mA, and Sink up to 2mA. Figure 1. Error Amplifier Configuration During UVLO, the Output is low. Figure 2. Undervoltage Lockout Peak Current (IS) is Determined By The Formula 1.0V ISMAX RS A small RC filter may be required to suppress switch transients. Figure 3. Current-Sense Circuit 4 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843A-SP UC1843A-SP www.ti.com............................................................................................................................................................................................... SLUS872 - JANUARY 2009 Figure 4. Output Saturation Characteristics Figure 5. Error Amplifier Open-Loop Frequency Response Oscillator Frequency vs Timing Resistance Maximum Duty Cycle vs Timing Resistor Figure 6. Oscillation Section Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843A-SP 5 UC1843A-SP SLUS872 - JANUARY 2009............................................................................................................................................................................................... www.ti.com High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sam ple the oscillator waveform and apply an adjustable ramp to pin 3. Figure 7. Open-Loop Laboratory Test Fixture A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes. Figure 8. Slope Compensation 6 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843A-SP UC1843A-SP www.ti.com............................................................................................................................................................................................... SLUS872 - JANUARY 2009 Power Supply Specifications 1. Input Voltage 2. Line Isolation 3. Switching Frequency 4. Efficiency Full Load 95VAC to 130VA (50 Hz/60Hz) 3750V 40kHz 70% 5. Output Voltage: A. +5V, 5%; 1A to 4A load Ripple voltage: 50mV P-P Max B. +12V, 3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max C. -12V , 3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max Figure 9. Offline Flyback Regulator Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1843A-SP 7 PACKAGE OPTION ADDENDUM www.ti.com 24-Feb-2009 PACKAGING INFORMATION Orderable Device Status (1) 5962-8670406VPA 5962-8670406VXA Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) Package Type Package Drawing ACTIVE CDIP JG 8 1 TBD ACTIVE LCCC FK 20 1 TBD 5962-8670409VPA PREVIEW CDIP JG 8 TBD Call TI Call TI UC1843AJQMLV ACTIVE CDIP JG 8 1 TBD Call TI Call TI UC1843ALQMLV ACTIVE LCCC FK 20 1 TBD Call TI Call TI A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UC1843A-SP : UC1843A * Catalog: * Enhanced Product: UC1843A-EP NOTE: Qualified Version Definitions: - TI's standard catalog product * Catalog * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 1 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MCER001A - JANUARY 1995 - REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. 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