1
FEATURES
1
2
3
45
6
7
8
Gnd
Output
VCC
VREF
R /C
T T
ISENSE
VFB
Comp
DESCRIPTION
7
5
4
2
1
3
8
7
6
5
UC1843A-SP
www.ti.com
............................................................................................................................................................................................... SLUS872 – JANUARY 2009
RAD-TOLERANT CLASS V, CURRENT-MODE PWM CONTROLLER
JG PACKAGE•QML-V Qualified, SMD 5962-86704
(TOP VIEW)•Rad-Tolerant: 30 kRad (Si) TID
(1)
•Optimized for Offline and DC-to-DC Converters•Low Start-Up Current ( < 0.5 mA)•Trimmed Oscillator Discharge Current•Automatic Feed Forward Compensation•Pulse-by-Pulse Current Limiting•Enhanced Load Response Characteristics
The UC1843A control IC is a pin-for-pin compatible•Undervoltage Lockout With Hysteresis
improved version of the UC1843. Providing the•Double-Pulse Suppression
necessary features to control current-modeswitched-mode power supplies, this device has the•High-Current Totem-Pole Output
following improved features. Start up current is•Internally Trimmed Bandgap Reference
guaranteed to be less than 0.5 mA. Oscillator•500-kHz Operation
discharge is trimmed to 8.3 mA. During undervoltage•Low R
O
Error Amplifier
lockout, the output stage can sink at least 10 mA atless than 1.2 V for V
CC
over 5 V.(1) Radiation tolerance is a typical value based upon initial devicequalification with dose rate = 10 mrad/sec. Radiation LotAcceptance Testing is available - contact factory for details.
BLOCK DIAGRAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
UC1843A-SP
SLUS872 – JANUARY 2009 ...............................................................................................................................................................................................
www.ti.com
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
– 55 ° C to 125 ° C CDIP – JG 5962-8670409VPA UC1843A-SP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
over operating free-air temperature range (unless otherwise noted)
V
CC
Supply voltage, low-impedance source 30 VSupply current Self limitingI
O
Output current ± 1 AOutput energy (capacitive load) 5 µJV
I
Input voltage (V
FB
, I
SENSE
) – 0.3 V to 6.3 VError amplifier output sink current 10 mAP
D
Power dissipation (T
A
= 25 ° C) 1 WT
stg
Storage temperature range – 65 ° C to 150 ° CT
lead
Lead temperature (soldering, 10 seconds) 300 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal.
over operating free-air temperature range (T
A
= T
J
= – 55 ° C to 125 ° C), unless otherwise noted.
MIN MAX UNIT
V
CC
Supply voltage 12 25 VSink/source output current (continuous or time average) 0 200 mAReference load current 0 20 mA
V
CC
= 15 V, R
T
= 10 k Ω, C
T
= 3.3 nF, T
A
= T
J
= – 55 ° C to 125 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference Section
Output voltage T
J
= 25 ° C, I
O
= 1 mA 4.94 5 5.06 VLine regulation V
CC
= 12 V to 25 V 6 20 mVLoad regulation I
L
= 1 mA to 20 mA 6 25 mVTotal output variation Over line, load, and temperature 4.9 5.1 VOutput noise voltage 10 Hz ≤f≤10 kHz, T
J
= 25 ° C 50 µVShort-circuit output current – 30 – 100 – 180 mA
Oscillator Section
Initial accuracy T
J
= 25 ° C 47 52 57 kHzVoltage stability V
CC
= 12 V to 25 V 0.2 1 %Temperature stability T
J
= -55 ° C to 125 ° C 5 %Amplitude V
RT/CT
peak to peak 1.7 VT
J
= 25 ° C, V
RT/CT
= 2 V 7.8 8.3 8.8Discharge current
(1)
mAV
RT/CT
= 2 V 7.5 8.8
(1) This parameter is measured with R
T
= 10 k Ωto V
REF
. This contributes approximately 300 µA of current to the measurement. The totalcurrent flowing into the R
T
/C
T
pin will be approximately 300 µA higher than the measured value.
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Product Folder Link(s): UC1843A-SP
UC1843A-SP
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............................................................................................................................................................................................... SLUS872 – JANUARY 2009
ELECTRICAL CHARACTERISTICS (continued)V
CC
= 15 V, R
T
= 10 k Ω, C
T
= 3.3 nF, T
A
= T
J
= – 55 ° C to 125 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Error Amp Section
Input voltage V
Comp
= 2.5 V 2.45 2.50 2.55 mVInput bias current – 0.3 – 1 µAOpen-loop voltage gain V
O
= 2 V to 4 V 65 90 dBUnity-gain bandwidth T
J
= 25 ° C
(2)
0.7 1 MHzPSRR V
CC
= 12 V to 25 V 60 70 dBOutput sink current V
FB
= 2.7 V, V
Comp
= 1.1 V 2 6 mAOutput source current V
FB
= 2.3 V, V
Comp
= 5 V – 0.5 – 0.8 mAHigh-level output voltage V
FB
= 2.3 V, R
L
= 15 k Ωto ground 5 6 VLow-level output voltage V
FB
= 2.7 V, R
L
= 15 k Ωto V
REF
0.7 1.1 V
Current Sense Section
Gain
(3) (4)
2.85 3 3.15 V/VMaximum input signal V
Comp
= 5 V
(3)
0.9 1 1.1 VPSRR V
CC
= 12 V to 25 V
(3)
70 dBInput bias current – 2 – 10 µADelay to output V
ISENSE
= 0 to 2 V
(2)
150 300 ns
Output Section
I
SINK
= 20 mA 0.1 0.4 VOutput low-level voltage
I
SINK
= 200 mA 1.5 2.2 VI
SOURCE
= 20 mA 13 13.5 VOutput high-level voltage
I
SOURCE
= 200 mA 12 13.0 VRise time C
L
= 1 nF, T
J
= 25 ° C
(2)
50 150 nsFall time C
L
= 1 nF, T
J
= 25 ° C
(2)
50 150 nsUVLO saturation V
CC
= 5 V, I
SINK
= 10 mA 0.7 1.2 V
Undervoltage Lockout Section
Start threshold 7.8 8.4 9 VMinimum operation voltage after turn-on 7 7.6 8.2 V
PWM Section
Maximum duty cycle 94 96 100 %Minimum duty cycle 0 %
Total Standby Current
Start-up current 0.3 0.5 mAOperating supply current V
FB
= V
ISENSE
= 0 V 11 17 mAV
CC
zener voltage I
CC
= 25 mA 30 34 V
(2) Parameters ensured by design and/or characterization, if not production tested.(3) Parameter measured at trip point of latch with V
FB
= 0 V.(4) Gain defined as: G = ΔV
Comp
/ΔV
ISENSE
; V
ISENSE
= 0 to 0.8 V.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): UC1843A-SP
APPLICATION INFORMATION
Amp can Source and Sink up to 0.5mA, and Sink up to 2mA.
During UVLO, the Output is low.
A small RC filter may be required to suppress switch transients.
Peak Current (I ) is Determined By The Formula
S
ISMAX ′1.0V
RS
UC1843A-SP
SLUS872 – JANUARY 2009 ...............................................................................................................................................................................................
www.ti.com
Figure 1. Error Amplifier Configuration
Figure 2. Undervoltage Lockout
Figure 3. Current-Sense Circuit
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Product Folder Link(s): UC1843A-SP
Oscillator Frequency vs Timing Resistance Maximum Duty Cycle vs Timing Resistor
UC1843A-SP
www.ti.com
............................................................................................................................................................................................... SLUS872 – JANUARY 2009
Figure 4. Output Saturation Characteristics
Figure 5. Error Amplifier Open-Loop Frequency Response
Figure 6. Oscillation Section
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): UC1843A-SP
High peak currents associated with capacitive loads necessi-
tate careful grounding techniques. Timing and bypass capaci-
tors should be connected close to pin 5 in a single point
ground. The transistor and 5k potentiometer are used to sam -
ple the oscillator waveform and apply an adjustable ramp to
pin 3.
A fraction of the oscillator ramp can be resistively
summed with the current sense signal to provide slope
compensation for converters requiring duty cycles over
50%.
Note that capacitor, C, forms a filter with R2 to suppress
the leading edge switch spikes.
UC1843A-SP
SLUS872 – JANUARY 2009 ...............................................................................................................................................................................................
www.ti.com
Figure 7. Open-Loop Laboratory Test Fixture
Figure 8. Slope Compensation
6Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): UC1843A-SP
UC1843A-SP
www.ti.com
............................................................................................................................................................................................... SLUS872 – JANUARY 2009
Figure 9. Offline Flyback Regulator
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): UC1843A-SP
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-8670406VPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
5962-8670406VXA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8670409VPA PREVIEW CDIP JG 8 TBD Call TI Call TI
UC1843AJQMLV ACTIVE CDIP JG 8 1 TBD Call TI Call TI
UC1843ALQMLV ACTIVE LCCC FK 20 1 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1843A-SP :
•Catalog: UC1843A
•Enhanced Product: UC1843A-EP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 24-Feb-2009
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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