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FEATURES
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
GND
A2
A3
VCC (3.3 V)
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC (3.3 V)
A16
A17
GND
CLKIN
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
VCC (5 V)
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VREF
B16
B17
GND
CLKOUT
CLKBA
CEBA
DESCRIPTION/ORDERING INFORMATION
SN74GTL1661617-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERWITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
•Member of the Texas Instruments Widebus™Family
•UBT™ Transceiver Combines D-Type Latchesand D-Type Flip-Flops for Operation inTransparent, Latched, Clocked, orClock-Enabled Modes•OEC™ Circuitry Improves Signal Integrity andReduces Electromagnetic Interference•GTL Buffered CLKAB Signal (CLKOUT)•Translates Between GTL/GTL+ Signal Levelsand LVTTL Logic Levels•Supports Mixed-Mode (3.3 V and 5 V) SignalOperation on A-Port and Control Inputs•Equivalent to '16601 Function•I
off
Supports Partial-Power-Down ModeOperation
•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors onA Port•Distributed V
CC
and GND Pins MinimizeHigh-Speed Switching Noise•Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)
The SN74GTL16616 is a 17-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTLsignal-level translation. Combined D-type flip-flops and D-type latches allow for transparent, latched, clocked,and clocked-enabled modes of data transfer identical to the '16601 function. Additionally, this device provides fora copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logiclevels (CLKIN). This device provides an interface between cards operating at LVTTL logic levels and a backplaneoperating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing(<1 V), reduced input threshold levels, and OEC™ circuitry.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube SN74GTL16616DL GTL16616SSOP – DL–40°C to 85°C Tape and reel SN74GTL16616DLR GTL16616TSSOP – DGG Tape and reel SN74GTL16616DGGR GTL16616
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus, UBT, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1994–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERWITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
The user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or the preferredhigher noise margin GTL+ (V
TT
= 1.5 V and V
REF
= 1 V) signal levels. GTL+ is the Texas Instruments derivativeof the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL orGTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-Vtolerant. V
REF
is the reference input voltage for the B port. V
CC
(5 V) supplies the internal and GTL circuitry, whileV
CC
(3.3 V) supplies the LVTTL output buffers.
Data flow in each direction is controlled by output-enable ( OEAB and OEBA), latch-enable (LEAB and LEBA),and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable ( CEAB and CEBA)inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low,the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus datais stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, theoutputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A issimilar to that of A to B, but uses OEBA, LEBA, CLKBA, and CEBA.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldownresistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(1)
INPUTS
OUTPUT
MODEBCEAB OEAB LEAB CLKAB A
X H X X X Z IsolationL L L H X B
0
(2)
Latched storage of A dataL L L L X B
0
(3)
X L H X L L
TransparentX L H X H HLLL↑L L
Clocked storage of A dataLLL↑H HH L L X X B
0
(3)
Clock inhibit
(1) A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA.The condition when OEAB and OEBA are both low at the same time is not recommended.(2) Output level before the indicated steady-state input conditions were established, provided thatCLKAB was high before LEAB went low(3) Output level before the indicated steady-state input conditions were established
2
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1D
C1
CLK
1D
C1
CLK
B1
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
1 of 17 Channels
CE
CE
CLKOUT
CLKIN
1
56
55
2
28
30
29
27
354
31
26
VREF 35
SN74GTL1661617-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERWITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
3
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1) (2) (3) (4)
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERWITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
3.3 V –0.5 4.6V
CC
Supply voltage range V5 V –0.5 7A-port and control inputs –0.5 7V
I
Input voltage range
(2)
VB port and V
REF
–0.5 4.6A port –0.5 7V
O
Voltage range applied to any output in the high or power-off state
(2)
VB port –0.5 4.6A port 128I
O
Current into any output in the low state mAB port 80I
O
Current into any A-port output in the high state
(3)
64 mAContinuous current through each V
CC
or GND ±100 mAI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mADGG package 64θ
JA
Package thermal impedance
(4)
°C/WDL package 56T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3) This current flows only when the output is in the high state and V
O
> V
CC
.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN NOM MAX UNIT
3.3 V 3.15 3.3 3.45V
CC
Supply voltage V5 V 4.75 5 5.25GTL 1.14 1.2 1.26V
TT
Termination voltage VGTL+ 1.35 1.5 1.65GTL 0.74 0.8 0.87V
REF
Reference voltage VGTL+ 0.87 1 1.1B port V
TTV
I
Input voltage VExcept B port 5.5B port V
REF
+ 50 mVV
IH
High-level input voltage VExcept B port 2B port V
REF
– 50 mVV
IL
Low-level input voltage VExcept B port 0.8I
IK
Input clamp current –18 mAI
OH
High-level output current A port –32 mAA port 64I
OL
Low-level output current mAB port 40T
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.(2) Normal connection sequence is GND first, V
CC
= 5 V second, and V
CC
= 3.3 V, I/O, control inputs, V
TT
and V
REF
(any order) last.(3) V
TT
and R
TT
can be adjusted to accommodate backplane impedances if the dc recommended I
OL
ratings are not exceeded.(4) V
REF
can be adjusted to optimize noise margins, but normally is two-thirds V
TT
.
4
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Electrical Characteristics
SN74GTL1661617-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERWITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IK
V
CC
(3.3 V) = 3.15 V, V
CC
(5 V) = 4.75 V, I
I
= –18 mA –1.2 VV
CC
(3.3 V) = 3.15 V to 3.45 V,
I
OH
= –100 µA V
CC
– 0.2V
CC
(5 V) = 4.75 V to 5.25 V,V
OH
A port VI
OH
= –8 mA 2.4V
CC
(3.3 V) = 3.15 V, V
CC
(5 V) = 4.75 V
I
OH
= –32 mA 2I
OL
= 100 µA 0.2I
OL
= 16 mA 0.4A port V
CC
(3.3 V) = 3.15 V, V
CC
(5 V) = 4.75 VV
OL
I
OL
= 32 mA 0.5 VI
OL
= 64 mA 0.55B port V
CC
(3.3 V) = 3.15 V, V
CC
(5 V) = 4.75 V, I
OL
= 40 mA 0.4Control inputs V
CC
= 0 or 3.45 V, V
CC
(5 V) = 0 or 5.25 V, V
I
= 5.5 V 10V
I
= 5.5 V 20A port V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V V
I
= V
CC
(3.3 V) 1I
I
µAV
I
= 0 –30V
I
= V
CC
(3.3 V) 5B port V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V
V
I
= 0 –5I
off
V
CC
= 0, V
I
or V
O
= 0 to 4.5 V 100 µAV
I
= 0.8 V 75I
I(hold)
A port V
CC
(3.3 V) = 3.15 V, V
CC
(5 V) = 4.75 V V
I
= 2 V –75 µAV
I
= 0 to V
CC
(3.3 V)
(2)
±500A port V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V, V
O
= 3 V 1I
OZH
µAB port V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V, V
O
= 1.2 V 10A port V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V, V
O
= 0.5 V –1I
OZL
µAB port V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V, V
O
= 0.4 V –10Outputs high 1V
CC
(3.3 V) = 3.45 V,I
CC
A or B port V
CC
(5 V) = 5.25 V, I
O
= 0, Outputs low 5 mA(3.3 V)
V
I
= V
CC
(3.3 V) or GND
Outputs disabled 1Outputs high 120V
CC
(3.3 V) = 3.45 V,I
CC
A or B port V
CC
(5 V) = 5.25 V, I
O
= 0, Outputs low 120 mA(5 V)
V
I
= V
CC
(3.3 V) or GND
Outputs disabled 120V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V,∆I
CC
(3)
1 mAA-port or control inputs at V
CC
(3.3 V) or GND, One input at 2.7 VC
i
Control inputs V
I
= 3.15 V or 0 3.5 pFA port V
O
= 3.15 V or 0 12C
io
pFB port Per IEEE Std 1194.1 5
(1) All typical values are at V
CC
(3.3 V) = 3.3 V, V
CC
(5 V) = 5 V, T
A
= 25°C.(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state toanother.
(3) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC
or GND.
5
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Timing Requirements
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERWITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
over recommended ranges of supply voltage and operating free-air temperature,V
TT
= 1.2 V and V
REF
= 0.8 V for GTL (unless otherwise noted) (see Figure 1 )
MIN MAX UNIT
f
clock
Clock frequency 95 MHzLEAB or LEBA high 3.3t
w
Pulse duration nsCLKAB or CLKBA high or low 5.5A before CLKAB ↑1.3B before CLKBA ↑2.5A before LEAB ↓0t
su
Setup time nsB before LEBA ↓1.1CEAB before CLKAB ↑2.2CEBA before CLKBA ↑2.7A after CLKAB ↑1.6B after CLKBA ↑0.4A after LEAB ↓4t
h
Hold time nsB after LEBA ↓3.5CEAB after CLKAB ↑1.1CEBA after CLKBA ↑0.9
6
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Switching Characteristics
SN74GTL1661617-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERWITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
over recommended ranges of supply voltage and operating free-air temperature,V
TT
= 1.2 V and V
REF
= 0.8 V for GTL (see Figure 1 )
FROM TOPARAMETER MIN TYP
(1)
MAX UNIT(INPUT) (OUTPUT)
f
max
95 MHzt
PLH
1.7 3 4.4A B nst
PHL
1.4 2.8 4.5t
PLH
2.3 3.8 5.4LEAB B nst
PHL
2.2 3.7 5.3t
PLH
2.4 4 5.7CLKAB B nst
PHL
2.1 3.7 5.4t
PLH
4.7 6.1 8.1CLKAB CLKOUT nst
PHL
5.7 7.9 11.3t
PHL
2.1 3.6 5.1OEAB B or CLKOUT nst
PLH
2.1 3.8 5.6t
r
Transition time, B outputs (0.5 V to 1 V) 1.2 nst
f
Transition time, B outputs (1 V to 0.5 V) 0.7 nst
PLH
1.7 4 6.7B A nst
PHL
1.4 2.9 4.7t
PLH
2.4 3.8 5.8LEBA A nst
PHL
2 3 4.6t
PLH
2.6 4 6CLKBA A nst
PHL
2.2 3.4 4.9t
PLH
7.4 10 14.4CLKOUT CLKIN nst
PHL
6.1 8.1 11.7t
en
2.8 5.3 7.8OEBA A or CLKIN nst
dis
2.7 4.3 6.4
(1) All typical values are at V
CC
(3.3 V) = 3.3 V, V
CC
(5 V) = 5 V, T
A
= 25°C.
7
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Timing Requirements
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERWITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
over recommended ranges of supply voltage and operating free-air temperature,V
TT
= 1.5 V and V
REF
= 1 V for GTL+ (unless otherwise noted) (see Figure 1 )
MIN MAX UNIT
f
clock
Clock frequency 95 MHzLEAB or LEBA high 3.3t
w
Pulse duration nsCLKAB or CLKBA high or low 5.5A before CLKAB ↑1.3B before CLKBA ↑2.3A before LEAB ↓0t
su
Setup time nsB before LEBA ↓1.3CEAB before CLKAB ↑2.2CEBA before CLKBA ↑2.7A after CLKAB ↑1.6B after CLKBA ↑0.6A after LEAB ↓4t
h
Hold time nsB after LEBA ↓3.5CEAB after CLKAB ↑1.1CEBA after CLKBA ↑0.9
8
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Switching Characteristics
SN74GTL1661617-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERWITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
over recommended ranges of supply voltage and operating free-air temperature,V
TT
= 1.5 V and V
REF
= 1 V for GTL+ (see Figure 1 )
FROM TOPARAMETER MIN TYP
(1)
MAX UNIT(INPUT) (OUTPUT)
f
max
95 MHzt
PLH
1.7 3 4.4A B nst
PHL
1.4 2.9 4.6t
PLH
2.3 3.8 5.4LEAB B nst
PHL
2.2 3.7 5.4t
PLH
2.4 4 5.7CLKAB B nst
PHL
2.1 3.8 5.5t
PLH
4.7 6.1 8.1CLKAB CLKOUT nst
PHL
5.7 8 11.4t
PLH
2.1 3.6 5.1OEAB B or CLKOUT nst
PHL
2.1 3.8 5.7t
r
Transition time, B outputs (0.5 V to 1 V) 1.4 nst
f
Transition time, B outputs (1 V to 0.5 V) 1 nst
PLH
1.6 3.9 6.6B A nst
PHL
1.3 2.8 4.5t
PLH
2.4 3.8 5.8LEBA A nst
PHL
2 3 4.6t
PLH
2.6 4 6CLKBA A nst
PHL
2.2 3.4 4.9t
PLH
7.3 9.9 14.3CLKOUT CLKIN nst
PHL
6 8 11.5t
en
2.8 5.3 7.8OEBA A or CLKIN nst
dis
2.7 4.3 6.4
(1) All typical values are at V
CC
(3.3 V) = 3.3 V, V
CC
(5 V) = 5 V, T
A
= 25°C.
9
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PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1 6 V
Open
GND
500 Ω
500 Ω TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
GND
tPLH tPHL
Output
Control
(see Note B)
Output
Waveform 1
S1 at 6 V
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VREF VREF
VTT
VOL
0 V
VOL + 0.3 V
VOH − 0.3 V
≈0 V
3 V
0 V
0 V
3 V
0 V
tw
Input
(see Note B)
3 V
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)†
VOLTAGE WA VEFORMS
PULSE DURATION
(VM = 1.5 V for A port and VREF for B port)†
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
(A port and CLKIN)
Timing
Input
Data Input
A Port
Output
Input
VTT
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
25 Ω
LOAD CIRCUIT FOR B OUTPUTS
tPLH tPHL
0 V
VOH
VOL
Input
(see Note B)
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
Output
VTT
VREF VREF 0 V
VTT
Data Input
B Port
†All control inputs are TTL levels.
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. The outputs are measured one at a time, with one transition per measurement.
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
VM V VM V
VREF VREF
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERWITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
V
TT
= 1.2 V, V
REF
= 0.8 V FOR GTL AND V
TT
= 1.5 V, V
REF
= 1 V FOR GTL+
Figure 1. Load Circuits and Voltage Waveforms
10
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
74GTL16616DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74GTL16616DGGRG4 ACTIVE TSSOP DGG 56 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74GTL16616DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74GTL16616DLR ACTIVE SSOP DL 56 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74GTL16616DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74GTL16616DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
SN74GTL16616DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74GTL16616DGGR TSSOP DGG 56 2000 346.0 346.0 41.0
SN74GTL16616DLR SSOP DL 56 1000 346.0 346.0 49.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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