TUSB1310 USB 3.0 Transceiver PRODUCT PREVIEW Data Manual PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Literature Number: SLLSE16 December 2009 TUSB1310 SLLSE16 - DECEMBER 2009 www.ti.com PRODUCT PREVIEW 2 Copyright (c) 2009, Texas Instruments Incorporated TUSB1310 www.ti.com SLLSE16 - DECEMBER 2009 USB 3.0 Transceiver Check for Samples: TUSB1310 1 PRODUCT OVERVIEW 1.1 Features * Universal Serial Bus (USB) - Single Port 5.0-Gbps USB 3.0 Physical Layer Transceiver * One 5.0-Gbps SuperSpeed Conneciton * One 480-Mbps HS/FS/LS Connection - Fully Compliant with USB 3.0 Specification, Revision 1.0: TID #T B D - Supports 3+ Meters USB 3.0 Cable Length - PIPE to Link Layer Controller * Supports 16-Bit SDR Mode at 250 MHz * Compliant With PHY Interface for the USB Architectures (PIPE), Version 3.0 - ULPI to Link Layer Controller * Supports 8-Bit SDR Mode at 60 MHz * Supports Synchronous Mode and Low Power Mode * Compliant with UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1 * General Features - IEEE 1149.1 JTAG Support - IEEE 1149.6 JTAG support for the SuperSpeed Port - Operates on a Single Reference Clock Selectable from 20, 25, 30 or 40 MHz - 3.3-, 1.8-, and 1.1-V Supply Voltages - 1.8-V PIPE and ULPI I/O - Available in Lead-Free 175-Ball 12- x 12-nF BGA Package (175ZAY) 1.2 * * * * * * * * * * Target Applications Surveillance Cameras Multimedia Handset Smartphone Digital Still Camera Portable Media Player Personal Navigation Device Audio Dock Video IP Phone Wireless IP Phone Software Defined Radio 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright (c) 2009, Texas Instruments Incorporated PRODUCT PREVIEW 1 TUSB1310 SLLSE16 - DECEMBER 2009 1.3 www.ti.com Introduction The TUSB1310 is a single port, 5.0-Gbps USB 3.0 physical layer transceiver operating off of a single reference clock provided by either a crystal or an external reference clock. The reference clock frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310 provides the clock to the USB controller. The use of a single reference clock allows the TUSB1310 to provide a cost effective USB 3.0 solution with few external components and a low implementation cost. The USB controller interfaces to the TUSB1310 via a PIPE (SuperSpeed) and a ULPI (USB2.0) interface. The 16-bit PIPE operates off of a 250-MHz interface clock. The ULPI supports 8-bit operations with a 60-MHz interface clock. USB 3.0 reduces active and idle power consumption with improved power management features. The TUSB1310 low power states are controlled by the USB controller via the PIPE interface. SuperSpeed USB uses existing USB software infrastructure by keeping the existing software interfaces and software drivers intact. In addition, SuperSpeed USB retains backward compatibility with USB 2.0 based products by using the same form-factor Type-A connector and cables. Existing USB 2.0 devices will work with new USB 3.0 hosts and new USB 3.0 devices with work with legacy USB 2.0 hosts. PRODUCT PREVIEW Figure 1-1. Typical Application 1.4 Functional Block Diagram The USB physical layer handles the low level USB protocol and signaling. This includes data serialization and deserialization, 8b/10b encoding, analog buffers, elastic buffers and receiver detection. It shifts the clock domain of the data from the USB rate to one that is compatible with the link layer controller. The SuperSpeed USB contains SSTXP/SSTXN and SSRXP/SSRXP differential pairs and uses the PIPE to communicate with the link layer controller. The Non-SuperSpeed USB has a DP/DM differential pair and communicates with the link layer controller via the ULPI. The TUSB1310 reference clock is connected to an internal crystal oscillator, spread spectrum clock and PLL which provides clocks to all functional blocks and to the CLKOUT pin for the link layer controller. A JTAG interface is used for IEEE1149.1 and IEEE1149.6 boundary scan. 4 PRODUCT OVERVIEW Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 TUSB1310 SLLSE16 - DECEMBER 2009 PRODUCT PREVIEW www.ti.com Figure 1-2. Functional Block Diagram PRODUCT OVERVIEW Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 5 TUSB1310 SLLSE16 - DECEMBER 2009 2 www.ti.com PIN DESCRIPTIONS TYPE DESCRIPTION I Input O Output I/O Input/output PD, PU 2.1 Internal pull-down / pull-up S Strapping pin P Power Supply G Ground Configuration Pins The configuration pins are not latched by RESETN. Table 2-1. Configuration Pins PRODUCT PREVIEW SIGNAL NAME TYPE PIN NO. MODE NAME PHY_MODE1 I, PD H12 USB Must be set to 0. Operates as USB 3.0 transceiver. PHY_MODE0 I, PU J12 USB Must be set to 1. Operates as USB 3.0 transceiver. 2.2 DESCRIPTION PIPE The TUSB1310 supports 16-bit SDR mode with a 250-MHz clock. Table 2-2. PIPE Signal Description SIGNAL NAME TX_CLK TYPE I BALL NO. DESCRIPTION K1 TX_DATA and TX_DATAK clock for source synchronous PIPE. This clock frequency is the same as PCLK frequency. The rising edge of the clock is the reference for all signals. TX_DATA15 G2 TX_DATA14 H2 TX_DATA13 H1 TX_DATA12 J2 TX_DATA11 L3 TX_DATA10 L2 TX_DATA9 M2 TX_DATA8 TX_DATA7 I M1 N1 TX_DATA6 P1 TX_DATA5 N2 TX_DATA4 P2 TX_DATA3 N3 TX_DATA2 P3 TX_DATA1 N4 TX_DATA0 P5 TX_DATAK1 TX_DATAK0 PCLK 6 I O G1 J1 A6 Parallel USB SuperSpeed data input bus. The 16 bits represent 2 symbols of transmit data where TX_DATA7-0 is the first symbol to be transmitted, and TX_DATA15-8 is the second symbol. Data/Control for the symbols of transmit data. TX_DATAK0 corresponds to the low-byte of TX_DATA, TX_DATAK1 to the upper byte. Parallel interface data clock. All data movement across the parallel PIPE is synchronous to this clock. This clock operates at 250 MHz. The rising edge of the clock is the reference for all signals. PIN DESCRIPTIONS Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 TUSB1310 www.ti.com SLLSE16 - DECEMBER 2009 PIPE Signal Description (continued) TYPE BALL NO. RX_DATA15 B9 RX_DATA14 A9 RX_DATA13 A8 RX_DATA12 B8 RX_DATA11 B5 RX_DATA10 B4 RX_DATA9 A4 RX_DATA8 RX_DATA7 O RX_DATA6 B3 A3 B1 RX_DATA4 C2 RX_DATA3 C1 RX_DATA2 D1 RX_DATA1 D2 RX_DATA0 E2 RX_DATAK1 RX_VALID Parallel USB SuperSpeed data output bus. The 16 bits represent 2 symbols of receive data where RX_DATA7-0 is the first symbol received, and RX_DATA15-8 is the second. A2 RX_DATA5 RX_DATAK0 DESCRIPTION B7 O O A7 Data/Control for the symbols of receive data. RX_DATAK0 corresponds to the low-byte of RX_DATA, RX_DATAK1 to the upper byte. A value of zero indicates a data byte; a value of 1 indicates a control byte. F1 Active High. Indicates symbol lock and valid data on RX_DATA and RX_DATAK. PRODUCT PREVIEW SIGNAL NAME CONTROL AND STATUS SIGNALS PHY_RESETN I, PU J3 Active Low. Resets the transmitter and receiver. This signal is asynchronous. TX_DETRX_LPBK I, PD M6 Active High. Used to tell the PHY to begin a receiver detection operation or to begin loopback. TX_ELECIDLE I K3 Active High. Forces TX output to electrical idle depending on the power state. RX_ELECIDLE S, I/O, PD F3 Active High. While de-asserted with the PHY in P0, P1, P2, or P3, indicates detection of LFPS. C7 Encodes receiver status and error codes for the received data stream when receiving data. RX_STATUS2 RX_STATUS1 O RX_STATUS0 POWER_DOWN1 POWER_DOWN0 I C6 BIT 2 BIT 1 BIT 0 C5 0 0 0 Received data OK 0 0 1 1 SKP ordered set added 0 1 0 1 SKP ordered set removed 0 1 1 Receiver detected 1 0 0 8B/10B decode error 1 0 1 Elastic buffer overflow 1 1 0 Elastic buffer underflow. This error code is not used if the elasticity buffer is operating in the nominal buffer empty mode. 1 1 1 Receive disparity error G3 H3 DESCRIPTION Power up and down the transceiver power states. BIT 1 BIT 0 0 0 P0, normal operation DESCRIPTION 0 1 P1, low recovery time latency, power saving state 1 0 P2, longer recovery time latency, low power state 1 1 P3, lowest power state When transitioning from P3 to P0, the signaling is asynchronous. PIN DESCRIPTIONS Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 7 TUSB1310 SLLSE16 - DECEMBER 2009 www.ti.com PIPE Signal Description (continued) SIGNAL NAME TYPE BALL NO. DESCRIPTION PHY_STATUS S, I/O, PD E3 PWRPRESENT O H11 Indicates the presence of VBUS I, PD M4 Active High. Used only when transmitting USB compliance pat-terns CP7 or CP8. Causes the transmitter to transmit an alternating sequence of 50 - 250 ones and 50 - 250 zeros - regardless of the state of the TX_DATA interface. K11 Selects transmitter de-emphasis. When the MAC changes, the TUSB1310 starts to transmit with the new setting within 128 ns. Active High. Used to communicate completion of several PHY func-tions including power management state transitions, rate change, and receiver detection. When this signal transitions during entry and exit from P3 and PCLK is not running, then the signaling is asynchronous. CONFIGURATION PINS TX_ONESZEROS TX_DEEMPH1 I, PD, PU TX_DEEMPH0 L11 TX_MARGIN2 TX_MARGIN1 M11 PRODUCT PREVIEW I, PD TX_MARGIN0 M10 M9 BIT 1 BIT 0 0 0 -6 dB de-emphasis DESCRIPTION 0 1 -3.5 dB de-emphasis 1 0 No de-emphasis 1 1 Reserved Selects transmitter voltage levels BIT 2 BIT 1 BIT 0 TX_SWING DESCRIPTION 0 0 0 0 Normal operating range 800 mV - 1200 mV 0 0 0 1 Normal operating range 400 mV - 700 mV 0 0 1 0 800 mV - 1200 mV 1 400 mV - 700 mV 0 1 0 0 700 mV - 900 mV 1 300 mV - 500 mV 0 400 mV - 600 mV 1 200 mV - 400 mV 0 200 mV - 400 mV 1 100 mV - 200 mV 0 1 1 1 1 Don't care Controls transmitter voltage swing level TX_SWING I, PD M5 0 Full swing 1 Half swing Active High. Tells PHY to do a polarity inversion on the received data. Inverted data show up on RX_DATA15-0 within 20 PCLK clocks after RX_POLARITY is asserted. RX_POLARITY I, PD C8 0 PHY does no polarity inversion. 1 PHY does polarity inversion. Controls presence of receiver terminations RX_TERMINATION I, PD D3 0 Terminations removed 1 Terminations present RATE I, PU L6 ELAS_BUF_MODE I, PD C9 Controls the link signaling rate The RATE is always 1. Selects elasticity buffer operating mode 0 Nominal half full buffer mode 1 Nominal empty buffer mode 8 PIN DESCRIPTIONS Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 TUSB1310 www.ti.com 2.3 SLLSE16 - DECEMBER 2009 ULPI The ULPI (ultra low pin count interface) is a low pin count USB PHY to a link layer controller interface. The ULPI consists of the interface and the ULPI registers. The TUSB1310 is always the master of the ULPI bus. Table 2-3. ULPI Signal Description SIGNAL NAME ULPI_CLK TYPE BALL NO. O P11 ULPI_DATA7 N6 ULPI_DATA6 P6 ULPI_DATA5 N7 ULPI_DATA4 ULPI_DATA3 DESCRIPTION 60-MHz interface clock. All ULPI signals are synchronous to ULPI_CLK. The ULPI_CLK is always a 60-MHz output of the TUSB1310. In low power mode, the ULPI_CLK is not driven. S, I/O, PD P7 N8 ULPI_DATA2 P8 ULPI_DATA1 P9 ULPI_DATA0 N9 Data bus. Driven to 00h by the Link when the ULPI bus is idle. 8-bit data timed on rising edge of ULPI_CLK O M7 0 ULPI_DATA lines are inputs 1 ULPI_DATA lines are outputs ULPI_STP S, I, PU M8 Active High. The Link must assert ULPI_STP to signal the end of a USB transmit packet or a register write operation. The ULPI_STP signal must be asserted in the cycle after the last data byte is presented on the bus. The ULPI_STP has an internal weak pull-up to safeguard against false commands on the ULPI_DATA lines. ULPI_NXT O N11 Active High. The PHY asserts ULPI_NXT to throttle all data types, except register read data and the RX CMD. The PHY also asserts ULPI_NXT and ULPI_DIR simultaneously to indicate USB receive activity, if ULPI_DIR was previously low. The PHY is not allowed to assert ULPI_NXT during the first cycle of the TX CMD driven by the Link. 2.3.1 ULPI Modes The TUSB1310 supports synchronous mode and low power mode. The default mode is synchronous mode. The synchronous mode is a normal operation mode. The ULPI_DATA are synchronous to ULPI_CLK. The low power mode is used during power down and no ULPI_CLK. The TUSB1310 sets ULPI_DIR to output and drives LineState signals and interrupts. Table 2-4. ULPI Synchronous and Low Power Mode Functions SYNCHRONOUS LOW POWER ULPI_CLK(OUT) ULPI_DATA7(I/O) ULPI_DATA6(I/O) ULPI_DATA5(I/O) ULPI_DATA4{I/O} ULPI_DATA3(I/O) ULPI_INT (OUT) ULPI_DATA2(I/O) ULPI_DATA1(I/O) ULPI_LINESTATE1(OUT) ULPI_DATA0(I/O) ULPI_LINE_STATE0 (OUT) ULPI_DIR(OUT) ULPI_STP(IN) PIN DESCRIPTIONS Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 9 PRODUCT PREVIEW Controls the direction of the ULPI_DATA bus ULPI_DIR TUSB1310 SLLSE16 - DECEMBER 2009 www.ti.com ULPI Synchronous and Low Power Mode Functions (continued) SYNCHRONOUS LOW POWER ULPI_NXT(OUT) 2.4 Clocking Table 2-5. Clock Signal Name Description SIGNAL NAME TYPE BALL NO. DESCRIPTION XI I A12 Crystal Input. This pin is the clock reference input for the TUSB1310. The TUSB1310 supports either a crystal unit, or a 1.8-V clock input. Frequencies supported are 20, 25, 30, or 40 MHz. XO O A11 Crystal output. If a 1.8-V clock input is connected to XI, XO must be left open. CLKOUT O D10 OOBCLK is driven in U3 mode. 2.5 JTAG Interface The JTAG Interface is used for board-level boundary scan. All digital IO support IEEE1149.1 boundary scan and SuperSpeed differential pairs support IEEE1149.6 boundary scan. PRODUCT PREVIEW Table 2-6. JTAG Signal Name Description SIGNAL NAME TYPE BALL NO. JTAG_TCK I, PU G11 JTAG test clock JTAG_TMS I, PU D11 JTAG test mode select JTAG_TDI I, PU E11 JTAG test data input JTAG_TRSTN I, PD E12 JTAG test asynchronous reset. Active Low. O F11 JTAG test data output JTAG_TDO 2.6 DESCRIPTION Reset and Output Control Interface Table 2-7. Reset and Output Control Signal Description SIGNAL NAME RESETN OUT_ENABLE 2.7 TYPE BALL NO. I J11 Active Low. Resets the transmitter and receiver. This signal is asynchronous. L10 Active High. This can be connected to a 1.8-V power on reset signal on the PCB in order to avoid static current and signal contention during power up. 0: Disable all driver outputs while IO powers are supplied, but internal control circuit powers are not present during power up. 1: Enable all driver outputs during normal operation. I DESCRIPTION Strap Options Strapping pins are latched by reset de-assertion in the TUSB1310. Table 2-8. Strapping Options SIGNAL NAME TYPE BALL NO. DESCRIPTION Selects an input clock source XTAL_DIS (RX_ELECIDLE) S, I/O, PD F3 0 Crystal Input 1 Clock Input Selects PIPE PIPE_16BIT (PHY_STATUS) S, I/O, PD E3 0 16-bit PIPE SDR mode Must be 0 at reset. 10 PIN DESCRIPTIONS Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 TUSB1310 www.ti.com SLLSE16 - DECEMBER 2009 Strapping Options (continued) SIGNAL NAME TYPE BALL NO. DESCRIPTION Active High. Puts PIPE into isolate mode. When in the isolate mode, TUSB1310 does not respond to packet data present at TX_DATA15-0, TXDATAK1-0 inputs and presents a high imped-ance on the PCLK, RX_DATA15-0, RX_DATAK1-0, RX_VALID outputs. When in the isolate mode, the TUSB1310 will continue to respond to ULPI. Once the isolate mode bit in ULPI register is cleared, the USB interfaces will start transmitting packet data on TX_DATA15-0 and driving PCLK, RX_DATA15-0, RX_DATA1-0, and RX_VALID. ISO_START (ULPI_DATA7) S, I/O, PD N6 ULPI_8BIT (ULPI_DATA6) S, I/O, PD P6 Selects ULPI data bus bit width 0 8-bit ULPI SDR mode Must be set to 0. Select input reference clock frequency for on-chip oscillator REFCLKSEL1, REFCLKSEL0 (ULPI_DATA5, ULPI_DATA4) 2.8 S, I/O, PD N7 P7 00 20 MHz on XI 01 25 MHz on XI 10 30 MHz on XI 11 40 MHz on XI USB Interfaces SIGNAL NAME SSTXP SSTXM TYPE O SSRXP I SSRXM DP I/O DM VBUS 2.9 I BALL NO. H14 J14 E14 F14 P14 P13 N12 PRODUCT PREVIEW Table 2-9. USB Interface Signal Name Descriptions DESCRIPTION USB SuperSpeed transmitter differential pair USB SuperSpeed receiver differential pair USB non-SuperSpeed differential pair USB VBUS pin Connected through an external voltage divider. Special Connect Table 2-10. Special Connect Signal Descriptions SIGNAL NAME R1EXT TYPE O BALL NO. DESCRIPTION L14 High precision external resistor used for calibration. The R1 value shall be 10 k 1% accuracy. R1EXTRTN I L13 R1 ground reference. This pin is not connected to board ground. CEXT O M14 Connected to an external 4.7-nF capacitor CEXTSS O A14 Connected to an external 4.7-nF capacitor D6 D5 RSVD I/O C13 C14 Must be left open. K4 J4 PIN DESCRIPTIONS Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 11 TUSB1310 SLLSE16 - DECEMBER 2009 www.ti.com 2.10 Power and Ground Table 2-11. Power/Ground Signal Descriptions SIGNAL NAME TYPE VDDA3P3 P BALL NO. P12 DESCRIPTION Analog 3.3-V power supply N14 VDDA1P8 P A13 Analog 1.8-V power supply C10 C12 K14 VDDA1P1 G13 P Analog 1.1-V power supply G14 D14 C11 PRODUCT PREVIEW VDD1P8 VDD1P1 P P B2 C3 D4 D7 D8 D9 E4 F4 G4 H4 L5 L4 M3 L7 L8 L9 A5 A10 B6 B10 E1 F2 K2 L1 N5 P4 N10 P10 K13 D13 Digital IO 1.8-V power supply Digital 1.1-V power supply C4 VSSA G B14 B13 J13 H13 F13 E13 K12 L12 G12 Analog ground D12 N13 M12 M13 VSSOSC 12 G B12 Oscillator ground If using a crystal, this should not be connected to PCB ground polane. See Chapter 5 for guidelines. If using an oscillator, this should be connected to PCB ground. PIN DESCRIPTIONS Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 TUSB1310 www.ti.com SLLSE16 - DECEMBER 2009 Power/Ground Signal Descriptions (continued) SIGNAL NAME TYPE BALL NO. F6 G F7 F8 F9 G6 G7 G8 G9 J6 J7 H6 H7 H8 H9 J8 J9 B11 F12 Digital ground PRODUCT PREVIEW VSS DESCRIPTION PIN DESCRIPTIONS Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB1310 13 PACKAGE OPTION ADDENDUM www.ti.com 15-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TUSB1310IZAYR PREVIEW NFBGA ZAY 175 1000 TBD Call TI Call TI TUSB1310ZAY PREVIEW NFBGA ZAY 175 160 TBD Call TI Call TI TUSB1310ZAYR PREVIEW NFBGA ZAY 175 1000 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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