PRODUCTPREVIEW
TUSB1310
USB 3.0 Transceiver
Data Manual
PRODUCT PREVIEW information concerns products in the formative
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
Literature Number: SLLSE16
December 2009
PRODUCTPREVIEW
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2Copyright © 2009, Texas Instruments Incorporated
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USB 3.0 Transceiver
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1 PRODUCT OVERVIEW
1.1 Features
1• Universal Serial Bus (USB)
– Single Port 5.0-Gbps USB 3.0 Physical Layer Transceiver
• One 5.0-Gbps SuperSpeed Conneciton
• One 480-Mbps HS/FS/LS Connection
– Fully Compliant with USB 3.0 Specification, Revision 1.0: TID #T B D
– Supports 3+ Meters USB 3.0 Cable Length
– PIPE to Link Layer Controller
• Supports 16-Bit SDR Mode at 250 MHz
• Compliant With PHY Interface for the USB Architectures (PIPE), Version 3.0
– ULPI to Link Layer Controller
• Supports 8-Bit SDR Mode at 60 MHz
• Supports Synchronous Mode and Low Power Mode
• Compliant with UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1
• General Features
– IEEE 1149.1 JTAG Support
– IEEE 1149.6 JTAG support for the SuperSpeed Port
– Operates on a Single Reference Clock Selectable from 20, 25, 30 or 40 MHz
– 3.3-, 1.8-, and 1.1-V Supply Voltages
– 1.8-V PIPE and ULPI I/O
– Available in Lead-Free 175-Ball 12- x 12-nF BGA Package (175ZAY)
1.2 Target Applications
• Surveillance Cameras
• Multimedia Handset
• Smartphone
• Digital Still Camera
• Portable Media Player
• Personal Navigation Device
• Audio Dock
• Video IP Phone
• Wireless IP Phone
• Software Defined Radio
1
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative Copyright © 2009, Texas Instruments Incorporated
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
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1.3 Introduction
The TUSB1310 is a single port, 5.0-Gbps USB 3.0 physical layer transceiver operating off of a single
reference clock provided by either a crystal or an external reference clock. The reference clock
frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310 provides the clock to the USB
controller. The use of a single reference clock allows the TUSB1310 to provide a cost effective USB 3.0
solution with few external components and a low implementation cost.
The USB controller interfaces to the TUSB1310 via a PIPE (SuperSpeed) and a ULPI (USB2.0) interface.
The 16-bit PIPE operates off of a 250-MHz interface clock. The ULPI supports 8-bit operations with a
60-MHz interface clock.
USB 3.0 reduces active and idle power consumption with improved power management features. The
TUSB1310 low power states are controlled by the USB controller via the PIPE interface.
SuperSpeed USB uses existing USB software infrastructure by keeping the existing software interfaces
and software drivers intact. In addition, SuperSpeed USB retains backward compatibility with USB 2.0
based products by using the same form-factor Type-A connector and cables. Existing USB 2.0 devices will
work with new USB 3.0 hosts and new USB 3.0 devices with work with legacy USB 2.0 hosts.
Figure 1-1. Typical Application
1.4 Functional Block Diagram
The USB physical layer handles the low level USB protocol and signaling. This includes data serialization
and deserialization, 8b/10b encoding, analog buffers, elastic buffers and receiver detection. It shifts the
clock domain of the data from the USB rate to one that is compatible with the link layer controller.
The SuperSpeed USB contains SSTXP/SSTXN and SSRXP/SSRXP differential pairs and uses the PIPE
to communicate with the link layer controller. The Non-SuperSpeed USB has a DP/DM differential pair and
communicates with the link layer controller via the ULPI. The TUSB1310 reference clock is connected to
an internal crystal oscillator, spread spectrum clock and PLL which provides clocks to all functional blocks
and to the CLKOUT pin for the link layer controller.
A JTAG interface is used for IEEE1149.1 and IEEE1149.6 boundary scan.
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Figure 1-2. Functional Block Diagram
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2 PIN DESCRIPTIONS
TYPE DESCRIPTION
I Input
O Output
I/O Input/output
PD, PU Internal pull-down / pull-up
S Strapping pin
P Power Supply
G Ground
2.1 Configuration Pins
The configuration pins are not latched by RESETN.
Table 2-1. Configuration Pins
SIGNAL NAME TYPE PIN NO. MODE NAME DESCRIPTION
PHY_MODE1 I, PD H12 USB Must be set to 0. Operates as USB 3.0 transceiver.
PHY_MODE0 I, PU J12 USB Must be set to 1. Operates as USB 3.0 transceiver.
2.2 PIPE
The TUSB1310 supports 16-bit SDR mode with a 250-MHz clock.
Table 2-2. PIPE Signal Description
SIGNAL NAME TYPE BALL NO. DESCRIPTION
TX_DATA and TX_DATAK clock for source synchronous PIPE. This clock frequency is
TX_CLK I K1 the same as PCLK frequency. The rising edge of the clock is the reference for all signals.
TX_DATA15 G2
TX_DATA14 H2
TX_DATA13 H1
TX_DATA12 J2
TX_DATA11 L3
TX_DATA10 L2
TX_DATA9 M2 Parallel USB SuperSpeed data input bus.
TX_DATA8 M1
I The 16 bits represent 2 symbols of transmit data where TX_DATA7-0 is the first symbol to
TX_DATA7 N1 be transmitted, and TX_DATA15-8 is the second symbol.
TX_DATA6 P1
TX_DATA5 N2
TX_DATA4 P2
TX_DATA3 N3
TX_DATA2 P3
TX_DATA1 N4
TX_DATA0 P5
TX_DATAK1 G1 Data/Control for the symbols of transmit data. TX_DATAK0 corresponds to the low-byte of
ITX_DATA, TX_DATAK1 to the upper byte.
TX_DATAK0 J1 Parallel interface data clock. All data movement across the parallel PIPE is synchronous
PCLK O A6 to this clock. This clock operates at 250 MHz. The rising edge of the clock is the reference
for all signals.
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PIPE Signal Description (continued)
SIGNAL NAME TYPE BALL NO. DESCRIPTION
RX_DATA15 B9
RX_DATA14 A9
RX_DATA13 A8
RX_DATA12 B8
RX_DATA11 B5
RX_DATA10 B4
RX_DATA9 A4 Parallel USB SuperSpeed data output bus.
RX_DATA8 B3
O The 16 bits represent 2 symbols of receive data where RX_DATA7-0 is the first symbol
RX_DATA7 A3 received, and RX_DATA15-8 is the second.
RX_DATA6 A2
RX_DATA5 B1
RX_DATA4 C2
RX_DATA3 C1
RX_DATA2 D1
RX_DATA1 D2
RX_DATA0 E2
RX_DATAK1 B7 Data/Control for the symbols of receive data. RX_DATAK0 corresponds to the low-byte of
O RX_DATA, RX_DATAK1 to the upper byte. A value of zero indicates a data byte; a value
RX_DATAK0 A7 of 1 indicates a control byte.
RX_VALID O F1 Active High. Indicates symbol lock and valid data on RX_DATA and RX_DATAK.
CONTROL AND STATUS SIGNALS
PHY_RESETN I, PU J3 Active Low. Resets the transmitter and receiver. This signal is asynchronous.
Active High. Used to tell the PHY to begin a receiver detection operation or to begin
TX_DETRX_LPBK I, PD M6 loopback.
TX_ELECIDLE I K3 Active High. Forces TX output to electrical idle depending on the power state.
S, I/O, Active High. While de-asserted with the PHY in P0, P1, P2, or P3, indicates detection of
RX_ELECIDLE F3
PD LFPS.
Encodes receiver status and error codes for the received data stream when receiving
RX_STATUS2 C7 data.
O
RX_STATUS1 C6 BIT 2 BIT 1 BIT 0 DESCRIPTION
RX_STATUS0 C5 0 0 0 Received data OK
0 0 1 1 SKP ordered set added
0 1 0 1 SKP ordered set removed
0 1 1 Receiver detected
1 0 0 8B/10B decode error
1 0 1 Elastic buffer overflow
Elastic buffer underflow.
1 1 0 This error code is not used if the elasticity buffer is
operating in the nominal buffer empty mode.
1 1 1 Receive disparity error
POWER_DOWN1 G3 Power up and down the transceiver power states.
I
POWER_DOWN0 H3 BIT 1 BIT 0 DESCRIPTION
0 0 P0, normal operation
0 1 P1, low recovery time latency, power saving state
1 0 P2, longer recovery time latency, low power state
1 1 P3, lowest power state
When transitioning from P3 to P0, the signaling is asynchronous.
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PIPE Signal Description (continued)
SIGNAL NAME TYPE BALL NO. DESCRIPTION
Active High. Used to communicate completion of several PHY func-tions including power
S, I/O, management state transitions, rate change, and receiver detection. When this signal
PHY_STATUS E3
PD transitions during entry and exit from P3 and PCLK is not running, then the signaling is
asynchronous.
PWRPRESENT O H11 Indicates the presence of VBUS
CONFIGURATION PINS
Active High. Used only when transmitting USB compliance pat-terns CP7 or CP8. Causes
TX_ONESZEROS I, PD M4 the transmitter to transmit an alternating sequence of 50 - 250 ones and 50 - 250 zeros –
regardless of the state of the TX_DATA interface.
Selects transmitter de-emphasis. When the MAC changes, the TUSB1310 starts to
TX_DEEMPH1 K11 transmit with the new setting within 128 ns.
I, PD, PU
TX_DEEMPH0 L11 BIT 1 BIT 0 DESCRIPTION
0 0 -6 dB de-emphasis
0 1 -3.5 dB de-emphasis
1 0 No de-emphasis
1 1 Reserved
TX_MARGIN2 M11 Selects transmitter voltage levels
TX_MARGIN1 M10 BIT 2 BIT 1 BIT 0 TX_SWING DESCRIPTION
I, PD Normal operating range
TX_MARGIN0 M9 0 0 0 0 800 mV - 1200 mV
Normal operating range
0 0 0 1 400 mV - 700 mV
0 800 mV - 1200 mV
001 1 400 mV - 700 mV
0 700 mV - 900 mV
010 1 300 mV - 500 mV
0 400 mV - 600 mV
011 1 200 mV - 400 mV
1 0 200 mV - 400 mV
Don't care
1 1 100 mV - 200 mV
Controls transmitter voltage swing level
TX_SWING I, PD M5 0 Full swing
1 Half swing
Active High. Tells PHY to do a polarity inversion on the received data. Inverted data show
up on RX_DATA15-0 within 20 PCLK clocks after RX_POLARITY is asserted.
RX_POLARITY I, PD C8 0 PHY does no polarity inversion.
1 PHY does polarity inversion.
Controls presence of receiver terminations
RX_TERMINATION I, PD D3 0 Terminations removed
1 Terminations present
Controls the link signaling rate
RATE I, PU L6 The RATE is always 1.
Selects elasticity buffer operating mode
ELAS_BUF_MODE I, PD C9 0 Nominal half full buffer mode
1 Nominal empty buffer mode
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2.3 ULPI
The ULPI (ultra low pin count interface) is a low pin count USB PHY to a link layer controller interface. The
ULPI consists of the interface and the ULPI registers. The TUSB1310 is always the master of the ULPI
bus.
Table 2-3. ULPI Signal Description
SIGNAL NAME TYPE BALL NO. DESCRIPTION
60-MHz interface clock. All ULPI signals are synchronous to ULPI_CLK. The ULPI_CLK is
ULPI_CLK O P11 always a 60-MHz output of the TUSB1310. In low power mode, the ULPI_CLK is not driven.
ULPI_DATA7 N6
ULPI_DATA6 P6
ULPI_DATA5 N7
ULPI_DATA4 P7 Data bus. Driven to 00h by the Link when the ULPI bus is idle.
S, I/O, PD 8-bit data timed on rising edge of ULPI_CLK
ULPI_DATA3 N8
ULPI_DATA2 P8
ULPI_DATA1 P9
ULPI_DATA0 N9 Controls the direction of the ULPI_DATA bus
ULPI_DIR O M7 0 ULPI_DATA lines are inputs
1 ULPI_DATA lines are outputs
Active High. The Link must assert ULPI_STP to signal the end of a USB transmit packet or a
register write operation. The ULPI_STP signal must be asserted in the cycle after the last data
ULPI_STP S, I, PU M8 byte is presented on the bus. The ULPI_STP has an internal weak pull-up to safeguard
against false commands on the ULPI_DATA lines.
Active High. The PHY asserts ULPI_NXT to throttle all data types, except register read data
and the RX CMD. The PHY also asserts ULPI_NXT and ULPI_DIR simultaneously to indicate
ULPI_NXT O N11 USB receive activity, if ULPI_DIR was previously low. The PHY is not allowed to assert
ULPI_NXT during the first cycle of the TX CMD driven by the Link.
2.3.1 ULPI Modes
The TUSB1310 supports synchronous mode and low power mode. The default mode is synchronous
mode.
The synchronous mode is a normal operation mode. The ULPI_DATA are synchronous to ULPI_CLK. The
low power mode is used during power down and no ULPI_CLK. The TUSB1310 sets ULPI_DIR to output
and drives LineState signals and interrupts.
Table 2-4. ULPI Synchronous and Low Power Mode Functions
SYNCHRONOUS LOW POWER
ULPI_CLK(OUT)
ULPI_DATA7(I/O)
ULPI_DATA6(I/O)
ULPI_DATA5(I/O)
ULPI_DATA4{I/O}
ULPI_DATA3(I/O) ULPI_INT (OUT)
ULPI_DATA2(I/O)
ULPI_DATA1(I/O) ULPI_LINESTATE1(OUT)
ULPI_DATA0(I/O) ULPI_LINE_STATE0 (OUT)
ULPI_DIR(OUT)
ULPI_STP(IN)
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ULPI Synchronous and Low Power Mode Functions (continued)
SYNCHRONOUS LOW POWER
ULPI_NXT(OUT)
2.4 Clocking
Table 2-5. Clock Signal Name Description
SIGNAL NAME TYPE BALL NO. DESCRIPTION
Crystal Input. This pin is the clock reference input for the TUSB1310. The TUSB1310
XI I A12 supports either a crystal unit, or a 1.8-V clock input. Frequencies supported are 20, 25,
30, or 40 MHz.
XO O A11 Crystal output. If a 1.8-V clock input is connected to XI, XO must be left open.
CLKOUT O D10 OOBCLK is driven in U3 mode.
2.5 JTAG Interface
The JTAG Interface is used for board-level boundary scan. All digital IO support IEEE1149.1 boundary
scan and SuperSpeed differential pairs support IEEE1149.6 boundary scan.
Table 2-6. JTAG Signal Name Description
SIGNAL NAME TYPE BALL NO. DESCRIPTION
JTAG_TCK I, PU G11 JTAG test clock
JTAG_TMS I, PU D11 JTAG test mode select
JTAG_TDI I, PU E11 JTAG test data input
JTAG_TRSTN I, PD E12 JTAG test asynchronous reset. Active Low.
JTAG_TDO O F11 JTAG test data output
2.6 Reset and Output Control Interface
Table 2-7. Reset and Output Control Signal Description
SIGNAL NAME TYPE BALL NO. DESCRIPTION
RESETN I J11 Active Low. Resets the transmitter and receiver. This signal is asynchronous.
Active High. This can be connected to a 1.8-V power on reset signal on the PCB in
order to avoid static current and signal contention during power up.
OUT_ENABLE I L10 0: Disable all driver outputs while IO powers are supplied, but internal control circuit
powers are not present during power up.
1: Enable all driver outputs during normal operation.
2.7 Strap Options
Strapping pins are latched by reset de-assertion in the TUSB1310.
Table 2-8. Strapping Options
SIGNAL NAME TYPE BALL NO. DESCRIPTION
Selects an input clock source
XTAL_DIS S, I/O, PD F3 0 Crystal Input
(RX_ELECIDLE) 1 Clock Input
Selects PIPE
PIPE_16BIT S, I/O, PD E3 0 16-bit PIPE SDR mode
(PHY_STATUS) Must be 0 at reset.
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Strapping Options (continued)
SIGNAL NAME TYPE BALL NO. DESCRIPTION
Active High. Puts PIPE into isolate mode. When in the isolate mode, TUSB1310 does
not respond to packet data present at TX_DATA15-0, TXDATAK1-0 inputs and presents
a high imped-ance on the PCLK, RX_DATA15-0, RX_DATAK1-0, RX_VALID outputs.
ISO_START S, I/O, PD N6 When in the isolate mode, the TUSB1310 will continue to respond to ULPI. Once the
(ULPI_DATA7) isolate mode bit in ULPI register is cleared, the USB interfaces will start transmitting
packet data on TX_DATA15-0 and driving PCLK, RX_DATA15-0, RX_DATA1-0, and
RX_VALID.
Selects ULPI data bus bit width
ULPI_8BIT S, I/O, PD P6 0 8-bit ULPI SDR mode
(ULPI_DATA6) Must be set to 0.
Select input reference clock frequency for on-chip oscillator
REFCLKSEL1, 00 20 MHz on XI
REFCLKSEL0 N7
S, I/O, PD 01 25 MHz on XI
(ULPI_DATA5, P7 10 30 MHz on XI
ULPI_DATA4) 11 40 MHz on XI
2.8 USB Interfaces
Table 2-9. USB Interface Signal Name Descriptions
SIGNAL NAME TYPE BALL NO. DESCRIPTION
SSTXP H14
O USB SuperSpeed transmitter differential pair
SSTXM J14
SSRXP E14
I USB SuperSpeed receiver differential pair
SSRXM F14
DP P14
I/O USB non-SuperSpeed differential pair
DM P13 USB VBUS pin
VBUS I N12 Connected through an external voltage divider.
2.9 Special Connect
Table 2-10. Special Connect Signal Descriptions
SIGNAL NAME TYPE BALL NO. DESCRIPTION
High precision external resistor used for calibration. The R1 value shall be 10 kΩ±1%
R1EXT O L14 accuracy.
R1EXTRTN I L13 R1 ground reference. This pin is not connected to board ground.
CEXT O M14 Connected to an external 4.7-nF capacitor
CEXTSS O A14 Connected to an external 4.7-nF capacitor
D6
D5
C13
RSVD I/O Must be left open.
C14
K4
J4
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2.10 Power and Ground
Table 2-11. Power/Ground Signal Descriptions
SIGNAL NAME TYPE BALL NO. DESCRIPTION
VDDA3P3 P P12 Analog 3.3-V power supply
N14
VDDA1P8 P A13 Analog 1.8-V power supply
C10
C12
K14
G13
VDDA1P1 P Analog 1.1-V power supply
G14
D14
C11
B2 C3
D4 D7
D8 D9
E4 F4
VDD1P8 P Digital IO 1.8-V power supply
G4 H4
L5 L4
M3 L7
L8 L9
A5 A10
B6 B10
E1 F2
K2 L1
VDD1P1 P Digital 1.1-V power supply
N5 P4
N10 P10
K13 D13
C4
B14 B13
J13 H13
F13 E13
K12 L12
VSSA G G12 Analog ground
D12
N13
M12
M13 Oscillator ground
If using a crystal, this should not be connected to PCB ground polane.
VSSOSC G B12 See Chapter 5 for guidelines.
If using an oscillator, this should be connected to PCB ground.
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Power/Ground Signal Descriptions (continued)
SIGNAL NAME TYPE BALL NO. DESCRIPTION
F6 F7
F8 F9
G6 G7
G8 G9
VSS G J6 J7 Digital ground
H6 H7
H8 H9
J8 J9
B11 F12
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TUSB1310IZAYR PREVIEW NFBGA ZAY 175 1000 TBD Call TI Call TI
TUSB1310ZAY PREVIEW NFBGA ZAY 175 160 TBD Call TI Call TI
TUSB1310ZAYR PREVIEW NFBGA ZAY 175 1000 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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