VNI2140JTR - STMicroelectronics, Inc.

November 2011 Doc ID 15187 Rev 8 1/23

VNI2140J

Dual high side smart power solid state relay

Features

■Nominal current: 0.5 A per channel

■Shorted load protections

■Junction overtemperature protection

■Case overtemperature protection for thermal

independence of the channels

■Thermal case shutdown restart not

simultaneous for the various channels

■Protection against loss of ground

■Current limitation 1 A per channel

■Undervoltage shutdown

■Open load in off-state and short to VCC

detection

■Open-drain diagnostic outputs

■3.3 V CMOS/TTL compatible inputs

■Fast demagnetization of inductive loads

■Conforms to IEC 61131-2

Description

The VNI2140J is a monolithic device designed

using STMicroelectronics' VIPower technology.

The device drives two independent resistive or

inductive loads with one side connected to

ground. Active current limitation prevents a drop

in system power supply in cases of shorted-load,

and built-in thermal shutdown protects the chip

from damage due to over-temperature and short-

circuit. In overload conditions, channel turns OFF

and ON automatically to maintain the junction

temperature between TTSD and TR. If the case

temperature reaches TCSD, the overloaded

channel is turned OFF and restarts only when

case temperature decreases down to TCR. In

order to avoid high-peak current from the supply,

when more than one channel is overloaded the

TCSD restart is not simultaneous. Non

overloaded channels continue to operate

normally. The open-drain diagnostics output

indicates over-temperature conditions and open-

load in off state.

Type Vdemag(1)

1. Per channel

RDSon(1) Iout(1) VCC

VNI2140J VCC-45 V 0.08 Ω1 A (2)

2. Current limitation

45 V

PowerSSO-12

Table 1. Device summary

Order codes Package Packaging

VNI2140J PowerSSO-12 Tube

VNI2140JTR Tape and reel

www.st.com

         
Contents VNI2140J
2/23  Doc ID 15187 Rev 8
Contents
Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1 Thermal data   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
Electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Truth table   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching waveforms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Open load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package and PCB thermal data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reverse polarity protection   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package mechanical data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

VNI2140J Block diagram

Doc ID 15187 Rev 8 3/23

1 Block diagram

Figure 1. Block diagram

Pin connections VNI2140J

4/23 Doc ID 15187 Rev 8

2 Pin connections

Figure 2. Pin connections (top view)

Table 2. Pin description

n° Name Description

1 NC Not connected

2 Input 1 Channel 1 input 3.3 V CMOS/TTL compatible

3 Diag 1 Channel 1 diagnostic in open-drain configuration

4 GND Device ground connection

5 Diag 2 Channel 2 diagnostic in open-drain configuration

6 Input 2 Channel 2 input 3.3 V CMOS/TTL compatible

7 VCC Supply voltage

8 Output 2 Channel 2 power stage output, internally protected

9 Output 2 Channel 2 power stage output, internally protected

10 Output 1 Channel 1 power stage output, internally protected

11 Output 1 Channel 1 power stage output, internally protected

12 VCC Supply voltage

TAB TAB Supply voltage

VCC

Output 1

Output 2

VCC

Input 1

Diag 1

GND

Diag 2

Input 2

VNI2140J Maximum ratings

Doc ID 15187 Rev 8 5/23

3 Maximum ratings

3.1 Thermal data

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC Power supply voltage 45 V

-VCC Reverse supply voltage -0.3 V

IGND DC ground reverse current -250 mA

IOUT Output current (continuous) Internally limited A

IRReverse output current (per channel) -5 A

IIN Input current (per channel) ± 10 mA

VIN Input voltage +VCC V

VDIAG Diag pin voltage +VCC V

IDIAG Diag pin current ± 10 mA

VESD Electrostatic discharge (R = 1.5 kΩ; C = 100 pF) 2000 V

EAS

Single pulse avalanche energy per channel not

simultaneously 300 mJ

PTOT Power dissipation at Tc = 25 °C Internally limited W

TJJunction operating temperature Internally limited °C

TSTG Storage temperature -55 to 150 °C

Table 4. Thermal data

Symbol Parameter Value Unit

Rth(JC) Thermal resistance junction-case (1)

1. Per channel

Max 1 °C/W

Rth(JA) Thermal resistance junction-ambient (2)

2. When mounted using minimum recommended pad size on FR-4 board

Max See Figure 11 on

page 15 °C/W

Electrical characteristics VNI2140J

6/23 Doc ID 15187 Rev 8

4 Electrical characteristics

9 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified

VCC = 24

Table 5. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

Vcc Supply voltage 9 45 V

RDS(ON) On-state resistance IOUT = 0.5 A at TJ = 25 °C

IOUT = 0.5 A

0.080

0.150

VCLAMP Clamp voltage Is = 20 mA 45 52 V

ISSupply current

All channel in off-state

On-state with VIN =5 V

(TJ = 125 °C)

300

1.9 4

µA

ILGND

Output current at

turn-off

VCC = VDIAG = VIN =

VGND = 24 V, VOUT = 0 V 1mA

VOUT(OFF)

Off-state output

voltage VIN = 0 V and IOUT = 0 A 3 V

IOUT(OFF) OFF-state output

current

VIN = VOUT = 0 V 0 5 µA

IOUT(OFF1) VIN = 0 V; VOUT = 4 V -35 0 µA

Table 6. Switching

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(ON)

Turn-on delay time of

output current

IOUT = 0.5 A, resistive load

Input rise time < 0.1 μs,

TJ = 25 °C

-20 -µs

Rise time of output

current

IOUT = 0.5 A, resistive load

Input rise time < 0.1 μs,

TJ = 25 °C

-10 -µs

td(OFF)

Turn-off delay time of

output current

IOUT = 0.5 A, resistive load

Input rise time < 0.1 μs,

TJ = 25 °C

-30 -µs

Fall time of output

current

IOUT = 0.5 A, resistive load

Input rise time < 0.1 μs,

TJ = 25 °C

-8 -µs

tDOL

Delay time for open

load detection - 500 - µs

dV/dt(ON) Turn ON voltage slope - 3 - V/µS

dV/dt(off) Turn OFF voltage

slope -4 -V/µS

VNI2140J Electrical characteristics

Doc ID 15187 Rev 8 7/23

Table 7. Logical input

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low level voltage 0.8 V

VIH Input high level voltage 2.20 V

VI(HYST)

Input hysteresis

voltage 0.15 V

IIN Input current VIN = 15 V 10 μA

VIN = 36 V 210

Table 8. Protection and diagnostic

Symbol Parameter Test conditions Min. Typ. Max. Unit

VDIAG (1)

1. Diag determination > 100 ms after the switching edge.

Diag voltage output

low IDIAG = 1.5 mA (fault condition) 0.6 V

VUSD

Undervoltage

protection 79V

VUSDHYS

Undervoltage

hysteresis 0.4 0.5 V

ILIM

DC short circuit

current VCC = 24 V; RLOAD < 10 mΩ12A

ILDIAG Diag leakage current VCC = 32 V 30 μA

VOL

Open-load off-state

voltage detection

threshold

VIN = 0 V 2 3 4 V

TTSD

Junction shutdown

temperature 150 170 °C

Junction reset

temperature 135 155 200 °C

THIST

Junction thermal

hysteresis 715 °C

TCSD

Case shutdown

temperature 125 130 135 °C

TCR

Case reset

temperature 110 °C

TCHYST

Case thermal

hysteresis 715 °C

Vdemag

Output voltage at

turn-OFF IOUT = 0.5 A; LLOAD >= 1 mH VCC-

VCC-

52 V

Electrical characteristics VNI2140J

8/23 Doc ID 15187 Rev 8

Figure 3. Current and voltage conventions

VNI2140J Truth table

Doc ID 15187 Rev 8 9/23

5 Truth table

Table 9. Truth table

INPUTn OUTPUTn DIAGn

Normal operation L

Overtemperature L

Undervoltage L

Shorted load

(Current limitation)

Output voltage > VOL

Z (1)

1. Z = Depending on the external circuit

Short to VCC

Switching waveforms VNI2140J

10/23 Doc ID 15187 Rev 8

6 Switching waveforms

Figure 4. Switching waveforms

VNI2140J Switching waveforms

Doc ID 15187 Rev 8 11/23

Figure 5. Switching waveforms (continued)

Figure 6. Switching parameter test conditions

IOUT

VIN

Switching waveforms VNI2140J

12/23 Doc ID 15187 Rev 8

Figure 7. Typical application circuit

VNI2140J Open load

Doc ID 15187 Rev 8 13/23

7 Open load

In order to detect the open load fault a pull-up resistor must be connected between the VCC

line and the output pin.

In a normal condition a current flows through the network made up of a pull-up resistor and

a load. The voltage across the load is less than VOLMIN; so the diag pin is kept high.

This is the result in the condition:

Equation 1

Equation 2

When a open load event occurs the voltage on the output pin rises to a value higher than

VOLMAX (depending on the pull-up resistor). The diag pin will go down.

This result in the condition:

Equation 3

Figure 8. Open load detection

VCC

RLOAD

RLOAD RPU

------------------------------------VOLMIN

VCC

VOLMIN

--------------------1–

⎝⎠

⎛⎞

RLOAD

⋅RPU

RPU

VCC VOLMAX

–

IOUT OFF1()MIN

------------------------------------------

Open load VNI2140J

14/23 Doc ID 15187 Rev 8

Figure 9. Turn on/off to open load

VNI2140J Package and PCB thermal data

Doc ID 15187 Rev 8 15/23

8 Package and PCB thermal data

Figure 10. PowerSSO-12 PC board

Figure 11. RthJA vs PCB copper area in open box free air condition

Figure 12. PowerSSO-12 thermal Impedance junction ambient single pulse

Package and PCB thermal data VNI2140J

16/23 Doc ID 15187 Rev 8

Pulse calculation formula

Equation 4

ZTHδ = RTH x δ + ZTHtp (1 – δ)

where δ = tP/T

Figure 13. Thermal fitting model of a double channel HSD in PowerSSO-12

Table 10. Thermal parameter

Area/island (cm2) Footprint 2 8

R1 (°C/W) 0.1

R2 (°C/W) 0.2

R3 (°C/W) 7

R4 (°C/W) 10 10 9

R5 (°C/W) 22 15 10

R6 (°C/W) 26 20 15

C1 (W.s/°C) 0.0001

C2 (W.s/°C) 0.002

C3 (W.s/°C) 0.05

C4 (W.s/°C) 0.2 0.1 0.1

C5 (W.s/°C) 0.27 0.8 1

C6 (W.s/°C) 3 6 9

VNI2140J Reverse polarity protection

Doc ID 15187 Rev 8 17/23

9 Reverse polarity protection

This schematic can be used with any type of load.

The following is an indication on how to dimension the RGND resistor.

RGND = (-VCC) / (-IGND)

where -IGND is the DC reverse ground pin current and can be found in the absolute

maximum rating section of the device datasheet.

Power dissipation in RGND (when VCC < 0: during reverse polarity situations) is:

PD = (-VCC)2/RGND

Note: In normal condition (no reverse polarity) due to the diode there will be a voltage drop

between GND of the device and GND of the system.

Figure 14. Reverse polarity protection

Diagi

Inputi

GND

Outputi

+ Vcc

RGND

Load

Diode

Diagi

Inputi

GND

Outputi

+ Vcc

RGND

Load

Diode

Package mechanical data VNI2140J

18/23 Doc ID 15187 Rev 8

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

VNI2140J Package mechanical data

Doc ID 15187 Rev 8 19/23

Figure 15. PowerSSO-12™ package dimensions

Table 11. PowerSSO-12™ mechanical data

Symbol

Min. Typ. Max.

A 1.250 1.620

A1 0.000 0.100

A2 1.100 1.650

B 0.230 0.410

C 0.190 0.250

D 4.800 5.000

E 3.800 4.000

e 0.800

H 5.800 6.200

h 0.250 0.500

L 0.400 1.270

k 0° 8°

X 1.900 2.500

Y 3.600 4.200

ddd 0.100

Package mechanical data VNI2140J

20/23 Doc ID 15187 Rev 8

Figure 16. PowerSSO-12™ tube shipment (no suffix)

Figure 17. PowerSSO-12™ tape and reel shipment (suffix “TR”)

VNI2140J Package mechanical data

Doc ID 15187 Rev 8 21/23

Figure 18. Suggested footprint

Revision history VNI2140J

22/23 Doc ID 15187 Rev 8

11 Revision history

Table 12. Document revision history

Date Revision Changes

16-Dec-2008 1 Initial release

29-Apr-2009 2 Updated Table 5 on page 6

03-Jul-2009 3 Updated features in coverpage and Table 5 on page 6

27-Aug-2009 4 Updated Section 9: Reverse polarity protection

25-Mar-2010 5 Updated Coverpage and Table4 on page5

26-Apr-2010 6 Updated Table 5 on page 6

21-Jul-2010 7 Updated Table 8 on page 7

15-Nov-2011 8 Updated Figure 18 on page 21

VNI2140J

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