2003 Microchip Technology Inc. DS21117A-page 1
MMCP6S21/2/6/8
Features
• Multiplexed Inputs: 1, 2, 6 or 8 channels
• 8 Gain Selections:
- +1, +2, +4, +5, +8, +10, +16 or +32 V/V
• Serial Peripheral Interface (SPI™)
• Rail-to-Rail Input and Output
• Low Gain Error: ±1% (max)
• Low Offset: ±275 µV (max)
• High Bandwidth: 2 to 12 MHz (typ)
• Low Noise: 10 nV/√Hz @ 10 kHz (typ)
• Low Supply Current: 1.0 mA (typ)
• Single Supply: 2.5V to 5.5V
Typical Applications
• A/D Converter Driver
• Multiplexed Analog Applications
• Data Acquisition
• Industrial Instrumentation
• Test Equipment
• Medical Instrumentation
Package Types
Description
The Microchip Technology Inc. MCP6S21/2/6/8 are
analog Programmable Gain Amplifiers (PGA). They
can be configured for gains from +1 V/V to +32 V/V and
the input multiplexer can select one of up to eight chan-
nels through an SPI port. The serial interface can also
put the PGA into shutdown to conserve power. These
PGAs are optimized for high speed, low offset voltage
and single-supply operation with rail-to-rail input and
output capability. These specifications support single
supply applications needing flexible performance or
multiple inputs.
The one channel MCP6S21 and the two channel
MCP6S22 are available in 8-pin PDIP, SOIC and
MSOP packages. The six channel MCP6S26 is avail-
able in 14-pin PDIP, SOIC and TSSOP packages. The
eight channel MCP6S28 is available in 16-pin PDIP
and SOIC packages. All parts are fully specified from
-40°C to +85°C.
Block Diagram
VREF
CH0
VSS
SI
SCK
1
2
3
4
8
7
6
5
VDD
CS
VOUT
CH1
CH0
CH2
CS
SI
1
2
3
4
14
13
12
11
VREF
VSS
VOUT
5
6
7
10
9
8
CH3
SCK
VDD
CH5
CH4
CH0
VOUT
CH1
VSS
CS
1
2
3
4
16
15
14
13 SI
SCK
5
6
7
12
11
10
CH2
CH4
CH7
VDD
CH5
89
SO
CH6
CH3
SO
CH1
CH0
VSS
SI
SCK
1
2
3
4
8
7
6
5
VDD
CS
VOUT
MCP6S21
PDIP, SOIC, MSOP
MCP6S26
PDIP, SOIC, TSSOP
MCP6S28
PDIP, SOIC
MCP6S22
PDIP, SOIC, MSOP
VREF
VOUT
VREF
VDD
CS
SI
SO
SCK
CH1
CH0
CH3
CH2
CH5
CH4
CH7
CH6
VSS
8
RF
RG
MUX
SPI™
Logic
POR
Gain
Switches
+
-
Resistor Ladder (RLAD)
Single-Ended, Rail-to-Rail I/O, Low Gain PGA
MCP6S21/2/6/8
DS21117A-page 2 2003 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
All inputs and outputs....................... VSS - 0.3V to VDD +0.3V
Difference Input voltage ........................................ |VDD - VSS|
Output Short Circuit Current...................................continuous
Current at Input Pin .............................................................±2mA
Current at Output and Supply Pins ................................ ±30 mA
Storage temperature .....................................-65°C to +150°C
Junction temperature ..................................................+150°C
ESD protection on all pins (HBM;MM).................. ≥ 2 kV; 200V
† Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
PIN FUNCTION TABLE
Name Function
VOUT Analog Output
CH0-CH7 Analog Inputs
VSS Negative Power Supply
VDD Positive Power Supply
SCK SPI Clock Input
SI SPI Serial Data Input
SO SPI Serial Data Output
CS SPI Chip Select
VREF External Reference Pin
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL=10kΩ to VDD/2, SI and SCK are tied low and CS is tied high.
Parameters Sym Min Typ Max Units Conditions
Amplifier Input
Input Offset Voltage VOS -275 — +275 µV G = +1, VDD = 4.0V
Input Offset Voltage Drift ∆VOS/∆TA—±4 —µV/°CT
A = -40 to +85°C
Power Supply Rejection Ratio PSRR 70 85 — dB G = +1 (Note 1)
Input Bias Current IB— ±1 — pA CHx = VDD/2
Input Bias Current over
Temperature
IB— — 250 pA TA = -40 to +85°C,
CHx = VDD/2
Input Impedance ZIN —10
13||15 — Ω||pF
Input Voltage Range VIVR VSS−0.3 — VDD+0.3 V
Amplifier Gain
Nominal Gains G — 1 to 32 — V/V +1, +2, +4, +5, +8, +10, +16 or +32
DC Gain Error G = +1 gE-0.1 — +0.1 % VOUT ≈ 0.3V to VDD − 0.3V
G ≥ +2 gE-1.0 — +1.0 % VOUT ≈ 0.3V to VDD − 0.3V
DC Gain Drift G = +1 ∆G/∆TA— ±0.0002 — %/°C TA = -40 to +85°C
G ≥ +2 ∆G/∆TA— ±0.0004 — %/°C TA = -40 to +85°C
Internal Resistance RLAD 3.4 4.9 6.4 kΩ(Note 1)
Internal Resistance over
Temperature
∆RLAD/∆TA—+0.028 — %/°C(Note 1)
TA = -40 to +85°C
Amplifier Output
DC Output Non-linearity G = +1 VONL — ±0.003 — % of FSR VOUT = 0.3V to VDD − 0.3V, VDD = 5.0V
G ≥ +2 VONL — ±0.001 — % of FSR VOUT = 0.3V to VDD − 0.3V, VDD = 5.0V
Maximum Output Voltage Swing VOH, VOL VSS+20 — VDD-100 mV G ≥ +2; 0.5V output overdrive
VSS+60 — VDD-60 G ≥ +2; 0.5V output overdrive,
VREF = VDD/2
Short-Circuit Current IO(SC) —±30 — mA
Note 1: RLAD (RF + RG in Figure 4-1) connects VREF
, VOUT and the inverting input of the internal amplifier. The MCP6S22 has
VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We
recommend the MCP6S22’s VSS pin be tied directly to ground to avoid noise problems.
2: IQ includes current in RLAD (typically 60 µA at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents.
3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.
2003 Microchip Technology Inc. DS21117A-page 3
MCP6S21/2/6/8
Power Supply
Supply Voltage VDD 2.5 — 5.5 V
Quiescent Current IQ0.5 1.0 1.35 mA IO = 0 (Note 2)
Quiescent Current, Shutdown
mode
IQ_SHDN —0.5 1.0 µAI
O = 0 (Note 2)
Power-On Reset
POR Trip Voltage VPOR 1.2 1.7 2.2 V (Note 3)
POR Trip Voltage Drift ∆VPOR/∆T— -3.0 — mV/°CT
A = -40°C to+85°C
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL=10kΩ to VDD/2, SI and SCK are tied low and CS is tied high.
Parameters Sym Min Typ Max Units Conditions
Note 1: RLAD (RF + RG in Figure 4-1) connects VREF
, VOUT and the inverting input of the internal amplifier. The MCP6S22 has
VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We
recommend the MCP6S22’s VSS pin be tied directly to ground to avoid noise problems.
2: IQ includes current in RLAD (typically 60 µA at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents.
3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 =(0.3V)/G, CH1 to CH7=0.3V, RL=10kΩ to VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters Sym Min Typ Max Units Conditions
Frequency Response
-3 dB Bandwidth BW — 2 to 12 — MHz All gains; VOUT < 100 mVP-P (Note 1)
Gain Peaking GPK — 0 — dB All gains; VOUT < 100 mVP-P
Total Harmonic Distortion plus Noise
f = 1 kHz, G = +1 V/V THD+N — 0.0015 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 22 kHz
f = 1 kHz, G = +4 V/V THD+N — 0.0058 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 22 kHz
f = 1 kHz, G = +16 V/V THD+N — 0.023 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 22 kHz
f = 20 kHz, G = +1 V/V THD+N — 0.0035 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 80 kHz
f = 20 kHz, G = +4 V/V THD+N — 0.0093 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 80 kHz
f = 20 kHz, G = +16 V/V THD+N — 0.036 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V,
BW = 80 kHz
Step Response
Slew Rate SR — 4.0 — V/µs G = 1, 2
— 11 — V/µs G = 4, 5, 8, 10
—22—V/µsG = 16, 32
Noise
Input Noise Voltage Eni —3.2—µV
P-P f = 0.1 Hz to 10 kHz (Note 2)
— 26 — f = 0.1 Hz to 200 kHz (Note 2)
Input Noise Voltage Density eni —10—nV/√Hz f = 10 kHz (Note 2)
Input Noise Current Density ini —4—fA/√Hz f = 10 kHz
Note 1: See Table 4-1 for a list of typical numbers.
2: Eni and eni include ladder resistance noise. See Figure 2-33 for eni vs. G data.
MCP6S21/2/6/8
DS21117A-page 4 2003 Microchip Technology Inc.
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL=10kΩ to VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters Sym Min Typ Max Units Conditions
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low VIL 0 — 0.3VDD V
Input Leakage Current IIL -1.0 — +1.0 µA
Logic Threshold, High VIH 0.7VDD —V
DD V
Amplifier Output Leakage Current — -1.0 — +1.0 µA In Shutdown mode
SPI Output (SO, for MCP6S26 and MCP6S28)
Logic Threshold, Low VOL VSS —V
SS+0.4 V IOL = 2.1 mA, VDD = 5V
Logic Threshold, High VOH VDD-0.5 — VDD VI
OH = -400 µA
SPI Timing
Pin Capacitance CPIN — 10 — pF All digital I/O pins
Input Rise/Fall Times (CS, SI, SCK) tRFI ——2µsNote 1
Output Rise/Fall Times (SO) tRFO — 5 — ns MCP6S26 and MCP6S28
CS high time tCSH 40 — — ns
SCK edge to CS fall setup time tCS0 10 — — ns SCK edge when CS is high
CS fall to first SCK edge setup time tCSSC 40 — — ns
SCK Frequency fSCK ——10MHzV
DD = 5V (Note 2)
SCK high time tHI 40 — — ns
SCK low time tLO 40 — — ns
SCK last edge to CS rise setup time tSCCS 30 — — ns
CS rise to SCK edge setup time tCS1 100 — — ns SCK edge when CS is high
SI set-up time tSU 40 — — ns
SI hold time tHD 10 — — ns
SCK to SO valid propagation delay tDO — — 80 ns MCP6S26 and MCP6S28
CS rise to SO forced to zero tSOZ — — 80 ns MCP6S26 and MCP6S28
Channel and Gain Select Timing
Channel Select Time tCH — 1.5 — µs CHx = 0.6V, CHy =0.3V, G = 1,
CHx to CHy select
CS = 0.7VDD to VOUT 90% point
Gain Select Time tG— 1 — µs CHx = 0.3V, G = 5 to G = 1 select,
CS = 0.7VDD to VOUT 90% point
Shutdown Mode Timing
Out of Shutdown mode (CS goes
high) to Amplifier Output Turn-on
Time
tON —3.510µs
CS = 0.7VDD to VOUT 90% point
Into Shutdown mode (CS goes high)
to Amplifier Output High-Z Turn-off
Time
tOFF —1.5—µs
CS = 0.7VDD to VOUT 90% point
POR Timing
Power-On Reset power-up time tRPU —30—µsV
DD = VPOR - 0.1V to VPOR + 0.1V,
50% VDD to 90% VOUT point
Power-On Reset power-down time tRPD —10—µsV
DD = VPOR + 0.1V to VPOR - 0.1V,
50% VDD to 90% VOUT point
Note 1: Not tested in production. Set by design and characterization.
2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (tDO ≤ 80 ns), data input setup time (tSU ≥ 40 ns), SCK high time (tHI ≥ 40 ns), and SCK rise and
fall times of 5 ns. Maximum fSCK is, therefore, ≈ 5.8 MHz.
2003 Microchip Technology Inc. DS21117A-page 5
MCP6S21/2/6/8
TEMPERATURE CHARACTERISTICS
FIGURE 1-1: Channel Select Timing
Diagram.
FIGURE 1-2: PGA Shutdown timing
diagram (must enter correct commands before
CS goes high).
FIGURE 1-3: Gain Select Timing
Diagram.
FIGURE 1-4: POR power-up and power-
down timing diagram.
Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +85 °C
Operating Temperature Range TA-40 — +125 °C (Note Note:)
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA —163—°C/W
Thermal Resistance, 8L-MSOP θJA —206—°C/W
Thermal Resistance, 14L-PDIP θJA —70—°C/W
Thermal Resistance, 14L-SOIC θJA —120—°C/W
Thermal Resistance, 14L-TSSOP θJA —100—°C/W
Thermal Resistance, 16L-PDIP θJA —70—°C/W
Thermal Resistance, 16L-SOIC θJA —90—°C/W
Note 1: The MCP6S21/2/6/8 family of PGAs operates over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature
(150°C).
CS
VOUT
tCH
0.6V
0.3V
CS
tOFF
VOUT
tON
Hi-Z Hi-Z
ISS
500 nA (typ)
1.0 mA (typ)
0.3V
CS
VOUT
tG
1.5V
0.3V
VDD
tRPD
VOUT
tRPU
Hi-Z Hi-Z
VPOR - 0.1V VPOR - 0.1V
VPOR + 0.1V
0.3V
ISS 500 nA (typ)
1.0 mA (typ)
MCP6S21/2/6/8
DS21117A-page 6 2003 Microchip Technology Inc.
FIGURE 1-5: Detailed SPI Serial Interface Timing, SPI 0,0 mode.
FIGURE 1-6: Detailed SPI Serial Interface Timing, SPI 1,1 mode.
CS
SCK
SI
tSU tHD
tCSSC tSCCS
tCSH
SO
(first 16 bits out are always zeros)
tDO tSOZ
tLO tHI
1/fSCK
tCS0
tCS1
CS
SCK
SI
tSU tHD
tCSSC tSCCS
SO
(first 16 bits out are always zeros)
tDO tSOZ
tHI tLO
1/fSCK
tCS1
tCSH
tCS0
2003 Microchip Technology Inc. DS21117A-page 7
MCP6S21/2/6/8
1.1 DC Output Voltage Specs / Model
1.1.1 IDEAL MODEL
The ideal PGA output voltage (VOUT) is:
EQUATION
(see Figure 1-7). This equation holds when there are
no gain or offset errors and when the VREF pin is tied to
a low impedance source (<< 0.1Ω) at ground potential
(VSS = 0V).
1.1.2 LINEAR MODEL
The PGA’s linear region of operation, including offset
and gain errors, is modeled by the line VO_linear, shown
in Figure 1-7.
EQUATION
The endpoints of this line are at VO_ideal =0.3V and
VDD-0.3V. The gain and offset specifications referred to
in the electrical specifications are related to Figure 1-7,
as follows:
EQUATION
FIGURE 1-7: Output Voltage Model with
the standard condition VREF = VSS = 0V.
1.1.3 OUTPUT NON-LINEARITY
Figure 1-8 shows the Integral Non-Linearity (INL) of the
output voltage.
EQUATION
The output non-linearity specification in the electrical
specifications is related to Figure 1-8 by:
EQUATION
FIGURE 1-8: Output Voltage INL with the
standard condition VREF = VSS = 0V.
VO_ideal GVIN
=VREF VSS 0V==
where: G is the nominal gain
VO_linear G1 g
E
+()VIN 0.3V VOS
+–()0.3V+=
VREF VSS 0V==
gE100% V2V1
–
GV
DD 0.6V–()
--------------------------------------=
VOS
V1
G1 g
E
+()
-------------------------
=
GT
A
∆⁄∆ gE
∆
TA
∆
----------
=
G+1=
0
0
0.3
VDD-0.3
VDD
VOUT
VOUT (V)
VIN (V)
0.3 VDD - 0.3 VDD
GGG
V1
VO_ideal
VO_linear
V2
INL VOUT VO_linear
–=
VONL
max V4V3
,{}
VDD 0.6V–
---------------------------------
=
0V3
V4
INL (V)
VIN (V)
0.3 VDD - 0.3 VDD
GGG
0
MCP6S21/2/6/8
DS21117A-page 8 2003 Microchip Technology Inc.
1.1.4 DIFFERENT VREF CONDITIONS
Some of the plots in Section 2.0, “Typical Performance
Curves”, have the conditions VREF =V
DD/2 or
VREF =V
DD. The equations and figures above are eas-
ily modified for these conditions. The ideal VOUT
becomes:
EQUATION
The complete linear model is:
EQUATION
where the new VIN endpoints are:
EQUATION
The equations for extracting the specifications do not
change.
VO_ideal VREF GV
IN VREF
–()+=
VDD VREF VSS
>0V=≥
VO_linear G1 g
E
+()VIN VIN_L VOS
+–()0.3V+=
VIN_L
0.3V VREF
–
GV
REF
+
------------------------------
=
VIN_R
VDD 0.3V–VREF
–
GV
REF
+
-----------------------------------------------
=
2003 Microchip Technology Inc. DS21117A-page 9
MCP6S21/2/6/8
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = GND, VREF =V
SS, G= +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL=10kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-1: DC Gain Error, G = +1.
FIGURE 2-2: DC Gain Error, G ≥+2.
FIGURE 2-3: Ladder Resistance Drift.
FIGURE 2-4: DC Gain Drift, G = +1.
FIGURE 2-5: DC Gain Drift, G ≥+2.
FIGURE 2-6: Input Offset Voltage,
VDD = 4.0V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
-0.040
-0.036
-0.032
-0.028
-0.024
-0.020
-0.016
-0.012
-0.008
-0.004
0.000
0.004
DC Gain Error (%)
Percentage of Occurrences
420 Samples
G = +1
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
DC Gain Error (%)
Percentage of Occurrences
420 Samples
G t +2
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
0.023
0.024
0.025
0.026
0.027
0.028
0.029
0.030
0.031
Ladder Resistance Drift (%/°C)
Percentage of Occurrences
420 Samples
TA = -40 to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-0.0006
-0.0005
-0.0004
-0.0003
-0.0002
-0.0001
0.0000
0.0001
0.0002
0.0003
0.0004
0.0005
0.0006
DC Gain Drift (%/°C)
Percentage of Occurrences
420 Samples
G = +1
TA = -40 to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
24%
-0.0020
-0.0016
-0.0012
-0.0008
-0.0004
0.0000
0.0004
0.0008
0.0012
0.0016
0.0020
DC Gain Drift (%/°C)
Percentage of Occurrences
420 Samples
G t +2
TA = -40 to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
-240
-200
-160
-120
-80
-40
0
40
80
120
160
200
240
Input Offset Voltage (µV)
Percentage of Occurrences
360 Samples
VDD = 4.0 V
G = +1
MCP6S21/2/6/8
DS21117A-page 10 2003 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = GND, VREF =V
SS, G= +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL=10kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-7: Input Offset Voltage vs.
VREF Voltage.
FIGURE 2-8: DC Output Non-Linearity vs.
Supply Voltage.
FIGURE 2-9: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-10: Input Offset Voltage Drift.
FIGURE 2-11: DC Output Non-Linearity vs.
Output Swing.
FIGURE 2-12: Input Noise Voltage Density
vs. Gain.
-200
-150
-100
-50
0
50
100
150
200
0.00.51.01.52.02.53.03.54.04.55.05.5
VREF Voltage (V)
Input Offset Voltage (µV)
VDD = +5.5
VDD = +2.5
G = +1
0.00001
0.0001
0.001
0.01
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
DC Output Non-Linearity,
Input Referred (% of FSR)
VONL/G, G = +1
VONL/G, G = +2
VONL/G, G t +4
VOUT = 0.3V to VDD -0.3V
1
10
100
1000
0.1 1 10 100 1000 10000 100000
Frequency (Hz)
Input Noise Voltage Density
(nV/Hz)
1k 10k 100k110 1000.1
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
420 Samples
TA = -40 to +125°C
G = +1
0.0001%
0.0010%
0.0100%
110
Output Voltage Swing (VP-P)
DC Output Non-Linearity,
Input Referred (%)
VONL/G, G t +2
VONL/G, G = +1
VDD = +5.5 V
0
1
2
3
4
5
6
7
8
9
10
11
12
12458101632
Gain (V/V)
Input Noise Voltage Density
(nV/Hz)
f = 10 kHz
2003 Microchip Technology Inc. DS21117A-page 11
MCP6S21/2/6/8
Note: Unless otherwise indicated, TA =+25°C, V
DD = +5.0V, VSS = GND, VREF =V
SS, G= +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL=10kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-13: PSRR vs. Ambient
Temperature.
FIGURE 2-14: Input Bias Current vs.
Ambient Temperature.
FIGURE 2-15: Bandwidth vs. Capacitive
Load.
FIGURE 2-16: PSRR vs. Frequency.
FIGURE 2-17: Input Bias Current vs. Input
Voltage.
FIGURE 2-18: Gain Peaking vs. Capacitive
Load.
70
80
90
100
110
120
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Power Supply Rejection Ratio
(dB)
1
10
100
1,000
55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias Current (pA)
CH0 = VDD
VDD = 5.5 V
1
10
100
10 100 1000
Capacitive Load (pF)
Bandwidth (MHz)
G = +1
G = +4
G = +16
40
50
60
70
80
90
100
10 100 1000 10000 100000
Frequency (Hz)
Power Supply Rejection Ratio
(dB)
VDD = 2.5 V
VDD = 5.5 V
1k 10k 100k10 100
Input Referred
1
10
100
1,000
10,000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Input Bias Current (pA)
TA = +85°C
VDD = 5.5 V
TA = +125°C
0
1
2
3
4
5
6
7
10 100 1000
Capacitive Load (pF)
Gain Peaking (dB)
G = +1
G = +4
G = +16
MCP6S21/2/6/8
DS21117A-page 12 2003 Microchip Technology Inc.
Note: Unless otherwise indicated, TA =+25°C, V
DD = +5.0V, VSS = GND, VREF =V
SS, G= +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL=10kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-19: Gain vs. Frequency.
FIGURE 2-20: Histogram of Quiescent
Current in Shutdown Mode.
FIGURE 2-21: Output Voltage Headroom
vs. Output Current.
FIGURE 2-22: Quiescent Current vs.
Supply Voltage.
FIGURE 2-23: Quiescent Current in
Shutdown Mode vs. Ambient Temperature.
FIGURE 2-24: Output Short Circuit Current
vs. Supply Voltage.
-20
-10
0
10
20
30
40
1.E+05 1.E+06 1.E+07 1.E+08
Frequency (Hz)
Gain (dB)
G = +2
G = +1
1M 10M 100M100k
G = +32
G = +16
G = +10
G = +8
G = +5
G = +4
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Quiescent Current in Shutdown (µA)
Percentage of Occurrences
420 Samples
VDD = 5.0 V
1
10
100
0.1 1 10
Output Current Magnitude (mA)
Output Voltage Headroom (mV)
VDD - VOH and VOL - VSS
VDD = +5.5V
VDD = +2.5V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
Quiescent Current (mA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Quiescent Current in Shutdown
(µA)
In Shutdown Mode
VDD = 5.0 V
0
5
10
15
20
25
30
35
40
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Output Short Circuit Current
(mA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
2003 Microchip Technology Inc. DS21117A-page 13
MCP6S21/2/6/8
Note: Unless otherwise indicated, TA =+25°C, V
DD = +5.0V, VSS = GND, VREF =V
SS, G= +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL=10kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-25: THD plus Noise vs.
Frequency, VOUT = 2 VP-P
.
FIGURE 2-26: Small Signal Pulse
Response.
FIGURE 2-27: Channel Select Timing.
FIGURE 2-28: THD plus Noise vs.
Frequency, VOUT = 4 VP-P
.
FIGURE 2-29: Large Signal Pulse
Response.
FIGURE 2-30: Gain Select Timing.
0.001
0.01
0.1
1
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
THD + Noise (%)
Measurement BW = 80 kHz
VOUT = 2 VP-P
VDD = 5.0 V
100 1k 100k10k
G = +4
G = +1
G = +16
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
0.00E+00 2.00E-07 4.00E-07 6.00E-07 8.00E-07 1.00E-06 1.20E-06 1.40E-06 1.60E-06 1.80E-06 2.00E-06
Time (200 ns/div)
Output Voltage
(10 mV/div)
-250
-200
-150
-100
-50
0
50
100
150
200
250
Normalized Input Voltage
(50 mV/div)
VDD = +5.0V
VOUT, G = +1
G = +5
G = +32
GVIN
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.00E+00 5.00E-07 1.00E-06 1.50E-06 2.00E-06 2.50E-06 3.00E-06 3.50E-06 4.00E-06 4.50E-06 5.00E-06
Time (500 ns/div)
Output Voltage (V)
-20
-15
-10
-5
0
5
10
15
20
Chip Select Voltage (V)
5
0
VOUT
(CH0 = 0.6V, G = +1)
VOUT
(CH1 = 0.3V, G = +1)
CS
CS
0.001
0.01
0.1
1
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
THD + Noise (%)
Measurement BW = 80 kHz
VOUT = 4 VP-P
VDD = 5.0 V
100 1k 100k10k
G = +4
G = +1
G = +16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.00E+00 5.00E-07 1.00E-06 1.50E-06 2.00E-06 2.50E-06 3.00E-06 3.50E-06 4.00E-06 4.50E-06 5.00E-06
Time (500 ns/div)
Output Voltage (V)
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
Normalized Input Voltage
(1V/div)
VDD = +5.0V
GVIN
VOUT, G = +1
G = +5
G = +32
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.00E+00 5.00E-07 1.00E-06 1.50E-06 2.00E-06 2.50E-06 3.00E-06 3.50E-06 4.00E-06 4.50E-06 5.00E-06
Time (500 ns/div)
Output Voltage (V)
-20
-15
-10
-5
0
5
10
15
20
Chip Select Voltage (V)
5
0
VOUT
(CH0 = 0.3V, G = +5)
VOUT
(CH0 = 0.3V, G = +1)
CS
CS
MCP6S21/2/6/8
DS21117A-page 14 2003 Microchip Technology Inc.
Note: Unless otherwise indicated, TA =+25°C, V
DD = +5.0V, VSS = GND, VREF =V
SS, G= +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL=10kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-31: Output Voltage vs.
Shutdown Mode.
FIGURE 2-32: POR Trip Voltage.
FIGURE 2-33: Output Voltage Swing vs.
Frequency.
FIGURE 2-34: The MCP6S21/2/6/8 family
shows no phase reversal under overdrive.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0E+00 1.0E-06 2.0E-06 3.0E-06 4.0E-06 5.0E-06 6.0E-06 7.0E-06 8.0E-06 9.0E-06 1.0E-05
Time (1 µs/div)
Output Voltage (mV)
-25
-20
-15
-10
-5
0
5
10
15
20
25
Chip Select Voltage (V)
5
0
VOUT is "ON"
(CH0 = 0.3V, G = +1)
Shutdown
CS
CS
Shutdown
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
1.60 1.64 1.68 1.72 1.76 1.80 1.84 1.88
POR Trip Voltage (V)
Percentage of Occurrences
420 Samples
0.1
1
10
1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Output Voltage Swing (VP-P)
VDD = 2.5 V
VDD = 5.5 V
G = +1, +2
G = +4 to +10
G = +16, +32
10k 100k 10M1M
-1
0
1
2
3
4
5
6
0.0E+00 1.0E-03 2.0E-03 3.0E-03 4.0E-03 5.0E-03 6.0E-03 7.0E-03 8.0E-03 9.0E-03 1.0E-02
Time (1 ms/div)
Input, Output Voltage (V)
VDD = 5.0 V
G = +1 V/V
VIN
VOUT
2003 Microchip Technology Inc. DS21117A-page 15
MCP6S21/2/6/8
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Output
The output pin (VOUT) is a low-impedance voltage
source. The selected gain (G), selected input (CH0-
CH7) and voltage at VREF determine its value.
3.2 Analog Inputs (CH0 thru CH7)
The inputs CH0 through CH7 connect to the signal
sources. They are high-impedance CMOS inputs with
low bias currents. The internal MUX selects which one
is amplified to the output.
3.3 External Reference Voltage (VREF)
The VREF pin should be at a voltage between VSS and
VDD (the MCP6S22 has VREF tied internally to VSS).
The voltage at this pin shifts the output voltage.
3.4 Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 2.5V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are between VSS and
VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (0.1 µF) at the VDD pin.
It can share a bulk capacitor with nearby analog parts
(typically 2.2 µF to 10 µF within 4 inches (100 mm) of
the VDD pin.
3.5 Digital Inputs
The SPI interface inputs are: Chip Select (CS), Serial
Input (SI) and Serial Clock (SCK). These are Schmitt-
triggered, CMOS logic inputs.
3.6 Digital Output
The MCP6S26 and MCP6S28 devices have a SPI
interface serial output (SO) pin. This is a CMOS push-
pull output and does not ever go High-Z. Once the
device is deselected (CS goes high), SO is forced low.
This feature supports daisy chaining, as explained in
Section 5.3, “Daisy Chain Configuration”.
MCP6S21 MCP6S22 MCP6S26 MCP6S28 Symbol Description
1111V
OUT Analog Output
2222CH0Analog Input
— 3 3 3 CH1 Analog Input
— — 4 4 CH2 Analog Input
— — 5 5 CH3 Analog Input
— — 6 6 CH4 Analog Input
— — 7 7 CH5 Analog Input
— — — 8 CH6 Analog Input
— — — 9 CH7 Analog Input
3—810V
REF External Reference Pin
44911V
SS Negative Power Supply
5 5 10 12 CS SPI Chip Select
6 6 11 13 SI SPI Serial Data Input
— — 12 14 SO SPI Serial Data Output
7 7 13 15 SCK SPI Clock Input
8 8 14 16 VDD Positive Power Supply
MCP6S21/2/6/8
DS21117A-page 16 2003 Microchip Technology Inc.
4.0 ANALOG FUNCTIONS
The MCP6S21/2/6/8 family of Programmable Gain
Amplifiers (PGA) are based on simple analog building
blocks (see Figure 4-1). Each of these blocks will be
explained in more detail in the following sub-sections.
FIGURE 4-1: PGA Block Diagram.
4.1 Input MUX
The MCP6S21 has one input, the MCP6S22 and
MCP6S25 have two inputs, the MCP6S26 has six
inputs and the MCP6S28 has eight inputs (see
Figure 4-1).
For the lowest input current, float unused inputs. Tying
these pins to a voltage near the used channels also
works well. For simplicity, they can be tied to VSS or
VDD, but the input current may increase.
The one channel MCP6S21 has the lowest input bias
current, while the eight channel MCP6S28 has the
highest. There is about a 2:1 ratio in IB between these
parts.
4.2 Internal Op Amp
The internal op amp provides the right combination of
bandwidth, accuracy and flexibility.
4.2.1 COMPENSATION CAPACITORS
The internal op amp has three compensation capaci-
tors connected to a switching network. They are
selected to give good small signal bandwidth at high
gains, and good slew rate (full power bandwidth) at low
gains. The change in bandwidth as gain changes is
between 2 MHz and 12 MHz. Refer to Table 4-1 for
more information.
TABLE 4-1: GAIN VS. INTERNAL COMPENSATION CAPACITOR
MCP6S21–One input (CH0), no SO pin
MCP6S22–Two inputs (CH0, CH1), VREF tied internally
to VSS, no SO pin
MCP6S26–Six inputs (CH0 to CH5)
MCP6S28–Eight inputs (CH0 to CH7)
VOUT
VREF
VDD
CS
SI
SO
SCK
CH1
CH0
CH3
CH2
CH5
CH4
CH7
CH6
VSS
8
RF
RG
MUX
SPI™
Logic
POR
Gain
Switches
+
-
Resistor Ladder (RLAD)
Gain
(V/V)
Internal
Compensation
Capacitor
Typical GBWP
(MHz)
Typical SR
(V/µs)
Typical FPBW
(MHz)
Typical BW
(MHz)
1 Large 12 4.0 0.30 12
2 Large 12 4.0 0.30 6
4Medium 20 11 0.70 10
5Medium 20 11 0.70 7
8 Medium 20 11 0.70 2.4
10 Medium 20 11 0.70 2.0
16 Small 64 22 1.6 5
32 Small 64 22 1.6 2.0
Note 1: FPBW is the Full Power Bandwidth. These numbers are based on VDD = 5.0V.
2: No changes in DC performance (e.g., VOS) accompany a change in compensation capacitor.
3: BW is the closed-loop, small signal -3 dB bandwidth.
2003 Microchip Technology Inc. DS21117A-page 17
MCP6S21/2/6/8
4.2.2 RAIL-TO-RAIL INPUT
The input stage of the internal op amp uses two differ-
ential input stages in parallel; one operates at low VIN
(input voltage), while the other operates at high VIN.
With this topology, the internal inputs can operate to
0.3V past either supply rail. The input offset voltage is
measured at both VIN =V
SS - 0.3V and VDD + 0.3V to
ensure proper operation.
The transition between the two input stages occurs
when VIN ≈VDD - 1.5V. For the best distortion and gain
linearity, avoid this region of operation.
4.2.3 RAIL-TO-RAIL OUTPUT
The Maximum Output Voltage Swing is the maximum
swing possible under a particular output load. Accord-
ing to the specification table, the output can reach
within 60 mV of either supply rail when RL=10kΩ and
VREF = VDD/2. See Figure 2-21 for typical performance
under other conditions.
4.2.4 INPUT VOLTAGE AND PHASE
REVERSAL
The amplifier family is designed with CMOS input
devices. It is designed to not exhibit phase inversion
when the input pins exceed the supply voltages.
Figure 2-34 shows an input voltage exceeding both
supplies with no resulting phase inversion.
The maximum voltage that can be applied to the input
pins (CHX) is VSS - 0.3V to VDD + 0.3V. Voltages on the
inputs that exceed this absolute maximum rating can
cause excessive current to flow in or out of the input
pins. Current beyond ±2 mA can cause possible reli-
ability problems. Applications that exceed this rating
must be externally limited with an input resistor, as
shown in Figure 4-2.
FIGURE 4-2: RIN limits the current flow
into an input pin.
4.3 Resistor Ladder
The resistor ladder shown in Figure 4-1 (RLAD = RF +
RG) sets the gain. Placing the gain switches in series
with the inverting input reduces the parasitic capaci-
tance, distortion and gain mismatch.
RLAD is an additional load on the output of the PGA and
causes additional current draw from the supplies.
In Shutdown mode, RLAD is still attached to the OUT
and VREF pins. Thus, these pins and the internal ampli-
fier’s inverting input are all connected through RLAD
and the output is not high-Z (unlike the external op
amp).
While RLAD contributes to the output noise, its effect is
small. Refer to Figure 2-12.
4.4 Shutdown Mode
These PGAs use a software shutdown command.
When the SPI interface sends a shutdown command,
the internal op amp is shut down and its output placed
in a high-Z state.
The resistive ladder is always connected between
VREF and VOUT
; even in shutdown. This means that the
output resistance will be on the order of 5 kΩ and there
will be a path for output signals to appear at the input.
The Power-on Reset (POR) circuitry will temporarily
place the part in shutdown when activated. See
Section 5.4, “Power-On Reset”, for details.
RIN
VSS Minimum expected VIN
()–
2 mA
----------------------------------------------------------------------------≥
RIN
Maximum expected VIN
()VDD
–
2 mA
-------------------------------------------------------------------------------
≥
VIN
RIN
VOUT
MCP6S2X
CHX
MCP6S21/2/6/8
DS21117A-page 18 2003 Microchip Technology Inc.
5.0 DIGITAL FUNCTIONS
The MCP6S21/2/6/8 PGAs use a standard SPI com-
patible serial interface to receive instructions from a
controller. This interface is configured to allow daisy
chaining with other SPI devices. There is an internal
POR (Power On Reset) that resets the registers under
low power conditions.
5.1 SPI Timing
Chip Select (CS) toggles low to initiate communication
with these devices. The first byte of each SI word (two
bytes long) is the instruction byte, which goes into the
Instruction Register. The Instruction Register points the
second byte to its destination. In a typical application,
CS is raised after one word (16 bits) to implement the
desired changes. Section 5.3, “Registers”, covers
applications using multiple 16-bit words. SO goes low
after CS goes high; it has a push-pull output that does
not go into a high-Z state.
The MCP6S21/2/6/8 devices operate in SPI Modes 0,0
and 1,1. In 0,0 mode, the clock idles in the low state
(Figure 5-1) and, in 1,1 mode, the clock idles in the high
state (Figure 5-2). In both modes, SI data is loaded into
the PGA on the rising edge of SCK and SO data is
clocked out on the falling edge of SCK. In 0,0 mode, the
falling edge of CS also acts as the first falling edge of
SCK (see Figure 5-1). There must be multiples of 16
clocks (SCK) while CS is low or commands will abort
(see Section 5.3, “Registers”).
FIGURE 5-1: Serial bus sequence for the PGA; SPI 0,0 mode (see Figure 1-5).
FIGURE 5-2: Serial bus sequence for the PGA; SPI 1,1 mode (see Figure 1-6).
12345678910 11 12 13 14 15 16
bit 7
CS
SCK
SI
Instruction Byte Data Byte
bit 0
bit 7
bit 0
SO
(first 16 bits out are always zeros)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
bit 7
CS
SCK
SI
Instruction Byte Data Byte
bit 0
bit 7
bit 0
SO
(first 16 bits out are always zeros)
2003 Microchip Technology Inc. DS21117A-page 19
MCP6S21/2/6/8
5.2 Registers
The analog functions are programmed through the SPI
interface using 16-bit words (see Figure 5-1 and
Figure 5-2). This data is sent to two of three 8-bit regis-
ters: Instruction Register (Register 5-1), Gain Register
(Register 5-2) and Channel Register (Register 5-3).
The power-up defaults for these three registers are:
• Instruction Register: 000x xxx0
• Gain Register: xxxx x000
• Channel Register: xxxx x000
Thus, these devices are initially programmed with the
Instruction Register set for NOP (no operation), a gain
of +1 V/V and CH0 as the input channel.
5.2.1 INSTRUCTION REGISTER
The Instruction Register has 3 command bits and 1
indirect address bit; see Register 5-1. The command
bits include a NOP (000) to support daisy chaining (see
Section 5.3, “Registers”); the other NOP commands
shown should not be used (they are reserved for future
use). The device is brought out of Shutdown mode
when a valid command, other than NOP or Shutdown, is
sent and CS is raised.
REGISTER 5-1: INSTRUCTION REGISTER
W-0 W-0 W-0 U-x U-x U-x U-x W-0
M2 M1 M0 ————A0
bit 7 bit 0
bit 7-5 M2-M0: Command Bits
000 = NOP (Default) (Note 1)
001 = PGA enters Shutdown Mode as soon as a full 16-bit word is sent and CS is raised.
(Notes 1 and 2)
010 = Write to register.
011 = NOP (reserved for future use) (Note 1)
1XX = NOP (reserved for future use) (Note 1)
bit 4-1 Unimplemented: Read as ‘0’ (reserved for future use)
bit 0 A0: Indirect Address Bit
1 = Addresses the Channel Register
0 = Addresses the Gain Register (Default)
Note 1: All other bits in the 16-bit word (including A0) are “don’t cares”.
2: The device exits Shutdown mode when a valid command (other than NOP or Shut-
down) is sent and CS is raised; that valid command will be executed. Shutdown
does not toggle.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
MCP6S21/2/6/8
DS21117A-page 20 2003 Microchip Technology Inc.
5.2.2 SETTING THE GAIN
The amplifier can be programmed to produce binary
and decimal gain settings between +1 V/V and +32 V/V.
Register 5-2 shows the details. At the same time, differ-
ent compensation capacitors are selected to optimize
the bandwidth vs. slew rate trade-off (see Table 4-1).
REGISTER 5-2: GAIN REGISTER
U-x U-x U-x U-x U-x W-0 W-0 W-0
— — — — —G2G1G0
bit 7 bit 0
bit 7-3 Unimplemented: Read as ‘0’ (reserved for future use)
bit 2-0 G2-G0: Gain Select Bits
000 = Gain of +1 (Default)
001 = Gain of +2
010 = Gain of +4
011 = Gain of +5
100 = Gain of +8
101 = Gain of +10
110 = Gain of +16
111 = Gain of +32
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS21117A-page 21
MCP6S21/2/6/8
5.2.3 CHANGING THE CHANNEL
If the instruction register is programmed to address the
channel register, the multiplexed inputs of the
MCP6S22, MCP6S26 and MCP6S28 can be changed
per Register 5-3.
REGISTER 5-3: CHANNEL REGISTER
U-x U-x U-x U-x U-x W-0 W-0 W-0
— — — — —C2C1C0
bit 7 bit 0
bit 7-3 Unimplemented: Read as ‘0’ (reserved for future use)
bit 2-0 C2-C0: Channel Select Bits
MCP6S21
000 = CH0 (Default)
001 = CH0
001 = CH0
011 = CH0
100 = CH0
101 = CH0
110 = CH0
111 = CH0
MCP6S22
CH0 (Default)
CH1
CH0
CH1
CH0
CH1
CH0
CH1
MCP6S26
CH0 (Default)
CH1
CH2
CH3
CH4
CH5
CH0
CH0
MCP6S28
CH0 (Default)
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
MCP6S21/2/6/8
DS21117A-page 22 2003 Microchip Technology Inc.
5.2.4 SHUTDOWN COMMAND
The software Shutdown command allows the user to
put the amplifier into a low power mode (see
Register 5-1). In this shutdown mode, most pins are
high impedance (Section 4.4, “Shutdown Mode”, and
Section 5.1, “SPI Timing”, cover the exceptions at pins
VREF, VOUT and SO).
Once the PGA has entered shutdown mode, it will
remain in this mode until either a valid command is sent
to the device (other than NOP or Shutdown), or the
device is powered down and back up again. The
internal registers maintain their values while in
shutdown.
Once brought out of shutdown mode, the part comes
back to its previous state (see Section 5.4 for excep-
tions to this rule). This makes it possible to bring the
device out of shutdown mode using one command;
send a command to select the current channel (or gain)
and the device will exit shutdown with the same state
that existed before shutdown.
5.3 Daisy Chain Configuration
Multiple devices can be connected in a daisy chain
configuration by connecting the SO pin from one device
to the SI pin on the next device and using common SCK
and CS lines (Figure 5-3). This approach reduces PCB
layout complexity.
The example in Figure 5-3 shows a daisy chain config-
uration with two devices, although any number of
devices can be configured this way. The MCP6S21 and
MCP6S22 can only be used at the far end of the daisy
chain because they do not have a serial data out (SO)
pin. As shown in Figure 5-4 and Figure 5-5, both SI
and SO data are sent in 16-bit (2 byte) words. These
devices abort any command that is not a multiple of 16
bits.
When using the daisy chain configuration, the maxi-
mum clock speed possible is reduced to ≈ 5.8 MHz
because of the SO pin’s propagation delay (see
Electrical Specifications).
The internal SPI shift register is automatically loaded
with zeros whenever CS goes high (a command is exe-
cuted). Thus, the first 16-bits out of the SO pin once CS
line goes low are always zeros. This means that the
first command loaded into the next device in the daisy
chain is a NOP. This feature makes it possible to send
shorter command and data byte strings when the far-
thest devices do not need to change. For example, if
there were three devices on the chain and only the mid-
dle device needed changing, only 32 bytes of data
need to be transmitted (for the first and middle
devices), and the last device on the chain would
receive a NOP when the CS pin is raised to execute the
command.
FIGURE 5-3: Daisy Chain Configuration.
Microcontroller
SO
CS
SCK
SI
CS
SCK
SO
Device 1
Device 1
00100000 00000000
SO
CS
SCK
SI
Device 2
Device 2
00000000 00000000
1. Set CS low.
2. Clock out the instruction and data
for Device 2 (16 clocks) to Device 1.
3. Device 1 automatically clocks out all
zeros (first 16 clocks) to Device 2.
4. Clock out the instruction and data
for Device 1 (16 clocks) to Device 1.
5. Device 1 automatically shifts data
from Device 1 to Device 2 (16
clocks).
6. Raise CS.
Device 1
01000001 00000111
Device 2
00100000 00000000
PICmicro®
2003 Microchip Technology Inc. DS21117A-page 23
MCP6S21/2/6/8
FIGURE 5-4: Serial bus sequence for daisy-chain configuration; SPI 0,0 mode.
FIGURE 5-5: Serial bus sequence for daisy-chain configuration; SPI 1,1 mode.
12345678910111213141516
bit 7
CS
SCK
SI
Instruction Byte Data Byte
bit 0
bit 7
bit 0
SO
(first 16 bits out are always zeros)
1 2 3 4 5 6 7 8 9 10111213141516
bit 7
Instruction Byte Data Byte
bit 0
bit 7
bit 0
for Device 2 for Device 2 for Device 1 for Device 1
bit 7
Instruction Byte Data Byte
bit 0
bit 7
bit 0
for Device 2 for Device 2
12345678910111213141516
bit 7
CS
SCK
SI
Instruction Byte Data Byte
bit 0
bit 7
bit 0
SO
(first 16 bits out are always zeros)
12345678910111213141516
bit 7
Instruction Byte Data Byte
bit 0
bit 7
bit 0
for Device 2 for Device 2 for Device 1 for Device 1
bit 7
Instruction Byte Data Byte
bit 0
bit 7
bit 0
for Device 2 for Device 2
MCP6S21/2/6/8
DS21117A-page 24 2003 Microchip Technology Inc.
5.4 Power-On Reset
If the power supply voltage goes below the POR trip
voltage (VDD < VPOR ≈ 1.7V), the internal POR circuit
will reset all of the internal registers to their power-up
defaults (this is a protection against low power supply
voltages). The POR circuit also holds the part in shut-
down mode while it is activated. It temporarily overrides
the software shutdown status. The POR releases the
shutdown circuitry once it is released (VDD > VPOR).
A 0.1 µF bypass capacitor mounted as close as possi-
ble to the VDD pin provides additional transient
immunity.
2003 Microchip Technology Inc. DS21117A-page 25
MCP6S21/2/6/8
6.0 APPLICATIONS INFORMATION
6.1 Changing External Reference
Voltage
Figure 6-1 shows a MCP6S21 with the VREF pin at
2.5V and VDD = 5.0V. This allows the PGA to amplify
signals centered on 2.5V, instead of ground-referenced
signals. The voltage reference MCP1525 is buffered by
a MCP6021, which gives a low output impedance ref-
erence voltage from DC to high frequencies. The
source driving the VREF pin should have an output
impedance of ≤0.1Ω to maintain reasonable gain
accuracy.
FIGURE 6-1: PGA with Different External
Reference Voltage.
6.2 Capacitive Load and Stability
Large capacitive loads can cause both stability prob-
lems and reduced bandwidth for the MCP6S21/2/6/8
family of PGAs (Figure 2-17 and Figure 2-18). This
happens because a large load capacitance decreases
the internal amplifier’s phase margin and bandwidth.
If the PGA drives a large capacitive load, the circuit in
Figure 6-2 can be used. A small series resistor (RISO)
at the VOUT improves the phase margin by making the
load resistive at high frequencies. It will not, however,
improve the bandwidth.
FIGURE 6-2: PGA Circuit for Large
Capacitive Loads.
For CL≥100 pF, a good estimate for RISO is 50Ω. This
value can be fine-tuned on the bench. Adjust RISO so
that the step response overshoot and frequency
response peaking are acceptable at all gains.
6.3 Layout Considerations
Good PC board layout techniques will help achieve the
performance shown in the Electrical Characteristics
and Typical Performance Curves. It will also help
minimize EMC (Electro-Magnetic Compatibility) issues.
6.3.1 COMPONENT PLACEMENT
Separate circuit functions; digital from analog, low
speed from high speed, and low power from high
power, as this will reduce crosstalk.
Keep sensitive traces short and straight, separating
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.
Use a 0.1 µF supply bypass capacitor within 0.1 inch
(2.5 mm) of the VDD pin. It must connect directly to the
ground plane. A multi-layer ceramic chip capacitor, or
high-frequency equivalent, works best.
6.3.2 SIGNAL COUPLING
The input pins of the MCP6S21/2/6/8 family of opera-
tional amplifiers (op amps) are high-impedance. This
makes them especially susceptible to capacitively-cou-
pled noise. Using a ground plane helps reduce this
problem.
When noise is capacitively-coupled, the ground plane
provides additional shunt capacitance to ground. When
noise is magnetically coupled, the ground plane
reduces the mutual inductance between traces.
Increasing the separation between traces makes a
significant difference.
Changing the direction of one of the traces can also
reduce magnetic coupling. It may help to locate guard
traces next to the victim trace. They should be on both
sides of the victim trace and be as close as possible.
Connect the guard traces to the ground plane at both
ends, and in the middle, of long traces.
6.3.3 HIGH FREQUENCY ISSUES
Because the MCP6S21/2/6/8 PGAs reach unity gain
near 64 MHz when G = 16 and 32, it is important to use
good PCB layout techniques. Any parasitic coupling at
high frequency might cause undesired peaking. Filter-
ing high frequency signals (i.e., fast edge rates) can
help. To minimize high frequency problems:
• Use complete ground and power planes
• Use HF, surface mount components
• Provide clean supply voltages and bypassing
• Keep traces short and straight
• Try a linear power supply (e.g., an LDO)
VDD
VREF
MCP6S21
MCP1525
MCP6021
2.5V
REF
VDD
VDD
VIN VOUT
1µF
VIN MCP6S2X
RISO
VOUT
CL
MCP6S21/2/6/8
DS21117A-page 26 2003 Microchip Technology Inc.
6.4 Typical Applications
6.4.1 GAIN RANGING
Figure 6-3 shows a circuit that measures the current IX.
It benefits from changing the gain on the PGA. Just as
a hand-held multimeter uses different measurement
ranges to obtain the best results, this circuit makes it
easy to set a high gain for small signals and a low gain
for large signals. As a result, the required dynamic
range at the PGA’s output is less than at its input (by up
to 30 dB).
FIGURE 6-3: Wide Dynamic Range
Current Measurement Circuit.
6.4.2 SHIFTED GAIN RANGE PGA
Figure 6-4 shows a circuit using an MCP6021 at a gain
of +10 in front of an MCP6S21. This changes the over-
all gain range to +10 V/V to +320 V/V (from +1 V/V to
+32 V/V).
FIGURE 6-4: PGA with Modified Gain
Range.
It is also easy to shift the gain range to lower gains (see
Figure 6-6). The MCP6021 acts as a unity gain buffer,
and the resistive voltage divider shifts the gain range
down to +0.1 V/V to +3.2 V/V (from +1 V/V to +32 V/V).
FIGURE 6-5: PGA with lower gain range.
6.4.3 EXTENDED GAIN RANGE PGA
Figure 6-6 gives a +1 V/V to +1024 V/V gain range,
which is much greater than the range for a single PGA
(+1 V/V to +32 V/V). The first PGA provides input mul-
tiplexing capability, while the second PGA only needs
one input. These devices can be daisy chained
(Section 5.3, “Daisy Chain Configuration”).
FIGURE 6-6: PGA with Extended Gain
Range.
6.4.4 MULTIPLE SENSOR AMPLIFIER
The multiple channel PGAs (except the MCP6S21)
allow the user to select which sensor appears on the
output (see Figure 6-7). These devices can also
change the gain to optimize performance for each
sensor.
FIGURE 6-7: PGA with Multiple Sensor
Inputs.
MCP6S2X VOUT
IXRS
VIN
MCP6021 MCP6S21 VOUT
10.0 kΩ
1.11 kΩ
+
_
VIN
MCP6021
MCP6S21
VOUT
10.0 kΩ
1.11 kΩ
+
_
VIN VOUT
MCP6S28 MCP6S21
Sensor # 0
Sensor # 1
Sensor # 5
MCP6S26 VOUT
2003 Microchip Technology Inc. DS21117A-page 27
MCP6S21/2/6/8
6.4.5 EXPANDED INPUT PGA
Figure 6-8 shows cascaded MCP6S28s that provide
up to 15 input channels. Obviously, Sensors #7-14
have a high total gain range available, as explained in
Section 6.4.3, “Extended Gain Range”. These devices
can be daisy chained (Section 5.3, “Daisy Chain
Configuration”).
FIGURE 6-8: PGA with Expanded Inputs.
6.4.6 PICmicro® MCU WITH EXPANDED
INPUT CAPABILITY
Figure 6-9 shows an MCP6S28 driving an analog input
to a PICmicro® microcontroller. This greatly expands
the input capacity of the microcontroller, while adding
the ability to select the appropriate gain for each
source.
FIGURE 6-9: Expanded Input for a
PICmicro Microcontroller.
6.4.7 ADC DRIVER
The family of PGA’s is well suited for driving Analog-to-
Digital Converters (ADC). The binary gains (1, 2, 4, 8,
16 and 32) effectively add five more bits to the input
range (see Figure 6-10). This works well for applica-
tions needing relative accuracy more than absolute
accuracy (e.g., power monitoring).
FIGURE 6-10: PGA as an ADC Driver.
At low gains, the ADC’s Signal-to-Noise Ratio (SNR)
will dominate since the PGAs input noise voltage den-
sity is so low (10 nV/√Hz @ 10 kHz, typ.). At high gains,
the PGA’s noise will dominate the SNR, but its low
noise supports most applications. Again, these PGAs
add the flexibility of selecting the best gain for an
application.
The low pass filter in the block diagram reduces the
integrated noise at the MCP6S28’s output and serves
as an anti-aliasing filter. This filter may be designed
using Microchip’s FilterLab® software, available at
www.microchip.com.
Sensors
Sensors MCP6S28
MCP6S28 VOUT
# 0-6
# 7-14
VIN MCP6S28 PICmicro®
Microcontroller
SPI™
VIN OUT
MCP6S28
Lowpass
Filter
12
MCP3201
MCP6S21/2/6/8
DS21117A-page 28 2003 Microchip Technology Inc.
7.0 PACKAGING INFORMATION
7.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) (MCP6S21, MCP6S22)Example:
8-Lead SOIC (150 mil) (MCP6S21, MCP6S22)Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6S21
I/P256
0345
MCP6S21
I/SN0345
256
8-Lead MSOP (MCP6S21, MCP6S22)Example:
XXXXX
YWWNNN
MCP6S21I
345256
Legend: XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office.
2003 Microchip Technology Inc. DS21117A-page 29
MCP6S21/2/6/8
Package Marking Information (Con’t)
14-Lead PDIP (300 mil) (MCP6S26)Example:
14-Lead SOIC (150 mil) (MCP6S26)Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
YYWWNNN
MCP6S26-I/P
XXXXXXXXXXXXXX
0345256
XXXXXXXXXXX
MCP6S26ISL
0345256
XXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXX
NNN
YYWW
14-Lead TSSOP (4.4mm) (MCP6S26)Example:
MCP6S26IST
256
0345
MCP6S21/2/6/8
DS21117A-page 30 2003 Microchip Technology Inc.
Package Marking Information (Con’t)
16-Lead PDIP (300 mil) (MCP6S28)Example:
16-Lead SOIC (150 mil) (MCP6S28)Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXXXX
YYWWNNN
MCP6S28-I/P
XXXXXXXXXXXXXX
0345256
XXXXXXXXXXXXX
MCP6S28-I/SL
0345256
XXXXXXXXXXXXXXXXXXXXXXXX
2003 Microchip Technology Inc. DS21117A-page 31
MCP6S21/2/6/8
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
MCP6S21/2/6/8
DS21117A-page 32 2003 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.33.020.017.013BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length
0.510.380.25.020.015.010hChamfer Distance
5.004.904.80.197.193.189DOverall Length
3.993.913.71.157.154.146E1Molded Package Width
6.206.025.79.244.237.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27.050
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
2003 Microchip Technology Inc. DS21117A-page 33
MCP6S21/2/6/8
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
p
A
A1
A2
D
L
c
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
.037.035FFootprint (Reference)
exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-111
*Controlling Parameter
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Lead Width
Lead Thickness
β
α
c
B
φ
7
7
.004
.010
0
.006
.012
(F)
β
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff §
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
.016
.114
.114
.022
.118
.118
.002
.030
.193
.034
MIN
p
n
Units
.026
NOM
8
INCHES
1.000.950.90.039
0.15
0.30
.008
.016
6
0.10
0.25
0
7
7
0.20
0.40
6
MILLIMETERS*
0.65
0.86
3.00
3.00
0.55
4.90
.044
.122
.028
.122
.038
.006
0.40
2.90
2.90
0.05
0.76
MINMAX NOM
1.18
0.70
3.10
3.10
0.15
0.97
MAX
8
α
E1
E
B
n 1
2
φ
§ Significant Characteristic
.184 .200 4.67 .5.08
MCP6S21/2/6/8
DS21117A-page 34 2003 Microchip Technology Inc.
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
n
D
1
2
eB
β
E
c
A
A1
B
B1
L
A2
p
α
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n14 14
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .740 .750 .760 18.80 19.05 19.30
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α5 10 15 5 10 15
β5 10 15 5 10 15
Mold Draft Angle Bottom
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
§ Significant Characteristic
2003 Microchip Technology Inc. DS21117A-page 35
MCP6S21/2/6/8
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.36.020.017.014BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length
0.510.380.25.020.015.010hChamfer Distance
8.818.698.56.347.342.337DOverall Length
3.993.903.81.157.154.150E1Molded Package Width
6.205.995.79.244.236.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27.050
p
Pitch
1414
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
h
L
c
β
45°
φ
α
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
§ Significant Characteristic
MCP6S21/2/6/8
DS21117A-page 36 2003 Microchip Technology Inc.
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
840840
φ
Foot Angle
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.300.250.19.012.010.007B1Lead Width
0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length
5.105.004.90.201.197.193DMolded Package Length
4.504.404.30.177.173.169E1Molded Package Width
6.506.386.25.256.251.246EOverall Width
0.150.100.05.006.004.002A1Standoff §
0.950.900.85.037.035.033A2Molded Package Thickness
1.10.043AOverall Height
0.65.026
p
Pitch
1414
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERS*INCHESUnits
L
β
c
φ
2
1
D
n
B
p
E1
E
α
A2A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
§ Significant Characteristic
2003 Microchip Technology Inc. DS21117A-page 37
MCP6S21/2/6/8
16-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom
1510515105
α
Mold Draft Angle Top
10.929.407.87.430.370.310
eB
Overall Row Spacing §
0.560.46.036.022.018.014BLower Lead Width
1.781.461.14.070.058.045B1Upper Lead Width
0.380.290.20.015.012.008
c
Lead Thickness
3.433.303.18.135.130.125LTip to Seating Plane
19.3019.0518.80.760.750.740DOverall Length
6.606.356.10.260.250.240E1Molded Package Width
8.267.947.62.325.313.300EShoulder to Shoulder Width
0.38.015A1Base to Seating Plane
3.683.302.92.145.130.115
A2
Molded Package Thickness
4.323.943.56.170.155.140ATop to Seating Plane
2.54.100
p
Pitch
1616
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
n
E1
c
β
eB
E
α
p
L
A2
B
B1
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-017
§ Significant Characteristic
MCP6S21/2/6/8
DS21117A-page 38 2003 Microchip Technology Inc.
16-Lead Plastic Small Outline (SL) – Narrow 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.33.020.017.013BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length
0.510.380.25.020.015.010hChamfer Distance
10.019.919.80.394.390.386DOverall Length
3.993.903.81.157.154.150E1Molded Package Width
6.206.025.79.244.237.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.441.32.061.057.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27.050
p
Pitch
1616
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
α
A2
E1
1
2
L
h
n
B
45°
E
p
D
φ
β
c
A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-108
§ Significant Characteristic
2003 Microchip Technology Inc. DS21117A-page 39
MCP6S21/2/6/8
NOTES:
2002 Microchip Technology Inc. DS21117A-page 39
MCP6S21/2/6/8
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
PART NO. -X /XX
PackageTemperature
Range
Device
Device: MCP6S21: One Channel PGA
MCP6S21T: One Channel PGA
(Tape and Reel for SOIC and MSOP)
MCP6S22: Two Channel PGA
MCP6S22T: Two Channel PGA
(Tape and Reel for SOIC and MSOP)
MCP6S26: Six Channel PGA
MCP6S26T: Six Channel PGA
(Tape and Reel for SOIC and TSSOP)
MCP6S28: Eight Channel PGA
MCP6S28T: Eight Channel PGA
(Tape and Reel for SOIC)
Temperature Range: I = -40°C to +85°C
Package: MS = Plastic Micro Small Outline (MSOP), 8-lead
P = Plastic DIP (300 mil Body), 8, 14, and 16-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14, 16-lead
ST = Plastic TSSOP (4.4mm Body), 14-lead
Examples:
a) MCP6S21-I/P: One Channel PGA,
PDIP package.
b) MCP6S21-I/SN: One Channel PGA,
SOIC package.
c) MCP6S21-I/MS: One Channel PGA,
MSOP package.
d) MCP6S22-I/MS: Two Channel PGA,
MSOP package.
e) MCP6S22T-I/MS: Tape and Reel,
Two Channel PGA, MSOP package.
f) MCP6S26-I/P: Six Channel PGA,
PDIP package.
g) MCP6S26-I/SN: Six Channel PGA,
SOIC package.
h) MCP6S26T-I/ST: Tape and Reel,
Six Channel PGA, TSSOP package.
i) MCP6S28T-I/SL: Tape and Reel,
Eight Channel PGA, SOIC package.
MCP6S21/2/6/8
DS21117A-page 40 2002 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS21117A - page 41
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications. No
representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the
accuracy or use of such information, or infringement of patents
or other intellectual property rights arising from such use or
otherwise. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Accuron, Application Maestro, dsPIC, dsPICDEM,
dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM,
fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal,
PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark of
Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such
acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
DS21117A-page 42 2003 Microchip Technology Inc.
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02/12/03
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