AS7C3512-35PC - Alliance Semiconductor

ALLIANCE SEMICONDUCTOR

High Performance

64K×8 3.3V

CMOS SRAM

AS7C3512

AS7C3512L

Low voltage 64K×8 CMOS SRAM

Logic block diagram

256×256×8

Array

(524,288)

Input buffer

10 A

11 A

12 A

13 A

I/O0

I/O7

Vcc

GND

CE1

Col umn decoder

Row decoder

Control

circuit

Sense amp

15 CE2

Pin arrangement

Vcc

A15

CE2

A13

A11

A10

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

A14

A12

I/O0

I/O1

I/O2

GND

AS7C3512

DIP, SOJ

Selection guide

Shaded areas contain advance information.

7C3512-12 7C3512-15 7C3512-20 7C3512-25 7C3512-35 Unit

Maximum address access time 12 15 20 25 35 ns

Maximum output enable access time 34568ns

Maximum operating current 70 65 60 55 50 mA

Maximum CMOS standby current 2.5 2.5 2.5 2.5 2.5 mA

L0.5 0.5 0.5 0.5 0.5 mA

Features

• Organization: 65,536 words × 8 bits

• Single 3.3 ±0.3V power supply

• 5V tolerant I/O specification

• High speed

- 12/15/20/25/35 ns address access time

- 3/4/5/6/8 ns output enable access time

• Very low power consumption

- Active: 250 mW max, 12 ns cycle

- Standby: 9.0 mW max, CMOS I/O

1.8 mW max, CMOS I/O, L version

• 2.0V data retention

• Equal access and cycle times

• Easy memory expansion with CE1, CE2 and OE inputs

• TTL-compatible, three-state I/O

• Ideal for cache and portable computing

- 75% power reduction during CPU idle mode

• 32-pin JEDEC standard packages

- 300 mil PDIP and SOJ

• ESD protection >2000 volts

• Latch-up current >200 mA

Preliminary information

AS7C3512

AS7C3512L

Functional description

The AS7C3512 is a 3.3V high performance CMOS 524,288-bit Static Random Access Memory (SRAM) organized as 65,536 words × 8 bits.

It is designed for memory applications requiring fast data access at low voltage, including Pentium™, PowerPC™, and portable computing.

Alliance’s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins.

The device enters standby mode when CE1 is HIGH or CE2 is LOW. CMOS standby mode consumes ≤9.0 mW (≤1.8 mW for the L version).

Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and

stretch mode. Both versions of the AS7C3512 offer 2.0V data retention.

Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20/25/35 ns with output enable access times (tOE) of 3/4/5/6/8 ns are ideal

for high performance applications. The active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank

memory systems.

A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written

on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external

devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip

drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is

active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and 5V tolerant. Operation is from a single 3.3±0.3V supply. The AS7C3512 is packaged in

all high volume industry standard packages.

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Truth table

Key: X = Don’t Care, L = LOW, H = HIGH

Parameter Symbol Min Max Unit

Power supply voltage relative to GND VCC –0.5 +4.6 V

Input voltage relative to GND VIN –0.5 +6.0 V

Power dissipation PD–1.0W

Storage temperature (plastic) Tstg –55 +150 oC

Temperature under bias Tbias –10 +85 oC

DC output current Iout –20mA

CE1 CE2 WE OE Data Mode

H X X X High Z Standby (ISB, ISB1)

X L X X High Z Standby (ISB, ISB1)

L H H H High Z Output disable

LHHLD

out Read

LHLXD

in Write

AS7C3512

AS7C3512L

Recommended operating conditions (Ta = 0°C to +70°C)

†VIL min = –2.0V for pulse width less than tRC/2.

DC operating characteristics1(VCC = 3.3±0.3V, GND = 0V, Ta = 0°C to +70°C)

Shaded areas contain advance information.

Capacitance2(f = 1 MHz, Ta = Room temperature, VCC = 3.3V)

Parameter Symbol Min Typ Max Unit

Supply voltage VCC 3.0 3.3 3.6 V

GND 0.0 0.0 0.0 V

Input voltage VIH 2.0 - 5.5 V

VIL –0.5†-0.8V

Parameter Symbol Test conditions

-12 -15 -20 -25 -35

Unit

Min Max Min Max Min Max Min Max Min Max

Input leakage

current |ILI|VCC = Max,

Vin = GND to VCC –1–1–1–1–1µA

Output

leakage current |ILO|CE1 = VIH or CE2 = VIL,

VCC = Max,

Vout = GND to VCC

–1–1–1–1–1µA

Operating

power supply

current

ICC CE1 = VIL, CE2 = VIH,

f = fmax, Iout = 0 mA –70 – 65 – 60 – 55 – 50 mA

Standby

power supply

current

ISB CE1 = VIH or CE2 = VIL,

f = fmax

– 30 – 25 – 20 – 20 – 15 mA

ISB1

CE1 ≥ VCC–0.2V or CE2 ≤ 0.2V,

Vin ≤ 0.2V or Vin ≥ VCC–0.2V,

f = 0

– 2.5 – 2.5 – 2.5 – 2.5 – 2.5 mA

L– 0.5 – 0.5 – 0.5 – 0.5 – 0.5 mA

Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 – 0.4 V

VOH IOH = –4 mA, VCC = Min 2.4 –2.4–2.4–2.4–2.4– V

Parameter Symbol Signals Test conditions Max Unit

Input capacitance CIN A, CE1, CE2, WE, OE Vin = 0V 5 pF

I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF

AS7C3512

AS7C3512L

Read cycle3,9,12 (VCC = 3.3±0.3V, GND = 0V, Ta = 0°C to +70°C)

Shaded areas contain advance information

Read waveform 13,6,7,9,12 Address controlled

Read waveform 23,6,8,9,12 CE1 and CE2 controlled

Parameter Symbol

-12 -15 -20 -25 -35

Unit Notes

Min Max Min Max Min Max Min Max Min Max

Read cycle time tRC 12 –15–20–25–35– ns

Address access time tAA –12 – 15 – 20 – 25 – 35 ns 3

Chip enable (CE1) access time tACE1 –12 – 15 – 20 – 25 – 35 ns 3, 12

Chip enable (CE2) access time tACE2 –12 – 15 – 20 – 25 – 35 ns 3, 12

Output enable (OE) access time tOE –3–4–5–6–8ns

Output hold from address change tOH 3–3–3–3–3–ns5

Chip enable (CE1) to output in Low Z tCLZ1 3–3–3–3–3–ns4, 5, 12

Chip enable (CE2) to output in Low Z tCLZ2 3–3–3–3–3–ns4, 5, 12

Chip disable (CE1) to output in High Z tCHZ1 –3–4–5–6–8ns4, 5, 12

Chip disable (CE2) to output in High Z tCHZ2 –3–4–5–6–8ns4, 5, 12

Output enable to output in Low Z tOLZ 0–0–0–0–0–ns4, 5

Output disable to output in High Z tOHZ –3–4–5–6–8ns4, 5

Chip enable to power up time tPU 0–0–0–0–0– ns4, 5, 12

Chip disable to power down time tPD – 12 – 15 – 20 – 25 – 35 ns 4, 5, 12

AAAA

Address

Dout Dat a Vali d

tOH

tAA

tRC

AAAA

Supply

Current

CE2

Dout

tOE

tOLZ

tACE1, tACE2 tCHZ1, tCHZ2

tCLZ1, tCLZ2

tPU

tPD ICC

ISB

50% 50%

tOHZ

AAAA

AAA

Data Valid

AAAA

tRC1

CE1

AS7C3512

AS7C3512L

Write cycle11,12 (VCC = 3.3±0.3V, GND = 0V, Ta = 0°C to +70°C)

Write waveform 110,11,12 WE controlled

Write waveform 210,11,12 CE1 and CE2 controlled

Parameter Symbol

-12 -15 -20 -25 -35

Unit Notes

Min Max Min Max Min Max Min Max Min Max

Write cycle time tWC 12 –15–20–25–30– ns

Chip enable (CE1) to write end tCW1 10 –12–12–15–20– ns12

Chip enable (CE2) to write end tCW2 10 –12–12–15–20– ns12

Address setup to write end tAW 10 –12–12–15–20– ns

Address setup time tAS 0–0–0–0–0–ns12

Write pulse width tWP 8– 9 – 12 – 15 – 17 – ns

Address hold from end of write tAH 0–0–0–0–0–ns

Data valid to write end tDW 6– 8 – 10 – 12 – 15 – ns

Data hold time tDH 0–0–0–0–0–ns4, 5

Write enable to output in High Z tWZ –5–5–5–5–5ns4, 5

Output active from write end tOW 3–3–3–3–3–ns4, 5

AW tAH

tWC

AAAA

Address

Din

Dout

tDH

tOW

tDW

tWZ

tWP

tAS

Data Valid

tAW

AAAA

AAA

Address

CE1

Din

Dout

tCW1, tCW2

tWP

tDW tDH

tAH

tWZ

tWC

AAAA

AAA

tAS

CE2

Dat a Vali d

AS7C3512

AS7C3512L

Data retention characteristics

Data retention waveform

AC test conditions

Notes

1 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.

2 This parameter is sampled and not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A, B, C.

CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.

5 This parameter is guaranteed but not tested.

6WE

is HIGH for read cycle.

7 CE1 and OE are LOW and CE2 is HIGH for read cycle.

8 Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE1 or WE must be HIGH or CE2 LOW during address transitions.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1 and CE2 have identical timing.

Parameter Symbol Test Conditions Min Max Unit

VCC for data retention VDR VCC = 2.0V

CE1 ≥ VCC–0.2V or

CE2 ≤ 0.2V

Vin ≥ VCC–0.2V or

Vin ≤ 0.2V

2.0 – V

Data retention current ICCDR

– 1200 µA

L – 250 µA

Chip deselect to data retention time tCDR 0–ns

Operation recovery time tRtRC –ns

Input leakage current | ILI | –1µA

AAAA

AAA

AAAA

AAA

CE1

tCDR

Dat a Retentio n Mo de

3.0V 3.0V

VDR ≥ 2.0V

VIH VIH

VDR

350Ω

• Output load: see Figure B,

except for tCLZ and tCHZ see Figure C.

• Input pulse level: GND to 3.0V. See Figure A.

• Input rise and fall times: 5 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

5 pF*

320Ω

Dout

GND

+3.3V

168Ω

Thevenin equivalent:

Dout +1.72V

Figure C: Output Load for tCLZ, tCHZ

350Ω30 pF*

320Ω

Dout

GND

+3.3V

Figure B: Output Load

*including sco pe

10%

90%

10%

90%

GND

+3.3V

Figure A: Input Waveform and jig capacitance

AS7C3512

AS7C3512L

Typical DC and AC characteristics

Supply voltage (V)

3.0 3.6

3.3

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC, ISB

Normalized supply current ICC, ISB

Am bi ent temper at ure (°C)

–15 60 85

3510

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC, ISB

Normalized supply cur rent ICC, ISB

vs. ambient te mper ature Ta

vs. supply voltage VCC

ICC

ISB

ICC

ISB

Ambient temperature (°C)

-55 80 125

35-10

0.2

0.04

625

Normalized ISB1 (log sc ale)

Normalized supply current ISB1

vs. am bient temperat ure Ta

VCC = 3. 30V

Supply voltage (V)

3.0 3.6

3.3

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Nor malized access time

Normalized access time tAA

Ambient temperature (°C)

–15 80 85

3510

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Nor malized access time

Normalized access time tAA

Cycle frequency (MHz)

060

4020

0.0

0.2

0.6

0.8

0.4

1.2

1.4

No rm al ized ICC

Normalize d supply current ICC

vs. ambi ent temper at ure Tavs. cycle frequency 1/tRC, 1/tWC

vs. supply voltage VCC

VCC = 3.3V

Ta = 25°C

VCC = 3.3VTa = 25° C

Output voltage (V)

0.0 3.3

1.65

Output source current (mA)

Output source current IOH

Output voltage (V)

0.0 3.3

1.65

Out put sink cur rent (mA)

Out put sink curre nt IOL

Capacitance (pF)

0750

1000

500250

Change in tAA (ns)

Typical access time change ∆tAA

vs. output voltage VOL vs. output capacitive loa dingvs. out p ut vol tage VOH

VCC = 3.3V

Ta = 25°C VCC = 3.3V

AS7C3512

AS7C3512L

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ALLIANCE SEMICONDUCTOR

3099 North First Street San Jose, CA 95134 Tel (408) 383-4900 Fax (408) 383-4999 www.alsc.com

Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a

committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not

authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion® and the Alliance logo are registered trademarks

of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders.

Ordering information

Shaded areas contain advance information.

Part numbering system

Representatives, distributors, and sales offices

Package \ Access Time 12 ns 15 ns 20 ns 25 ns 35 ns

Plastic DIP, 300 mil AS7C3512-12PC

AS7C3512L-12PC

AS7C3512-15PC

AS7C3512L-15PC

AS7C3512-20PC

AS7C3512L-20PC

AS7C3512-25PC

AS7C3512L-25PC

AS7C3512-35PC

AS7C3512L-35PC

Plastic SOJ, 300 mil AS7C3512-12JC

AS7C3512L-12JC

AS7C3512-15JC

AS7C3512L-15JC

AS7C3512-20JC

AS7C3512L-20JC

AS7C3512-25JC

AS7C3512L-25JC

AS7C3512-35JC

AS7C3512L-35JC

AS7C 3 512 –XX X C

SRAM prefix Blank = 5V supply

3 = 3.3V supply Device number Access time Package: P = PDIP 300 mil

J = SOJ 300 mil

Commercial temperature range,

0°C to 70 °C