High Performance 64Kx8 3.3V CMOS SRAM AS7C3512 AS7C3512L (R) Low voltage 64Kx8 CMOS SRAM Preliminary information Features * Organization: 65,536 words x 8 bits * Single 3.3 0.3V power supply * 5V tolerant I/O specification * High speed - 12/15/20/25/35 ns address access time - 3/4/5/6/8 ns output enable access time * Very low power consumption - Active: 250 mW max, 12 ns cycle - Standby: 9.0 mW max, CMOS I/O 1.8 mW max, CMOS I/O, L version * 2.0V data retention * Equal access and cycle times * Easy memory expansion with CE1, CE2 and OE inputs * TTL-compatible, three-state I/O * Ideal for cache and portable computing - 75% power reduction during CPU idle mode * 32-pin JEDEC standard packages - 300 mil PDIP and SOJ * ESD protection >2000 volts * Latch-up current >200 mA Logic block diagram Pin arrangement DIP, SOJ GND 256x256x8 Array (524,288) Sense amp I/O7 Row decoder A0 A1 A2 A3 A4 A5 A6 A7 I/O0 WE Column decoder Control circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND Input buffer OE AS7C3512 Vcc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 CE1 CE2 A A A A A A A A 8 9 10 11 12 13 14 15 Selection guide Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current L 7C3512-12 12 3 70 2.5 0.5 7C3512-15 15 4 65 2.5 0.5 7C3512-20 20 5 60 2.5 0.5 7C3512-25 25 6 55 2.5 0.5 Shaded areas contain advance information. ALLIANCE SEMICONDUCTOR 7C3512-35 35 8 50 2.5 0.5 Unit ns ns mA mA mA AS7C3512 AS7C3512L Functional description The AS7C3512 is a 3.3V high performance CMOS 524,288-bit Static Random Access Memory (SRAM) organized as 65,536 words x 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance's advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins. The device enters standby mode when CE1 is HIGH or CE2 is LOW. CMOS standby mode consumes 9.0 mW (1.8 mW for the L version). Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions of the AS7C3512 offer 2.0V data retention. Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20/25/35 ns with output enable access times (tOE) of 3/4/5/6/8 ns are ideal for high performance applications. The active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory systems. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and 5V tolerant. Operation is from a single 3.30.3V supply. The AS7C3512 is packaged in all high volume industry standard packages. Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND Power dissipation Storage temperature (plastic) Temperature under bias DC output current Symbol VCC VIN PD Tstg Tbias Iout Min -0.5 -0.5 - -55 -10 - Max +4.6 +6.0 1.0 +150 +85 20 Unit V V W o C o C mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 H X L L L CE2 X L H H H Key: X = Don't Care, L = LOW, H = HIGH 2 WE X X H H L OE X X H L X Data High Z High Z High Z Dout Din Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable Read Write AS7C3512 AS7C3512L Recommended operating conditions Parameter Symbol VCC GND VIH VIL Supply voltage Input voltage (Ta = 0C to +70C) Min 3.0 0.0 2.0 -0.5 Typ 3.3 0.0 - Max 3.6 0.0 5.5 0.8 Unit V V V V VIL min = -2.0V for pulse width less than tRC/2. DC operating characteristics1 Parameter Input leakage current (VCC = 3.30.3V, GND = 0V, Ta = 0C to +70C) -12 Min Max Symbol Test conditions VCC = Max, |ILI| Vin = GND to VCC -15 Min Max -20 Min Max -25 Min Max -35 Min Max Unit - 1 - 1 - 1 - 1 - 1 A - 1 - 1 - 1 - 1 - 1 A CE1 = VIH or CE2 = VIL, Output leakage current |ILO| VCC = Max, Operating power supply current ICC CE1 = VIL, CE2 = VIH, f = fmax, Iout = 0 mA - 70 - 65 - 60 - 55 - 50 mA ISB CE1 = VIH or CE2 = VIL, f = fmax - 30 - 25 - 20 - 20 - 15 mA - 2.5 - 2.5 - 2.5 - 2.5 - 2.5 mA - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 mA - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - - 2.4 0.4 - V V Standby power supply current Output voltage Vout = GND to VCC ISB1 VOL VOH CE1 VCC-0.2V or CE2 0.2V, Vin 0.2V or Vin VCC-0.2V, f=0 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min L Shaded areas contain advance information. Capacitance2 Parameter Input capacitance I/O capacitance (f = 1 MHz, Ta = Room temperature, VCC = 3.3V) Symbol CIN CI/O Signals A, CE1, CE2, WE, OE I/O Test conditions Vin = 0V Vin = Vout = 0V Max 5 7 Unit pF pF 3 AS7C3512 AS7C3512L Read cycle3,9,12 (VCC = 3.30.3V, GND = 0V, Ta = 0C to +70C) Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time Output hold from address change Chip enable (CE1) to output in Low Z Chip enable (CE2) to output in Low Z Chip disable (CE1) to output in High Z Chip disable (CE2) to output in High Z Output enable to output in Low Z Output disable to output in High Z Chip enable to power up time Chip disable to power down time -12 Min Max 12 - - 12 - 12 - 12 - 3 3 - 3 - 3 - - 3 - 3 0 - - 3 0 - - 12 Symbol tRC tAA tACE1 tACE2 tOE tOH tCLZ1 tCLZ2 tCHZ1 tCHZ2 tOLZ tOHZ tPU tPD -15 Min Max 15 - - 15 - 15 - 15 - 4 3 - 3 - 3 - - 4 - 4 0 - - 4 0 - - 15 -20 Min Max 20 - - 20 - 20 - 20 - 5 3 - 3 - 3 - - 5 - 5 0 - - 5 0 - - 20 -25 Min Max 25 - - 25 - 25 - 25 - 6 3 - 3 - 3 - - 6 - 6 0 - - 6 0 - - 25 -35 Min Max 35 - - 35 - 35 - 35 - 8 3 - 3 - 3 - - 8 - 8 0 - - 8 0 - - 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 3 3, 12 3, 12 5 4, 5, 12 4, 5, 12 4, 5, 12 4, 5, 12 4, 5 4, 5 4, 5, 12 4, 5, 12 Shaded areas contain advance information Read waveform 13,6,7,9,12 Address controlled tRC Address tAA AAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA Dout tOH Data Valid Read waveform 23,6,8,9,12 CE1 and CE2 controlled 1 tRC CE1 CE2 AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A OE AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tOE AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA tOLZ tOHZ tCHZ1, tCHZ2 tACE1, tACE2 Dout tCLZ1, tCLZ2 Supply Current 4 tPU AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAAAAAAAAAAAA Data Valid tPD 50% 50% ICC ISB AS7C3512 AS7C3512L Write cycle11,12 (VCC = 3.30.3V, GND = 0V, Ta = 0C to +70C) -12 -15 -20 -25 -35 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Write cycle time tWC 12 - 15 - 20 - 25 - 30 - ns Chip enable (CE1) to write end tCW1 10 - 12 - 12 - 15 - 20 - ns 12 Chip enable (CE2) to write end tCW2 10 - 12 - 12 - 15 - 20 - ns 12 Address setup to write end tAW 10 - 12 - 12 - 15 - 20 - ns Address setup time tAS 0 - 0 - 0 - 0 - 0 - ns Write pulse width tWP 8 - 9 - 12 - 15 - 17 - ns Address hold from end of write tAH 0 - 0 - 0 - 0 - 0 - ns Data valid to write end tDW 6 - 8 - 10 - 12 - 15 - ns Data hold time tDH 0 - 0 - 0 - 0 - 0 - ns Write enable to output in High Z tWZ - 5 - 5 - 5 - 5 - 5 ns 4, 5 Output active from write end tOW 3 - 3 - 3 - 3 - 3 - ns 4, 5 Write waveform 110,11,12 Unit Notes 12 4, 5 WE controlled tWC tAW tAH Address WE tAS tWP AAAAAAAAA AAAA AAAAAAAA AAAAA A AAAA AAAAAAAA AAAAA A tDW Din tDH Data Valid tWZ tOW Dout Write waveform 210,11,12 CE1 and CE2 controlled tWC tAW tAH Address tAS tCW1, tCW2 CE1 CE2 AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA tWZ Din Dout AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA tWP WE AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA tDW tDH Data Valid AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAAAAAAAAAAAAA AAA 5 AS7C3512 AS7C3512L Data retention characteristics Parameter VCC for data retention Data retention current L Chip deselect to data retention time Operation recovery time Input leakage current Symbol VDR Test Conditions ICCDR CE1 VCC-0.2V or CE2 0.2V Min 2.0 - - 0 tRC - VCC = 2.0V tCDR tR | ILI | Vin VCC-0.2V or Vin 0.2V Max - 1200 250 - - 1 Unit V A A ns ns A Data retention waveform Data Retention Mode VCC VDR 2.0V 3.0V 3.0V tCDR tR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VDR AAAAAAAAAAAAAAAAAAAAAAAAAAA CE1AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIH AAAAAAAAAAAAAAAAAAAAAAAAAAA VIH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AC test conditions * Output load: see Figure B, except for tCLZ and tCHZ see Figure C. * Input pulse level: GND to 3.0V. See Figure A. * Input rise and fall times: 5 ns. See Figure A. * Input and output timing reference levels: 1.5V. Thevenin equivalent: 168 Dout +1.72V +3.3V +3.3V 320 +3.3V GND Dout 90% 10% 90% 10% Figure A: Input Waveform 350 320 Dout 30 pF* GND Figure B: Output Load 350 *including scope GND and jig capacitance Figure C: Output Load for tCLZ, tCHZ Notes 1 2 3 4 5 6 7 8 9 10 11 12 6 5 pF* During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed but not tested. WE is HIGH for read cycle. CE1 and OE are LOW and CE2 is HIGH for read cycle. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. All read cycle timings are referenced from the last valid address to the first transitioning address. CE1 or WE must be HIGH or CE2 LOW during address transitions. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. AS7C3512 AS7C3512L Typical DC and AC characteristics 1.4 0.6 0.4 ISB 0.2 0.0 3.0 Normalized access time tAA vs. supply voltage VCC Normalized access time Ta = 25C 1.0 0.9 3.3 Supply voltage (V) Output source current IOH vs. output voltage VOH VCC = 3.3V Ta = 25C 30 20 10 1.65 Output voltage (V) 3.3 1 0.2 -10 35 80 125 Ambient temperature (C) Normalized supply current I CC vs. cycle frequency 1/t RC, 1/tWC 1.4 1.2 VCC = 3.3V 1.0 0.9 VCC = 3.3V Ta = 25C 1.2 0.8 0.6 0.4 0.2 0.0 10 35 80 85 Ambient temperature (C) 0 20 40 60 Cycle frequency (MHz) 80 Typical access time change tAA vs. output capacitive loading Output sink current IOL vs. output voltage VOL 35 60 30 VCC = 3.3V Ta = 25C 40 30 20 10 0 0.0 5 -55 Normalized access time tAA vs. ambient temperature Ta 1.1 50 VCC = 3.30V 25 10 35 60 85 Ambient temperature (C) 1.2 70 40 0 0.0 1.3 625 0.04 1.4 0.8 -15 3.6 60 50 ISB 0.4 1.5 1.1 70 0.6 0.0 -15 3.6 1.2 0.8 3.0 Output source current (mA) 3.3 Supply voltage (V) 1.4 1.3 0.8 0.2 Output sink current (mA) Normalized access time 1.5 Normalized ISB1 (log scale) 0.8 ICC 1.0 Normalized supply current ISB1 vs. ambient temperature Ta Normalized ICC 1.0 1.2 ICC Normalized ICC, ISB Normalized ICC, ISB 1.2 Normalized supply current ICC, ISB vs. ambient temperature Ta Change in tAA (ns) 1.4 Normalized supply current ICC, ISB vs. supply voltage VCC VCC = 3.3V 25 20 15 10 5 0 1.65 Output voltage (V) 3.3 0 250 500 750 Capacitance (pF) 1000 7 AS7C3512 AS7C3512L Ordering information Package \ Access Time 12 ns 15 ns 20 ns 25 ns 35 ns Plastic DIP, 300 mil AS7C3512-12PC AS7C3512L-12PC AS7C3512-15PC AS7C3512L-15PC AS7C3512-20PC AS7C3512L-20PC AS7C3512-25PC AS7C3512L-25PC AS7C3512-35PC AS7C3512L-35PC Plastic SOJ, 300 mil AS7C3512-12JC AS7C3512L-12JC AS7C3512-15JC AS7C3512L-15JC AS7C3512-20JC AS7C3512L-20JC AS7C3512-25JC AS7C3512L-25JC AS7C3512-35JC AS7C3512L-35JC Shaded areas contain advance information. Part numbering system AS7C 3 SRAM prefix Blank 3 512 = 5V supply = 3.3V supply -XX X Access time Package: P J Device number C = PDIP 300 mil = SOJ 300 mil Commercial temperature range, 0C to 70 C Representatives, distributors, and sales offices DOMESTIC REPS KANSAS ALABAMA CenTech (816) 358-8100 Concord Component (205) 772-8883 ARKANSAS Southern States Marketing (214) 238-7500 CALIFORNIA North Brooks Technical (415) 960-3880 LA Area Competitive Tech. (714) 450-0170 San Diego ATS (619) 634-1488 COLORADO KENTUCKY CC Electro Sales (317) 921-5000 LOUISIANA Electro Tech (610) 272-2125 ERA Associates (516) 543-0510 (713) 895-8533 MAINE Upstate Kitchen & Kutchin (617) 229-2660 DELAWARE MICHIGAN (607) 722-3580 Concord Component (919) 846-3441 Midwest Marketing Assoc. Micro-Electronic Comp. Dayton Deerfield Beach D. A. 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The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion(R) and the Alliance logo are registered trademarks of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders. 3099 North First Street Printed in U.S.A. ALLIANCE SEMICONDUCTOR San Jose, CA 95134 Tel (408) 383-4900 Fax (408) 383-4999 Copyright (c) 1996 All rights reserved. www.alsc.com June 1996